CN102609235B - Method and system for updating data after data reading of double-port RAM (random-access memory) - Google Patents

Method and system for updating data after data reading of double-port RAM (random-access memory) Download PDF

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CN102609235B
CN102609235B CN201110027241.1A CN201110027241A CN102609235B CN 102609235 B CN102609235 B CN 102609235B CN 201110027241 A CN201110027241 A CN 201110027241A CN 102609235 B CN102609235 B CN 102609235B
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fifo
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CN102609235A (en
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徐心明
刘伟达
王红旗
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Sanechips Technology Co Ltd
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ZTE Corp
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Abstract

The invention discloses a method for updating data after data reading of a double-port RAM (random-access memory), which includes steps of preparing for caching write address signals and write data signals which are to be written into the double-port RAM by the aid of an FIFO (first-in first-out) cache source port before triggering write enable signals of the FIFO cache source port; preparing for caching read address signals and read data signals which are to be read out from the double-port RAM through an FIFO cache destination port before triggering the write enable signals of the FIFO cache destination port; and building chip select signals by null marking signals of the FIFO cache source port and null marking signals of the FIFO cache destination port, and writing data in the FIFO cache source port and the FIFO cache destination port into the double-port RAM in a time sharing manner. The invention further discloses a system for updating data after data reading of the double-port RAM. The method and the system for updating data after data reading of the double-port RAM can meet requirements for data updating after data reading process of the double-port RAM.

Description

Method and system for updating data after data reading of dual-port RAM
Technical Field
The present invention relates to a technology for updating data in a dual port Random Access Memory (RAM), and more particularly, to a method and system for updating data after reading data in a dual port RAM.
Background
Dual port RAM is a commonly used storage element in digital designs and can be applied to any of the following three cases: (1) storing the data; (2) data is transmitted in a mode of writing in by a source end and reading out by a destination end; (3) and completing the clock domain conversion from the source end to the destination end.
However, in digital design, when the control function is completed, it is often a combination of the above three cases, that is: the source end and the destination end work in different clock domains, data are written into the dual-port RAM from the source end, and the data are read out by the destination end and then are used. For the comprehensive application of the three cases, in order to meet the different data updating requirements of the first data reading and the second data reading, the destination terminal is required to read data from the dual-port RAM, process the data and write the data into the same dual-port RAM. At present, the prior art does not have a good solution to the data update requirement.
Disclosure of Invention
In view of the above, the present invention provides a method and a system for updating data after reading data by a dual port RAM, which can satisfy the data updating requirement after reading data by the dual port RAM.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a method for updating data after data is read by a dual port RAM, which comprises the following steps:
when a write enable signal of a first-in first-out (FIFO) cache source end is not triggered, the FIFO cache source end is used for carrying out cache preparation on a write address signal and a write data signal to be written into a dual-port Random Access Memory (RAM);
when the write enable signal of the FIFO cache destination end is not triggered, the FIFO cache destination end is used for carrying out cache preparation on a read address signal and a read data signal which are to be read out of the dual-port RAM;
and constructing a chip selection signal by using the empty mark signal of the FIFO cache source end and the empty mark signal of the FIFO cache destination end, and writing the data in the FIFO cache source end and the FIFO cache destination end into the dual-port RAM in a time-sharing manner.
Wherein, the method also comprises: when a write enable signal of the FIFO cache source end is triggered, a write address signal of the dual-port RAM and a write data signal of the dual-port RAM are pieced together to form a write data signal of the FIFO cache source end;
and when the write enable signal of the FIFO cache destination end is triggered, splicing the read address signal of the dual-port RAM and the read data signal of the dual-port RAM into a write data signal of the FIFO cache destination end.
Wherein, the method also comprises: and splicing the read address signal of the dual-port RAM and a read data signal formed by data processing of the read data signal of the dual-port RAM into a write data signal of an FIFO cache destination.
Before the data in the FIFO cache source end and the FIFO cache destination end are written into the dual-port RAM in a time-sharing manner, the method further comprises the following steps: and performing time-sharing reading on the FIFO cache source end and the FIFO cache destination end according to the constructed chip selection signal.
The time-sharing reading of the FIFO cache source end and the FIFO cache destination end according to the constructed chip selection signal specifically comprises the following steps:
performing AND operation on the chip selection signal formed by inverting and summing the empty mark signal of the FIFO cache source end, and taking the operation result as a read enabling signal of the FIFO cache source end;
after the empty mark signal of the FIFO cache destination end is inverted, carrying out AND operation with the inverted signal of the constructed chip selection signal, and taking the operation result as a read enable signal of the FIFO cache destination end;
reading the FIFO cache source end when the FIFO cache source end read enable signal is effective; and reading the destination end of the FIFO buffer when the read enable signal of the destination end of the FIFO buffer is effective.
Wherein, the method also comprises: delaying the constructed chip selection signal, the read enabling signal of the FIFO cache source end and the read enabling signal of the FIFO cache destination end respectively, performing time-sharing gating on the delayed read enabling signal of the FIFO cache source end and the delayed read enabling signal of the FIFO cache destination end, and taking a gating result as a write enabling signal of the dual-port RAM;
the time-sharing writing of the data in the FIFO buffer source end and the FIFO buffer destination end into the dual-port RAM specifically includes:
reading an FIFO cache source end, and writing data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache source end when the write enable signal of the dual-port RAM is effective;
and reading the FIFO cache destination end, and writing the data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache destination end when the write enable signal of the dual-port RAM is effective.
A system for updating data after reading data by a dual port RAM, the system comprising: the device comprises an FIFO cache source end, an FIFO cache destination end and a chip selection unit; wherein,
the FIFO cache source end is used for performing cache preparation for a write address signal and a write data signal to be written into the dual-port RAM when a write enable signal of the FIFO cache source end is not triggered;
the FIFO cache destination is used for making cache preparation for a read address signal and a read data signal which are to be read out of the dual-port RAM when a write enable signal of the FIFO cache destination is not triggered;
and the chip selection unit is used for constructing a chip selection signal by using the empty mark signal of the FIFO cache source end and the empty mark signal of the FIFO cache destination end, and writing the data in the FIFO cache source end and the FIFO cache destination end into the dual-port RAM in a time-sharing manner.
The FIFO cache source end is further used for piecing a write address signal of the dual-port RAM and a write data signal of the dual-port RAM into a write data signal of the FIFO cache source end when a write enable signal of the FIFO cache source end is triggered;
the FIFO cache destination is further configured to, when the write enable signal of the FIFO cache destination is triggered, piece together the read address signal of the dual-port RAM and the read data signal of the dual-port RAM into a write data signal of the FIFO cache destination.
The FIFO cache destination is further configured to combine the read address signal of the dual-port RAM and the read data signal formed by data processing of the read data signal of the dual-port RAM into a write data signal of the FIFO cache destination.
The chip selection unit is further configured to perform and operation on the chip selection signal formed by inverting and summing the empty flag signal of the FIFO buffer source, and use an operation result as a read enable signal of the FIFO buffer source; after the empty mark signal of the FIFO cache destination end is inverted, carrying out AND operation with the inverted signal of the constructed chip selection signal, and taking the operation result as a read enable signal of the FIFO cache destination end; and delaying the constructed chip selection signal, the read enabling signal of the FIFO cache source end and the read enabling signal of the FIFO cache destination end respectively, performing time-sharing gating on the delayed read enabling signal of the FIFO cache source end and the delayed read enabling signal of the FIFO cache destination end, and taking a gating result as a write enabling signal of the dual-port RAM.
The chip selection unit is further used for reading the FIFO cache source end when the FIFO cache source end read enable signal is valid, reading the FIFO cache source end and writing data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache source end when the dual-port RAM write enable signal is valid; and reading the FIFO cache destination end when the read enable signal of the FIFO cache destination end is effective, reading the FIFO cache destination end and writing data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache destination end when the write enable signal of the dual-port RAM is effective.
When the write enable signal of a First-In First-Out (FIFO) cache source end is not triggered, the FIFO cache source end is used for performing cache preparation on a write address signal and a write data signal to be written into a dual-port RAM; when the write enable signal of the FIFO cache destination end is not triggered, the FIFO cache destination end is used for carrying out cache preparation on a read address signal and a read data signal which are to be read out of the dual-port RAM; and constructing a chip selection signal by using the empty mark signal of the FIFO cache source end and the empty mark signal of the FIFO cache destination end, and writing the data in the FIFO cache source end and the FIFO cache destination end into the dual-port RAM in a time-sharing manner. The invention adopts the FIFO buffer source end and the FIFO buffer destination end to regulate the cross-clock domain transmission data of the source end and the destination end, adopts the chip selection unit to time-divisionally read the FIFO buffer source end and the FIFO buffer destination end and time-divisionally write the read data into the dual-port RAM, thereby meeting the data updating requirement after the dual-port RAM reads the data in the comprehensive application situation of the three situations.
Drawings
FIG. 1 is a signaling diagram of data update according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the chip select unit based signaling of FIG. 1;
FIG. 3 is a schematic diagram of an embodiment of the data processing unit in FIG. 1 for data processing.
Detailed Description
According to the scheme of the invention, when the source end and the destination end work in different clock domains, namely the source end and the destination end transmit data across the clock domains, the source end can write the data into the dual-port RAM, the destination end can read the data from the dual-port RAM, and the data can be written into the same dual-port RAM again after the data is read by the destination end through data processing, so that the data updating requirement after the data is read by the dual-port RAM is met.
A method for updating data after reading data by a dual-port RAM mainly comprises the following steps:
the method comprises the steps of using an FIFO cache source end as a data input cache source end of a dual-port RAM, using the FIFO cache source end under the action of a write enable signal of the non-triggered FIFO cache source end to prepare for caching a write address signal and a write data signal to be written into the dual-port RAM, and splicing the write address signal of the dual-port RAM and the write data signal into the write data signal of the FIFO cache source end under the action of the write enable signal of the triggered FIFO cache source end.
Here, the first part specifically includes:
1. setting the depth of the FIFO buffer source end to be more than or equal to 2, and setting the width of the FIFO buffer source end to be equal to the sum of the bit width of the write address signal bus and the bit width of the write data signal bus entering the dual-port RAM.
Here, it should be noted that: the FIFO is a first-in first-out data buffer, and can only write data in sequence, and read data in sequence, the data address of the data is completed by adding 1 automatically by an internal read-write pointer, and a certain specified address cannot be read or written by an address line as a common memory. Especially between two different clock domains, a FIFO can be used as a data buffer. With respect to the depth of the FIFO, the depth of the FIFO refers to: how many N bits of data a FIFO can store (if the width of the FIFO is N), such as an 8-bit FIFO, which can store 8 bits of data if the depth is 8; the depth is 12, 12 data with 8 bits can be stored, the depth of the FIFO can be large or small, and the calculation of the depth of the FIFO has no fixed formula. In the actual operation of the FIFO, the full/empty flag of its data can control the writing or reading of data. In terms of FIFO width, the FIFO width refers to: FIFO is a data bit of read-write operation, the width of FIFO is fixed in monolithic finished IC, there is also optional, if FPGA realizes a FIFO by itself, its data bit, namely the width can be defined by itself.
2. And the write enable signal of the source end of the dual-port RAM is taken as the write enable signal of the FIFO buffer source end, and the write address signal and the write data signal of the source end of the dual-port RAM are spliced into the write data signal of the FIFO buffer source end.
3. And connecting the read enable signal, the read data signal and the empty mark signal of the FIFO buffer source end to the chip selection unit.
And secondly, using the FIFO cache destination end as a data input cache destination end of the dual-port RAM, using the FIFO cache destination end to perform cache preparation for read address signals and read data signals of the dual-port RAM to be read under the action of a write enable signal of the non-triggered FIFO cache destination end, and splicing the read address signals and the read data signals of the dual-port RAM into write data signals of the FIFO cache destination end under the action of a write enable signal of the triggered FIFO cache destination end. Furthermore, the read data signals of the dual-port RAM read address signals and the read data signals after data processing by the data processing unit can be spliced into the write data signals of the FIFO buffer destination.
Here, the second part specifically includes:
1. setting the depth of the FIFO buffer destination end to be more than or equal to 2, and the width of the FIFO buffer source end to be equal to the sum of the bit width of the read address signal bus of the RAM and the bit width of the read data signal bus after the data processing of the read data signal.
2. The read enable signal of the destination end of the dual-port RAM is delayed and then used as a write enable signal of the FIFO cache destination end, and the delay time length is equal to the read delay period of the RAM. If the read delay of the dual port RAM itself is 0, the delay time length here is 0. And splicing the read address signal and the read data signal of the dual-port RAM into a data writing signal of an FIFO buffer destination end by data processing.
3. And connecting the read enable signal, the read data signal and the empty mark signal of the destination end of the FIFO buffer to the chip selection unit.
And thirdly, constructing chip selection signals by using the empty mark signals of the FIFO buffer source end and the FIFO buffer destination end so as to write the data in the FIFO buffer source end and the FIFO buffer destination end into the dual-port RAM in a time-sharing manner.
The third part specifically includes:
1. the chip selection signal is constructed by utilizing the empty mark signals of the FIFO buffer source end and the FIFO buffer destination end, and the chip selection principle for constructing the chip selection signal can be set according to actual requirements.
2. And performing time-sharing reading on the FIFO cache source end and the FIFO cache destination end according to the chip selection signal. After the null mark signal of the FIFO buffer source end is inverted, carrying out AND operation with the chip selection signal, and taking the result as a read enable signal of the FIFO buffer source end; and the result of the AND operation of the empty mark signal at the destination end of the FIFO buffer and the negation signal of the chip select signal is used as the read enable signal at the destination end of the FIFO buffer.
3. And respectively delaying the chip selection signal, the read enable signal of the FIFO cache source end and the read enable signal of the FIFO cache destination end, wherein the delay time length is equal to the read delay period of the FIFO cache source end and the FIFO cache destination end. The method comprises the following steps: the FIFO buffer source end and the FIFO buffer destination end have the same delay period. And time-sharing gating the delayed FIFO buffer source end read enabling signal and the delayed FIFO buffer destination end read enabling signal by using the delayed chip selection signal, wherein the gating result is used as a write enabling signal of the dual-port RAM.
4. According to the arrangement relation of the addresses and the data of the dual-port RAM in the data writing signals of the first part of the FIFO cache source end, when the read enabling signals of the FIFO cache source end are effective, the addresses and the data information of the dual-port RAM are obtained, and when the write enabling signals of the dual-port RAM are effective, the data are written into the dual-port RAM according to the addresses; according to the arrangement relation of the addresses and the data of the dual-port RAM in the data writing signals of the second part of the FIFO cache destination end, when the reading enabling signals of the FIFO cache destination end are effective, the addresses and the data information of the dual-port RAM are obtained, and when the writing enabling signals of the dual-port RAM are effective, the data are written into the dual-port RAM according to the addresses. The delayed chip select signal can be used for time-sharing chip selection for the two processes.
A system for updating data after reading data by a dual-port RAM mainly comprises the following contents:
the system comprises: the device comprises an FIFO cache source end, an FIFO cache destination end and a chip selection unit; the FIFO buffer source end is used for performing buffer preparation for a write address signal and a write data signal to be written into the dual-port RAM when a write enable signal of the FIFO buffer source end is not triggered. The FIFO buffer destination is used for preparing buffer for read address signals and read data signals to be read out of the dual-port RAM when the write enable signals of the FIFO buffer destination are not triggered. The chip selection unit is used for constructing a chip selection signal by using the empty mark signal of the FIFO cache source end and the empty mark signal of the FIFO cache destination end, and writing data in the FIFO cache source end and the FIFO cache destination end into the dual-port RAM in a time-sharing manner.
The FIFO buffer source is further configured to, when the write enable signal of the FIFO buffer source is triggered, piece together the write address signal of the dual-port RAM and the write data signal of the dual-port RAM into the write data signal of the FIFO buffer source. The FIFO cache destination is further used for piecing the read address signal of the dual-port RAM and the read data signal of the dual-port RAM into a write data signal of the FIFO cache destination when triggering the write enable signal of the FIFO cache destination.
The FIFO buffer destination is further used for splicing the read address signal of the dual-port RAM and the read data signal formed by data processing of the read data signal of the dual-port RAM into the write data signal of the FIFO buffer destination.
The chip selection unit is further used for performing AND operation on the chip selection signal obtained by inverting and constructing the empty mark signal of the FIFO cache source end, and taking the operation result as a read enable signal of the FIFO cache source end; after the empty mark signal of the FIFO cache destination end is inverted, carrying out AND operation with the inverted signal of the constructed chip selection signal, and taking the operation result as a read enable signal of the FIFO cache destination end; and delaying the constructed chip selection signal, the read enabling signal of the FIFO cache source end and the read enabling signal of the FIFO cache destination end respectively, performing time-sharing gating on the delayed read enabling signal of the FIFO cache source end and the delayed read enabling signal of the FIFO cache destination end, and taking a gating result as a write enabling signal of the dual-port RAM.
The chip selection unit is further configured to read the FIFO buffer source end when the FIFO buffer source end read enable signal is valid, read the FIFO buffer source end and write data into the dual-port RAM according to the address and the arrangement relationship of the data in the FIFO buffer source end when the dual-port RAM write enable signal is valid; and reading the FIFO cache destination end when the read enable signal of the FIFO cache destination end is effective, reading the FIFO cache destination end and writing data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache destination end when the write enable signal of the dual-port RAM is effective.
The present invention is described below by way of example, and for the sake of simplicity, the dual port RAM is simply referred to as RAM.
The method comprises the following steps: the FIFO1 is used as a FIFO buffer source in this embodiment, and the FIFO2 is used as a FIFO buffer destination in this embodiment, and is used in cooperation with source and destination clock domain crossing data transmission by the RAM.
As shown in fig. 1, the present embodiment includes the following steps:
step 101, using the FIFO buffer source (FIFO1) as the data input buffer source of the RAM, that is: data is not written for the moment, and is only written under the action of a write enable signal that triggers the FIFO 1.
That is, the write address signal 12 and the write data signal 11 to be written to RAM are prepared using the FIFO1 under the write enable signal of the TRIGGER FIFO1, and the write data signal of the FIFO1 is pieced together with the write address signal 12 and the write data signal 11 of RAM under the write enable signal of the TRIGGER FIFO 1.
Here, the processing procedure of this step specifically includes the following steps:
step 1011, setting the depth of the FIFO1 to be greater than or equal to 2; the data bit width of the FIFO1, referred to simply as the width of the FIFO1, is equal to the sum of the write address signal 12 bus bit width and the write data signal 11 bus bit width of the RAM.
Step 1012, using the write enable signal 13 at the source end of the RAM as the write enable signal of the FIFO1, and using the write address signal 12 and the write data signal 11 of the RAM to be pieced together to form the write data signal of the FIFO 1. So that the write address signal 12 and the write data signal 11 of the RAM are only pieced together into the FIFO1 write data signal to write data under the write enable signal of the flip-flop FIFO 1.
Step 1013 couples the read enable signal 32, read data signal 33, and empty flag signal 31 of the FIFO1 to the chip select unit.
Step 102, using the FIFO buffer destination (FIFO2) as the data input buffer destination of the RAM, that is: data is not written for the moment, and is only written under the action of a write enable signal that triggers the FIFO 2.
That is, under the action of the write enable signal of the non-trigger FIFO2, the FIFO2 is used to prepare the read address signal 62 and the read data signal 21 after data processing of the read data signal 61 to be read out from the RAM, and under the action of the write enable signal of the trigger FIFO2, the write data signal of the FIFO2 is formed by splicing the read data signal 21 after data processing of the read address signal 62 and the read data signal 61 from the RAM. It should be noted here that the write data signal of FIFO2 can also be pieced together with the RAM read address signal 62 and the read data signal 61 by the write enable signal of flip-flop FIFO2 using the FIFO buffer source under the write enable signal of the flipflop FIFO2 in preparation for the read address signal 62 and the read data signal 61 to be read out from RAM.
Here, the processing procedure of this step includes the steps of:
step 1021, setting the depth of the FIFO2 to be more than or equal to 2; the data bit width of the FIFO2, which is abbreviated as FIFO2, is equal to the sum of the bus bit width of the read address signal 62 of the RAM and the bus bit width of the read data signal 21 after data processing of the read data signal 61.
In step 1022, the read enable signal 63 at the destination of the RAM is delayed to serve as the write enable signal 23 of the FIFO2, with the delay time equal to the read delay period of the RAM itself. If the read delay of the RAM itself is 0, the delay time length here is 0. The read data signals 21 after data processing with the read address signals 62 and the read data signals 61 of the RAM are pieced together to form the write data signals of the FIFO 2. Fig. 3 is a schematic diagram of data processing performed by the data processing unit of this embodiment, and the purpose of performing data processing is to clear 0 a partial bit (bit) of data.
Step 1023 couples the read enable signal 42, read data signal 43, and empty flag signal 41 of the FIFO2 to the chip select unit.
Step 103 uses the empty flag signal 31 of the FIFO1 and the empty flag signal 41 of the FIFO2 to form chip select signals to time-share the data read by the read data signal 33 in the FIFO1 and the data read by the read data signal 43 in the FIFO2 into the RAM.
Here, as shown in fig. 2, the processing procedure of this step includes the steps of:
and step 1031, constructing the chip selection signal 61 by using the empty flag signal 31 of the FIFO1 and the empty flag signal 41 of the FIFO2, wherein a chip selection principle can be set according to actual requirements, an example of the chip selection principle is shown in table 1, and table 1 is a schematic table of the chip selection principle.
TABLE 1
Step 1032, time-sharing reading is performed on the FIFOs 1 and 2 according to the chip select signal 61.
Here, the signal 34 formed by inverting the empty flag signal 31 of the FIFO1 is and-operated with the chip select signal 61, and the result is the read enable signal 32 of the FIFO 1; the signal 44 obtained by inverting the empty flag signal 41 of the FIFO2 and the inverted signal 62 of the chip select signal 61 are anded, and the result is the read enable signal 42 of the FIFO 2.
Step 1033 delays the chip select signal 61, the read enable signal 32 from FIFO1, and the read enable signal 42 from FIFO2 by a time period equal to the read delay period of FIFOs 1 and 2, respectively. The method comprises the following steps: FIFO1 and FIFO2 have the same delay period. The delayed FIFO1 read enable signal 35 and the delayed FIFO2 read enable signal 45 are time-divisionally strobed with the delayed chip select signal 63, strobing the result as the write enable signal 51 for the RAM.
Step 1034, according to the arrangement relation of the RAM address and the data in the FIFO1 write data signal of step 101, when the FIFO1 read enable signal 32 is valid, obtaining the RAM address 33-1 and the data information 33-2, and when the RAM write enable signal 51 is valid, writing the data 33-2 into the RAM according to the address 33-1; according to the arrangement relationship of the RAM address and the data in the FIFO2 write data signal of the step 102, when the FIFO2 read enable signal 42 is valid, the RAM address 43-1 and the data information 43-2 are obtained, and when the RAM write enable signal 51 is valid, the data 43-2 is written into the RAM according to the address 43-1. The delayed chip select signal 63 may be used for time-shared chip selection for both processes.
The embodiment of the system is as follows: as shown in fig. 1, the system of the present embodiment includes: FIFO1, FIFO2, chip select unit, dual port RAM and data processing unit.
The FIFO1 serves as a FIFO buffer source, the FIFO1 is configured to prepare for the write address signal 12 and the write data signal 11 to be written into the RAM by using the FIFO1 under the action of the write enable signal of the nonfrigger FIFO1, and to piece together the write data signal of the FIFO1 with the write address signal 12 and the write data signal 11 of the RAM under the action of the write enable signal of the toggle FIFO 1. Here, the depth of the FIFO1 is 2 or more; the data bit width of the FIFO1, referred to simply as the width of the FIFO1, is equal to the sum of the write address signal 12 bus bit width and the write data signal 11 bus bit width of the RAM. The write enable signal 13 at the source of the RAM is used as the write enable signal of the FIFO1, and the write address signal 12 and the write data signal 11 of the RAM are spliced into a FIFO1 write data signal.
The FIFO2 is used as a destination of the FIFO buffer, the FIFO2 is used for preparing the read address signal 62 to be read out from the RAM and the read data signal 21 after the read data signal 61 is data processed by using the FIFO2 under the action of the write enable signal of the unfired FIFO2, and the write data signal of the FIFO2 is pieced by the read address signal 62 from the RAM and the read data signal 21 after the read data signal 61 is data processed by using the write enable signal of the triggered FIFO 2. It should be noted here that the write data signal of FIFO2 can also be pieced together with the RAM read address signal 62 and the read data signal 61 by the write enable signal of flip-flop FIFO2 using the FIFO buffer source under the write enable signal of the flipflop FIFO2 in preparation for the read address signal 62 and the read data signal 61 to be read out from RAM. Here, the depth of the FIFO2 is set to 2 or more; the data bit width of the FIFO2, which is abbreviated as FIFO2, is equal to the sum of the bus bit width of the read address signal 62 of the RAM and the bus bit width of the read data signal 21 after data processing of the read data signal 61. The read enable signal 63 at the destination of the RAM is delayed as the write enable signal 23 for the FIFO2 for a length of time equal to the read delay period of the RAM itself. If the read delay of the RAM itself is 0, the delay time length here is 0. The read data signals 21 after data processing with the read address signals 62 and the read data signals 61 of the RAM are pieced together to form the write data signals of the FIFO 2.
The schematic diagram of data processing performed by the data processing unit is shown in fig. 3, and is used for forming a read data signal 21 after data processing is performed on a read data signal 61, and the purpose of the data processing is to clear 0 a part of bit of data.
The chip select cell is used to connect the read enable signal 32, the read data signal 33 and the empty flag signal 31 of the FIFO1 to the chip select cell, and in the case of connecting the read enable signal 42, the read data signal 43 and the empty flag signal 41 of the FIFO2 to the chip select cell, the data read out by the read data signal 33 in the FIFO1 and the data read out by the read data signal 43 in the FIFO2 are time-divisionally written into the RAM by using the empty flag signal 31 of the FIFO1 and the empty flag signal 41 of the FIFO2 to constitute the chip select signal.
Here, as shown in fig. 2, the chip select unit uses the empty flag signal 31 of the FIFO1 and the empty flag signal 41 of the FIFO2 to construct the chip select signal 61, and when time-sharing reading is performed on the FIFO1 and the FIFO2 according to the chip select signal 61, the and operation is performed on the signal 34 formed by inverting the empty flag signal 31 of the FIFO1 and the chip select signal 61, and the result is the read enable signal 32 of the FIFO 1; the signal 44 obtained by inverting the empty flag signal 41 of the FIFO2 and the inverted signal 62 of the chip select signal 61 are anded, and the result is the read enable signal 42 of the FIFO 2. The chip select signal 61, the read enable signal 32 of the FIFO1, and the read enable signal 42 of the FIFO2 are delayed by a time period equal to the read delay period of the FIFOs 1 and 2, respectively. The method comprises the following steps: FIFO1 and FIFO2 have the same delay period. The delayed FIFO1 read enable signal 35 and the delayed FIFO2 read enable signal 45 are time-divisionally strobed with the delayed chip select signal 63, strobing the result as the write enable signal 51 for the RAM. According to the arrangement relation of the RAM address and the data in the FIFO1 write data signal in the step 101, when the FIFO1 read enable signal 32 is effective, the RAM address 33-1 and the data information 33-2 are obtained, and when the RAM write enable signal 51 is effective, the data 33-2 are written into the RAM according to the address 33-1; according to the arrangement relationship of the RAM address and the data in the FIFO2 write data signal of the step 102, when the FIFO2 read enable signal 42 is valid, the RAM address 43-1 and the data information 43-2 are obtained, and when the RAM write enable signal 51 is valid, the data 43-2 is written into the RAM according to the address 43-1. The delayed chip select signal 63 may be used for time-shared chip selection for both processes.
In summary, by using the FIFO buffer address and data, the present invention can satisfy various requirements of the same clock domain design and the cross clock domain design, thereby expanding the application range. In addition, the invention has good expansibility and provides connection reference for the fan-in of a plurality of source ends.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (9)

1. A method for updating data after data is read by a dual-port RAM (random access memory), which is characterized by comprising the following steps:
when a write enable signal of a first-in first-out (FIFO) cache source end is not triggered, the FIFO cache source end is used for carrying out cache preparation on a write address signal and a write data signal to be written into a dual-port Random Access Memory (RAM); when a write enable signal of the FIFO cache source end is triggered, a write address signal of the dual-port RAM and a write data signal of the dual-port RAM are pieced together to form a write data signal of the FIFO cache source end;
when the write enable signal of the FIFO cache destination end is not triggered, the FIFO cache destination end is used for carrying out cache preparation on a read address signal and a read data signal which are to be read out of the dual-port RAM; when a write enable signal of the FIFO cache destination end is triggered, a read address signal of the dual-port RAM and a read data signal of the dual-port RAM are spliced into a write data signal of the FIFO cache destination end;
and constructing a chip selection signal by using the empty mark signal of the FIFO cache source end and the empty mark signal of the FIFO cache destination end, and writing the data in the FIFO cache source end and the FIFO cache destination end into the dual-port RAM in a time-sharing manner.
2. The method of claim 1, further comprising: and splicing the read address signal of the dual-port RAM and a read data signal formed by data processing of the read data signal of the dual-port RAM into a write data signal of an FIFO cache destination.
3. The method of claim 2, wherein before time-sharing the data in the FIFO buffer source and the FIFO buffer destination into the dual port RAM, the method further comprises: and performing time-sharing reading on the FIFO cache source end and the FIFO cache destination end according to the constructed chip selection signal.
4. The method according to claim 3, wherein said time-sharing reading the FIFO buffer source and the FIFO buffer destination according to the constructed chip select signal specifically comprises:
performing AND operation on the chip selection signal formed by inverting and summing the empty mark signal of the FIFO cache source end, and taking the operation result as a read enabling signal of the FIFO cache source end;
after the empty mark signal of the FIFO cache destination end is inverted, carrying out AND operation with the inverted signal of the constructed chip selection signal, and taking the operation result as a read enable signal of the FIFO cache destination end;
reading the FIFO cache source end when the FIFO cache source end read enable signal is effective; and reading the destination end of the FIFO buffer when the read enable signal of the destination end of the FIFO buffer is effective.
5. The method of claim 4, further comprising: delaying the constructed chip selection signal, the read enabling signal of the FIFO cache source end and the read enabling signal of the FIFO cache destination end respectively, performing time-sharing gating on the delayed read enabling signal of the FIFO cache source end and the delayed read enabling signal of the FIFO cache destination end, and taking a gating result as a write enabling signal of the dual-port RAM;
the time-sharing writing of the data in the FIFO buffer source end and the FIFO buffer destination end into the dual-port RAM specifically includes:
reading an FIFO cache source end, and writing data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache source end when the write enable signal of the dual-port RAM is effective;
and reading the FIFO cache destination end, and writing the data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache destination end when the write enable signal of the dual-port RAM is effective.
6. A system for updating data after reading data from a dual port RAM, the system comprising: the device comprises an FIFO cache source end, an FIFO cache destination end and a chip selection unit; wherein,
the FIFO cache source end is used for performing cache preparation for a write address signal and a write data signal to be written into the dual-port RAM when a write enable signal of the FIFO cache source end is not triggered; when a write enable signal of the FIFO cache source end is triggered, a write address signal of the dual-port RAM and a write data signal of the dual-port RAM are pieced together to form a write data signal of the FIFO cache source end;
the FIFO cache destination is used for making cache preparation for a read address signal and a read data signal which are to be read out of the dual-port RAM when a write enable signal of the FIFO cache destination is not triggered; when a write enable signal of the FIFO cache destination end is triggered, a read address signal of the dual-port RAM and a read data signal of the dual-port RAM are spliced into a write data signal of the FIFO cache destination end;
and the chip selection unit is used for constructing a chip selection signal by using the empty mark signal of the FIFO cache source end and the empty mark signal of the FIFO cache destination end, and writing the data in the FIFO cache source end and the FIFO cache destination end into the dual-port RAM in a time-sharing manner.
7. The system of claim 6, wherein the FIFO buffer destination is further configured to combine the read address signal of the dual port RAM and the read data signal formed by data processing the read data signal of the dual port RAM into the write data signal of the FIFO buffer destination.
8. The system of claim 7, wherein the chip select unit is further configured to perform an and operation on the chip select signal obtained by inverting and constructing the empty flag signal at the FIFO buffer source end, and taking the operation result as the read enable signal at the FIFO buffer source end; after the empty mark signal of the FIFO cache destination end is inverted, carrying out AND operation with the inverted signal of the constructed chip selection signal, and taking the operation result as a read enable signal of the FIFO cache destination end; and delaying the constructed chip selection signal, the read enabling signal of the FIFO cache source end and the read enabling signal of the FIFO cache destination end respectively, performing time-sharing gating on the delayed read enabling signal of the FIFO cache source end and the delayed read enabling signal of the FIFO cache destination end, and taking a gating result as a write enabling signal of the dual-port RAM.
9. The system of claim 8, wherein the chip select unit is further configured to read the FIFO buffer source port when the FIFO buffer source port read enable signal is valid, read the FIFO buffer source port, and write data into the dual-port RAM according to the address and the arrangement relationship of the data in the FIFO buffer source port when the dual-port RAM write enable signal is valid; and reading the FIFO cache destination end when the read enable signal of the FIFO cache destination end is effective, reading the FIFO cache destination end and writing data into the dual-port RAM according to the address and the data arrangement relation in the FIFO cache destination end when the write enable signal of the dual-port RAM is effective.
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