CN1479383A - 半导体装置及其制造方法 - Google Patents
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Abstract
一种半导体装置及其制造方法,提高高耐压MOS晶体管的静电破坏耐量。在MOS晶体管的N+型漏层(9)下不形成N-型漏层(11),且在N+型漏层(9)下的区域形成P+型埋入层(11)。在N+型漏层(9)和P+型埋入层(11)之间形成高浓度的PN结。即,局部形成结耐压小的区域。因此,在栅极(6)下的N-型漏层(2)热破坏前,浪涌电流通过该PN结逃逸到硅衬底1。其结果可提高ESD耐量。
Description
技术领域
本发明涉及半导体装置,特别是涉及半导体集成电路上内装的高耐压MOS晶体管。
背景技术
高耐压MOS晶体管具有高源漏耐压(BVDS)或高栅耐压,其应用于LCD激励器、EL激励器或电源电路等上。
图9是显示现有例的N沟道型高耐压MOS晶体管结构的剖面图。在P型硅衬底100的表面形成栅氧化膜101和厚的场氧化膜102。而后,形成由栅氧化膜101延伸到邻接的场氧化膜102的局部上的栅极103。在该栅极103的一端邻接的硅衬底100的表面区域形成N+型源层104。另外,与栅极103的另一端分离,在半导体衬底100的表面形成N+型漏层105。
在该N+型漏层105和栅极103的另一端之间,在硅衬底1的表面区域(偏移区域)形成N-漏层106。N-型漏层106比N+型漏层105更深地扩散,扩散到由场氧化膜102的下方至栅极103的一端的区域。
根据所述高耐压MOS晶体管结构,通过设置N-型漏层106,在漏层106上施加高电压时,通过耗尽层在N-型漏层106中扩展,而缓和了漏极电场,故可得到高的源漏耐压。另外,栅极103由于自栅氧化膜101延伸到邻接的场氧化膜102的一部分上,故具有抵抗栅氧化膜103的破坏的牢固结构。
但是,根据本发明者的实验,在所述现有晶体管结构中有静电破坏耐量(耐受度,以下称ESO耐量)低的问题。例如,根据基于人体模型的一般静电破坏试验(容量100pF、电阻1.5kΩ)有500V左右的ESD耐量,这是不充分的值。
发明内容
因此,本发明者分析了现有晶体管的静电破坏的原因,判明了:浪涌电流集中在栅极103下的N-型漏层106(图9中A部分)上,该部分被热破坏的现象。
因此,本发明如图3(a)所示,在N+型漏层9下不形成N-型漏层2,且N+型漏层9下的区域形成P+型埋入层11。因此,在N+型漏层9和P+型埋入层11之间形成PN结。局部形成结耐压小的区域。由此,在栅极6下的N-型漏层2热破坏前,浪涌电流由N+型漏层9逃逸到硅衬底1。其结果可提高ESD耐量。
附图说明
图1是显示本发明第一实施形态的半导体装置及其制造方法的剖面图;
图2是显示本发明第一实施形态的半导体装置及其制造方法的剖面图;
图3是显示本发明第一实施形态的半导体装置及其制造方法的剖面图;
图4是显示用于形成P+型埋入层11的所述离子注入工序中硼(11B+)的剂(dose)量和最小源漏耐压BVDSmin的关系的图;
图5是显示用于形成P+型埋入层11的所述离子注入工序中硼(11B+)的剂量和ESD耐量的关系的图;
图6是显示本发明第二实施形态的半导体装置及其制造方法的剖面图;
图7是显示本发明第二实施形态的半导体装置及其制造方法的剖面图;
图8是显示本发明第二实施形态的半导体装置及其制造方法的剖面图;
图9是显示现有例的半导体装置的剖面图。
具体实施方式
下面,参照附图说明本发明第一实施形态的半导体装置及其制造方法。
首先,如图1(a)所示,通过在P型硅衬底1表面进行离子注入、热扩散形成N-型漏层2A、2B。N-型漏层2A、2B之间分离。即,由于使用规定的掩模,在该分离区域不注入离子,故不形成N-型漏层。在此,P型硅衬底1的杂质浓度为大约1×1015/cm3。另外,离子注入是以剂量4×1015/cm2的条件将例如磷(11P+)注入P型硅衬底1。另外,热扩散的条件为例如1100℃、N2氛围气。其结果,N-型漏层2A、2B扩散至约1.2μm深度。
其次,如图1(b)所示,使用LOCOS(硅的局部氧化,Local Oxidation ofSilicon)法,在N-型漏层2A、2B的表面分别形成厚的场氧化膜4A、4B。场氧化膜4A、4B一般用于元件分离,但在该半导体装置中用于提高高耐压晶体管的耐压。其膜厚根据目标耐压而不同,为300nm~600nm左右。然后,除去厚的场氧化膜4A、4B,在硅衬底1的表面区域形成栅氧化膜3。其膜厚也因晶体管栅极耐压的目标耐压而不同,为15nm~100nm左右。厚的场氧化膜4A、4B具有比栅氧化膜3厚很多的膜厚。
然后,如图1(c)所示,通过LPCVD法整面堆积多晶硅层5,并扩散磷等杂质,形成低电阻化。
接着,如图2(a)所示,使用未图示的光致抗蚀剂选择性蚀刻多晶硅层5,并形成栅极6。栅极6蚀刻为由栅氧化膜3延伸至邻接的场氧化膜4A的一部分上。
然后,如图2(b)所示,形成N+型源层8及N+型漏层9。该工序形成在N-型漏层2A、2B之间具有开口的光致抗蚀剂层7,且以该光致抗蚀剂层7为掩膜进行离子注入。该离子注入例如在剂量4×1015/cm2、加速能量40kev的条件下注入砷(75As+),而后,在剂量4×1015/cm2、加速能量40kev的条件下注入磷(31P+)。即N+型源层8及N+型漏层9由砷(75As+)和磷(31P+)两种N型杂质形成。通过其后的热处理,磷(31P+)比砷(75As+)更深地扩散,故在源漏耐压的提高方面有效果。
其次,如图2(c)所示,除去光致抗蚀剂层7后,再通过掩膜曝光及显影形成另外的光致抗蚀层10。该光致抗蚀层10具有比光致抗蚀层7更小的开口。即,将比N+型漏层9的离子注入区域更内侧的区域设定为注入区域。而后,将光致抗蚀层10作为掩膜,在剂量4×1012/cm2、加速能量160kev的条件下注入例如硼(11B+)。
由此,在比N+型漏层9更深的区域形成P+型埋入层11。因为如上所述设定离子注入区域,所以P+型埋入层11和N-型漏层2A、2B难于重叠。由此,N-型漏层2A、2B的杂质浓度不受影响,可高精度控制P+型埋入层11的杂质浓度,ESD耐量的控制变得容易。
其次,如图3(a)所示,除去光致抗蚀剂层10,并在800℃进行N+型源层8及N+型漏层9的退火。
而后,如图3(b)所示,作为层间绝缘膜,通过CVD法堆积BPSG膜12。其后,在N+型源层8及N+型漏层9上形成接触孔,并在N+型源层8上形成源极13,在N+型漏层9上形成漏极14。
根据这样完成的半导体装置,在N型漏层9下不形成N-型漏层2,且在N+型漏层9下的区域形成P+型埋入层11。在N+型漏层9和P+型埋入层11之间形成高浓度的PN结。即,局部形成结耐压小的区域。由此,在栅极6下的N-型漏层2热破坏前,浪涌电流通过该PN结逃逸到硅衬底。其结果可提高ESD耐量。
图4是显示为形成P+型埋入层11在所述离子注入工序中硼(11B+)的剂量和最小源漏耐压BVDSmin的关系的图。在此,最小源漏耐压BVDSmin是晶体管包含动作中时最低的源漏耐压。一般地,N沟道型MOS晶体管的源漏耐压显示栅电压依存性,且对应源漏极间电流的流动状态,在某栅电压时最小。如图4所示,在硼(11B+)剂量为0~4×1012/cm2的范围内,最小源漏耐压BVDSmin大致一定是36V。
图5是显示为形成P+型埋入层11在所述离子注入工序中硼(11B+)的剂量和ESD耐量的关系的图。ESD耐量在硼(11B+)的剂量为0时是800V。即使此时与现有例相比,ESD耐量也提高了,在硼(11B+)的剂量是4×1012/cm2时,实验确认提高到2700V。
下面,参照附图说明本发明第二实施形态的半导体装置及其制造方法。另外,对和第一实施形态的图1~图3同一构成部分赋予同一符号。
首先,如图6(a)所示,在P型硅衬底1的表面形成N-型漏层2。与第一实施形态不同的点是,N-型漏层2是不具有分离区域的点。其它的工艺条件和第一实施形态完全相同。
然后,如图6(b)所示,形成栅氧化膜3、场氧化膜4A、4B。而后,如图6(c)所示,整面形成多晶硅层5。至此的工序也和第一实施形态完全相同。
接着,如图7(a)所示,在N-型漏层2上形成光致抗蚀剂层20,并在剂量4×1015/cm2、加速能量40kev的条件下注入例如砷(75As+),形成N+型源层21。
其次,如图7(b)所示,在除去光致蚀刻剂层20后,形成另外的光致抗蚀剂层22,并在N+型漏层23的形成预定区域设置开口部。而后,由该开口部以剂量4×1015/cm2、加速能量40kev的条件注入例如砷(75As+),其后,由剂量4×1015/cm2、加速能量40kev的条件注入磷(31P+)。即,N+型漏层23由砷(75As+)和磷(31P+)两种N型杂质形成。在其后的热处理中,由于磷(31P+)比砷(75As+)扩散得深,故对源漏耐压提高有效果。
接着,自相同的光致抗蚀刻层22的开口部,在加速能量160kev的条件下注入硼(11B+),从而在N+型漏层23下的区域形成P+埋入层24。
在本实施形态中,由于N-型漏层2向N+型漏层23下的区域扩展,故为了使P+型埋入层24的浓度和第一实施形态的相同,故必须进一步增加所述硼的剂量。
其次,如图7(c)所示,除去光致抗蚀剂层22,并例如在800℃进行退火。由此,N+型漏层23、P+型埋入层24扩散。在此,为了使浪涌电流迅速逃逸到硅衬底1,最好使P+型埋入层24扩散,并与P型硅衬底1接触。
而后,如图8所示,作为层间绝缘膜采用VCD法堆积BPSG膜12。其后,在N+型源层21及N+型漏层23上形成接触孔,并在N+型源层21上形成源极13,在N+型漏层23上形成漏极14。
这样,根据本实施形态,由于在N+型漏层23下的区域形成P+型埋入层24,所以在N+型漏层23和P+型埋入层24之间形成高浓度的PN结。即,局部形成结耐压小的区域。由此,在栅极6下的N-型漏层2热破坏前,浪涌电流通过该PN结,逃逸到硅衬底1。其结果和第一实施形态相同,有望提高ESD耐量。
另外,在所述实施形态中,说明了N沟道型MOS晶体管,但本发明对P沟道型MOS晶体管也同样可以适用。
根据本发明,在MOS晶体管的N+型漏层9下不形成N-型漏层2,且在N+型漏层9下的区域形成P+型埋入层11。因此,可提高ESD耐压。另外,将P+型埋入层11形成用的离子注入量适当地设定,可不降低晶体管最小源漏耐压,将ESD耐量至少提高到2700V。
Claims (5)
1.一种半导体装置,其特征在于,包括:第一导电型半导体衬底;在该半导体衬底的表面配置的栅绝缘膜;在该栅绝缘膜上配置的栅极;邻接于该栅极的一端,并配置在所述半导体衬底的表面的第二导电型的源层;自所述栅极的另一端离开,配置在所述半导体衬底的表面的第二导电型的高浓度漏层;在该高浓度漏层和所述栅极的另一端之间,配置在所述半导体衬底的表面的第二导电型的低浓度漏层;在比所述高浓度漏层更深的区域配置的与该高浓度漏层构成PN结的第一导电型埋入层。
2.如权利要求1所述的半导体装置,其特征在于,在所述低浓度漏层的表面配置比所述栅绝缘膜更厚的绝缘膜,所述栅极延伸在该厚的氧化膜的一部分上。
3.一种半导体装置的制造方法,其特征在于,包括:在第一导电型半导体衬底的表面形成第二导电型的低浓度漏层的工序;在所述半导体衬底的表面形成栅绝缘膜的工序;在该栅绝缘膜上、与所述低浓度的漏层邻接,形成栅极的工序;与所述低浓度的漏层邻接,在由所述栅极离开的所述半导体衬底的表面形成第二导电型的高浓度漏层的工序;在比所述高浓度漏层更深的位置形成与该高浓度漏层构成PN结的第一导电型埋入层的工序。
4.一种半导体装置的制造方法,其特征在于,包括:在第一导电型半导体衬底的表面形成第二导电型低浓度漏层的工序;在该低浓度漏层的表面形成场氧化膜的工序;在所述半导体衬底的表面形成栅绝缘膜的工序;形成自该栅绝缘膜上延伸至所述场氧化膜的一部分上的栅极的工序;在与所述低浓度漏层邻接,自所述栅极离开的所述半导体衬底的表面形成第二导电型的高浓度漏层的工序;在比所述高浓度漏层更深的位置形成与该高浓度漏层构成PN结的第一导电型的埋入层的工序。
5.一种半导体装置的制造方法,其特征在于,包括:在第一导电型的半导体衬底表面形成第二导电型低浓度漏层的工序;在该低浓度漏层的表面形成场氧化膜的工序;在所述半导体衬底的表面上形成栅绝缘膜的工序;形成自该栅绝缘上延伸至所述场氧化膜的一部分上的栅极的工序;在与所述低浓度漏层接触,并自所述栅极离开的所述半导体衬底的表面为了形成第二导电型的高浓度漏层而进行第一离子注入的工序;在所述高浓度漏层的离子注入区域内侧的区域,在比所述高浓度漏层的离子注入区域更深的区域,为了形成第一导电型埋入层而进行第二离子注入的工序。
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US8541848B2 (en) * | 2011-10-12 | 2013-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-voltage MOSFETs having current diversion region in substrate near fieldplate |
US8907432B2 (en) * | 2012-02-10 | 2014-12-09 | Richtek Technology Corporation | Isolated device and manufacturing method thereof |
US9559170B2 (en) * | 2012-03-01 | 2017-01-31 | X-Fab Semiconductor Foundries Ag | Electrostatic discharge protection devices |
US9177953B2 (en) * | 2013-10-31 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Limited | Circular semiconductor device with electrostatic discharge (ESD) device and functional device |
CN106158921B (zh) * | 2015-04-10 | 2019-07-23 | 无锡华润上华科技有限公司 | 具resurf结构的横向扩散金属氧化物半导体场效应管 |
JP2017092297A (ja) * | 2015-11-12 | 2017-05-25 | ソニー株式会社 | 電界効果トランジスタ、および半導体装置 |
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US20040051158A1 (en) | 2004-03-18 |
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