CN1433083A - 双重扩散型mosfet及其半导体装置 - Google Patents
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Abstract
本发明提供一种L-DMOSFET。其中包括:由形成在半导体基板(11)上的N型半导体层构成的漏极区域(13)、由形成在漏极区域(13)内的P型半导体区域构成的底盘区域(15)、形成在底盘区域(15)内的N型源极区域(16)和形成在底盘区域(15)表面上的栅极电极(21),其特征在于:在漏极区域(13)内形成N+型漏极接触区域(18)和P+型区域(19),并使该两区域的电位相等。从而,不会降低L-DMOSFET的本来的特性,并且不需增大元件面积便可实现高的抗静电击穿耐压。
Description
技术领域
本发明涉及横向双重扩散型MOSFET及其装置,特别是关于抗静电击穿耐压高、导通阻抗低的横向双重扩散型MOSFET的结构。
背景技术
作为一种一般在100伏特以下的较低电压范围内使用的IC或分立FET,有被称为L-DMOS的横向双重扩散型MOSFET。它可通过通常的扩散工序形成,并由于不同于纵向双重扩散型MOSFET,所有的端子全可以从芯片的上面引出,所以适合于IC化,尤其是被广泛地使用在要求导通阻抗低的用途上。
图5是表示以往的横向双重扩散型MOSFET的立体剖面图。该横向双重扩散型MOSFET(以下表示为L-DMOSFET)在P型半导体基板101上,通过N+型埋入区域102,使N型3半导体层外延生长,从而形成漏极区域103。然后,在漏极区域103上通过扩散N型杂质而形成N+型漏极接触区域104,再通过扩散P型杂质而形成底盘区域105。在底盘区域105的表面部上,与底盘区域105的外缘相隔一定间隔地形成N+型源极区域106,并且在N+型源极区域106的内侧形成P+型区域107。在N+型源极区域106与N+型漏极接触区域104之间形成漂移沟道区域。而且,通过栅极氧化膜设置覆盖从N+型源极区域106的外缘部到漂移沟道区域的内缘部的表面部分的栅极电极。
这种L-DMOSFET,与通常的MOSFET比较,由于其不仅耐压高,而且导通阻抗(动作阻抗)低,所以广泛地使用在达数伏~100伏的很宽的电压范围内,尤其是广泛地使用在电源IC和电机驱动装置等中。
但是,如图6所示的等效电路那样,在L-DMOSFET中存在着寄生NPN晶体管(由漏极区域103、底盘区域105和N+型源极区域106所构成的NPN结构),而该寄生NPN晶体管,会成为阻碍进行本来的各种正常动作的原因。
特别是,在以漏极开放方式使用该L-DMOSFET的情况下,当输出端子(漏极)被施加有外部的静电电压时,由于没有把该静电电压旁路掉的路径,所以全部电流都流入L-DMOSFET的内部。此时,由于寄生NPN晶体管进行对应于温度的正反馈动作,使电流集中流过因制造上的偏差而形成的薄弱部分,从而容易使元件损坏。
为了提高该破坏耐量,进行了如降低寄生晶体管的增益,或附加保护电路等的试验。但是,当降低了寄生晶体管的增益后,会导致L-DMOSFET的特性劣化,而如果附加保护电路,会增加了芯片的面积。
另一方面,作为静电感应非常强的元件,一般有如图7,所示结构的绝缘栅型双极晶体管(以下用IGBT表示)。如图7所示,IGBT的结构是,把图5所示的L-DMOSFET的N+型漏极接触区域104置换成P+型漏极接触区域110。
在IGBT中存在有如图8所示那样的寄生闸流晶体管(由漏极区域103、底盘区域105和N+型源极区域106构成的NPN型晶体管及由底盘区域105、漏极区域103和P+型漏极接触区域110构成的PNP型晶体管)。当有如静电那样的形成过大的电流时,寄生闸流晶体管导通,能够以极低的动作阻抗处理该过大的电流,所以IGBT具有极高的抗静电击穿耐压。
IGBT由于是通过从在漏极区域(集电极)103上扩散P型杂质而形成P+型漏极接触区域110向漏极区域103注入的空穴改变漏极区域103的传导度来降低其阻抗成分,所以一般是作为漂移长度(d)比较长的耐压在100伏以上的高耐压元件使用,然而由于是击穿型元件,所以不能够充分减少漂移长度,因此几乎不能在100伏以下的较低电压范围内使用。特别是在IC中,集成L-DMOSFET看不出好的效果,因此,在IC中不会考虑使用IGBT。
另外,由于IGBT的上升初期的Vf(顺方向电压)值的损失大,所以在低电流域的导通阻抗比L-DMOSFET高,存在着各种不利的情况。而且,由于在大电流域容易引起寄生闸流晶体管的闭锁,所以必须要注意使用条件。并且,在动作时由于有少量的载流子的存在,所以其频率特性也比L-DMOSFET差,这一点已被公认为是IGBT的重大缺点。
如上所述,以往的L-DMOSFET虽然具有易于实现高耐压化并且导通阻抗低的优点,而另一方面却存在着抗静电击穿耐压低的缺点。另外,虽然IGBT具有极高的抗静电击穿耐压,但却存在着与L-DMOSFET比较不适于高度的集成,在低电流域的导通阻抗高、频率特性差等的各种缺点。
发明内容
本发明就是为了解决上述的问题,目的在于提供一种不丧失L-DMOSFET原来的特性、而且不增大元件的面积的可实现高抗静电击穿耐压的L-DMOSFET及使用给L-DMOSFET的半导体装置。
为了达到上述的目的,本发明的L-DMOSFET,包括:由形成在半导体基板上的N型半导体层构成的漏极区域、由形成在所述漏极区域内的P型半导体区域构成的底盘区域、形成在所述底盘区域内的N型源极区域和在所述底盘区域表面上通过介入栅极绝缘膜而形成的栅极电极,其特征在于:在所述漏极区域内,具有形成在漏极区域表面上的N+型漏极接触区域、及与所述N+型漏极接触区域电连接成具有相等电位的P+型区域。
根据这样的构成,通过在漏极区域内使N+型漏极接触区域与P+型区域的电位相同,在L-DMOSFET中形成寄生PNP晶体管,从而形成由该PNP晶体管与本来存在的寄生NPN晶体管共同构成寄生闸流晶体管的结构。
根据这样的构成,由于N+型漏极接触区域与P+型区域的电位相等,所以在通常的动作时,可以使寄生闸流晶体管不形成导通。
因此,根据本发明的L-DMOSFET,由于不需要降低寄生NPN晶体管的增益,所以不会降低L-DMOSFET本来的特性,而且由于不需要设置用于提高破坏耐量的保护电路,所以不需增大元件的面积便可实现高的抗静电击穿耐压。
在本发明的L-DMOSFET中构成了所形成的与所述N+型漏极接触区域相接触的漏极电极一直延伸到所述P型区域的表面,所述N+型漏极接触区域与P型区域形成电接触的结构。
根据这样的构成,通过该漏极电极使所述N+型漏极接触区域与P型区域形成电接触,只需调整电极的长度便可容易地形成相同的电位。
理想的是,所述N+型漏极接触区域形成梳齿状,所述P性区域形成在所述梳齿间的区域内。
即,理想的是,把所述N+型漏极接触区域沿着所述N型源极区域等间隔地形成多处切口,在该切口的部分上设置所述P+型区域。
更理想的是,所述N+型漏极接触区域形成梳齿位于栅极侧的梳齿状。
根据这样的构成,通过把P+型区域设置在N+型漏极接触区域内,可容易地形成寄生闸流晶体管。
理想的是,所述P型区域的位于所述底盘区域侧的端部比所述N+型漏极接触区域的位于所述底盘区域侧的端部更远离所述底盘区域。
根据这样的构成,即使具有与以往的L-MOSFET相同的漂移长度,也能够确保充分高的击穿耐压。从而可在不增加元件面积、维持以往的L-MOSFET特性的状态下,大幅地提高静电破坏耐压。
所述P+型区域也可以形成在被所述N+型漏极接触区域所包围的区域内。
根据这样的构成,由于不仅可容易地形成寄生闸流晶体管,并且P型区域的位于所述底盘区域侧的端部形成比所述N+型漏极接触区域的位于所述底盘区域侧的端部更远离(收进)所述底盘区域的状态,所以,即使具有与以往的L-MOSFET相同的漂移长度,也能够确保充分高的击穿耐压。从而可在不增加元件面积、维持以往的L-MOSFET特性的状态下,大幅地提高静电破坏耐压。
理想的是,所述P型区域及所述N+型漏极接触区域形成在所述漏极区域内的N缓冲层内。
根据这样的构成,可进一步提高击穿耐压,进一步降低导通阻抗。
另外,本发明的半导体装置,是通过把上述构成的本发明的L-DMOSFET与其他元件共同集成而构成。
即,其特征是,包括:由形成在半导体基板上的N型半导体层构成的漏极区域;由形成在所述漏极区域内的P型半导体区域构成的底盘区域;形成在所述底盘区域内的N型源极区域;在所述底盘区域表面上通过介入栅极绝缘膜而形成的栅极电极;在所述漏极区域内的,形成在漏极区域表面上的N+型漏极接触区域、及与所述N+型漏极接触区域电连接成具有相等电位的P+型区域;从N+型漏极接触区域一直延伸到所述P型区域表面的漏极电极;及与所述N源极区域形成接触的源极电极。
理想的是,使源极电极一直延伸到所述P型底盘区域的表面。
根据这样的构成,通过改变与其他元件共同集成的L-DMOSFET的漂移长度和P+型区域的收进长度,可容易地对该L-DMOSFET的击穿电压进行调整,因此,可把其击穿电压调整成与其他元件的耐压相同,从而可获得具有作为其他元件的保护元件的L-DMOSFET的半导体装置。
附图说明
图1是表示本发明一实施例的双重扩散型MOSFET的立体剖面图。
图2是图1所示的双重扩散型KOSFET的等效电路图。
图3是表示本发明其他实施例的双重扩散型MOSFET的立体剖面图。
图4是表示本发明的半导体装置的构成例的电路图。
图5是表示以往的双重扩散型MOSFET的立体剖面图。
图6是图5所示的以往的双重扩散型MOSFET的等效电路图。
图7是表示绝缘栅性双极性晶体管的立体剖面图。
图8是图7所示的绝缘栅性双极性晶体管的立体剖面图。
图中:10-横向双重扩散型MOSFET,11-P型半导体基板,12-N+型埋入区域,13-漏极区域(N型半导体层),14-N-缓冲层,15-底盘区域,16-N+型源极区域,17-P+型区域,18-N+型漏极接触区域,19-P+型区域,22-漏极电极,23-源极电极,25-半导体装置,26-元件。
具体实施方式
下面,参照附图,对本发明的L-DMOSFET进行说明。
图1是表示本发明一实施例的L-DMOSFET的立体剖面图。该L-MOSFET在P型半导体基板11上通过在N+型埋入区域12的介入下使N型半导体层外延成长而形成漏极区域13。然后通过在该漏极区域13上扩散N型杂质而形成N-缓冲层14,再通过扩散P型杂质,形成底盘区域15。
在底盘区域15的表面部上,与底盘区域15的外缘留出一定的间隙地形成N+型源极区域16,并且在N+型源极区域16的内侧形成P+型区域17。在N-缓冲层14内使N+型漏极接触区域18与P+型区域19相互接触,并沿着N+型源极接触区域16形成相互交叉的配置。在N+型源极区域16与N-缓冲层14之间形成漂移沟道区域20。
而且,通过栅极氧化膜设置覆盖从N+型源极区域16外缘部到沟道区域20内缘部的表面部分的栅极电极21。为了使其与N+型漏极接触区域18接触所形成的漏极电极22使N+型漏极接触区域18与P+型区域19保持相互相同的电位。源极电极23跨在N+型源极区域16和P+型区域17之上。
把N+型漏极接触区域18沿着N型源极区域等间隔地切割出多处切口,把P+型区域19设置在该切口的部分上。而且,P+型区域19的配置形状为,使其位于该底盘区域15侧的端部比N+型漏极接触区域18的位于底盘区域15侧的端部,从底盘区域15向后收进例如约1.0μm。
如上所述,在漏极区域13内,通过使N+型漏极接触区域18与P+型区域19相互接触,在L-MOSFET10中形成寄生PNP型晶体管,该PNP晶体管与原本存在的寄生NPN型晶体管构成了寄生闸流晶体管。
因此,根据该L-MOSFET10,由于不降低寄生NPN晶体管的增益,所以不会损失L-MOSFET本来的特性,而且,由于不需要设置用于提高破坏耐量的保护电路等,所以,不需增大元件面积便可获得高的抗静电击穿耐压。
而且,通过使P+型区域19形成从底盘区域15比N+型漏极接触区域18向分离侧收进配置状态,可提高在源极-漏极之间的因扩展的过度层到达P+型区域19而引起击穿的击穿耐压。
而且,通过构成由N-缓冲层14覆盖N+型漏极接触区域18和P+型区域19的结构,可抑制过度层向漏极侧逐渐延伸,因此,可进一步提高漏极区域侧的P+型区域19的击穿耐压。除此之外,通过构成由N-缓冲层14覆盖N+型漏极接触区域18的结构,可完全祢补因把漏极侧的N+型漏极接触区域18形成带有梳齿状切口的结构所导致的导电性的下降。
图2表示该L-DMOSFET10的等效电路。如图2所示,由于构成L-DMOSFET10的寄生闸流晶体管的PNP晶体管在发射极与基极之间形成短路,所以通常不动作。因此,该L-DMOSFET10在导通时可进行与以往的L-DMOSFET相比没有任何变化的动作,即使在大电流域也不需担心有寄生闸流晶体管的存在。而且,根据同样的理由,不会造成像IGBT那样的在上升时的Vf损失,并可确保在低电流域的低的电流阻抗。
而且,由于构成使漏极电极22一直延伸到N-缓冲层14的表面的结构,使得漏极侧的P+型区域19与漏极区域13形成同一电位,所以不会像IGBT那样形成从P+型区域19的空穴注入。因此,该L-DMOSFET10的开关速度(频率特性)与以往的L-DMOSFET相比也没有任何改变。
但是,该L-DMOSFET10当一度被加载静电电压时,该大电压把寄生闸流晶体管的PNP晶体管强制击穿,使寄生闸流晶体管开始动作,因此,能够以极低的导通阻抗处理非常强大的电流,从而可大幅提高抗静电击穿耐压。
根据本实施例所构成的L-DMOSFET10,不需要使用任何新的制造技术,而且不会损失以往的L-DMOSFET的特性,可将抗静电击穿耐压例如以人体模特为例,可从以往的1.5kV左右的抗静电击穿耐压大幅地提高到3~10倍的4.5~15kV。
图3是表示本发明其他实施例的L-DMOSFET的立体剖面图。本实施例不是采用把漏极侧N+型漏极接触区域18等间隔地切割成具有多处切口的结构,而是采用把N+型漏极接触区域18等间隔地形成多处挖口的结构,通过在该挖口部分上埋入P+型区域19,在被N+型漏极接触区域18保卫的区域内形成P+型区域19。根据图3所示的构成,同样可获得图1所示的实施例的L-DMOSFET的效果。
图4是表示本发明的半导体装置的构成例的电路图。该半导体装置25是通过把上述构成的L-DMOSFET10与其他元件26集成而构成。
根据该构成,通过改变与其他元件26共同集成的L-DMOSFET10的漂移长度d和P+型区域19的收进长度,可简单地调节L-DMOSFET10的击穿耐压,因此,通过简单的调节,可把L-DMOSFET10作为适合其他元件26的耐压的保护元件加以利用。
如上所述,根据本发明的双重扩散型MOSFET,通过在该漏极区域内形成N+型漏极接触区域和P+型区域,并使两者的电位相互相等,由此形成寄生闸流晶体管,由于不需要降低寄生NPN晶体管的增益,所以不会降低L-DMOSFET的本来的特性,并由于不需要设置用于提高破坏耐量的保护电路,所以不需增大元件的面积,便可获得高的抗静电击穿耐压。
另外,本发明的半导体装置由于把本发明的横向双重扩散型MOSFET作为内部电路(或内部元件)的保护元件使用,所以可实现高的抗静电击穿耐压。
Claims (8)
1.一种双重扩散型MOSFET,包括:由形成在半导体基板上的N型半导体层构成的漏极区域、由形成在所述漏极区域内的P型半导体区域构成的底盘区域、形成在所述底盘区域内的N型源极区域和在所述底盘区域表面上通过介入栅极绝缘膜而形成的栅极电极,其特征在于:在所述漏极区域内,具有形成在漏极区域表面上的N+型漏极接触区域、及与所述N+型漏极接触区域电连接成具有相等电位的P+型区域。
2.根据权利要求1所述的双重扩散型MOSFET,其特征在于:所形成的与所述N+型漏极接触区域相接触的漏极电极一直延伸到所述P型区域的表面。
3.根据权利要求1或2所述的双重扩散型MOSFET,其特征在于:所述N+型漏极接触区域形成梳齿状,所述P性区域形成在所述梳齿间的区域内。
4.根据权利要求1或2所述的双重扩散型MOSFET,其特征在于:所述N+型漏极接触区域形成梳齿位于栅极侧的梳齿状,所述P型区域形成在所述梳齿之间的区域内。
5.根据权利要求1至3中任意一项所述的双重扩散型MOSFET,其特征在于:所述P型区域的位于所述底盘区域侧的端部比所述N+型漏极接触区域的位于所述底盘区域侧的端部更远离所述底盘区域。
6.根据权利要求1或2所述的双重扩散型MOSFET,其特征在于:所述P型区域形成在被所述N+型漏极接触区域所包围的区域内。
7.根据权利要求1至6中任意一项所述的双重扩散型MOSFET,其特征在于:所述P型区域及所述N+型漏极接触区域形成在所述漏极区域内的N缓冲层内。
8.一种半导体装置,其特征在于:包括:由形成在半导体基板上的N型半导体层构成的漏极区域;由形成在所述漏极区域内的P型半导体区域构成的底盘区域;形成在所述底盘区域内的N型源极区域;在所述底盘区域表面上通过介入栅极绝缘膜而形成的栅极电极;在所述漏极区域内的,形成在漏极区域表面上的N+型漏极接触区域、及与所述N+型漏极接触区域电连接成具有相等电位的P+型区域;从N+型漏极接触区域一直延伸到所述P型区域表面的漏极电极;及与所述N源极区域形成接触的源极电极。
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EP1331672A2 (en) | 2003-07-30 |
JP2003218348A (ja) | 2003-07-31 |
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CN100349302C (zh) | 2007-11-14 |
DE60319899T2 (de) | 2009-04-09 |
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US6914298B1 (en) | 2005-07-05 |
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