CN1425797A

CN1425797A - Process for chemical vapor phase depositing titaniam nitride containing silicon using titanium containing organic metal material

Info

Publication number: CN1425797A
Application number: CN 03114707
Authority: CN
Inventors: 徐小诚; 缪炳有
Original assignee: Shanghai Huahong Group Co Ltd
Current assignee: Shanghai Huahong Group Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date: 2003-01-02
Filing date: 2003-01-02
Publication date: 2003-06-25
Anticipated expiration: 2023-01-02
Also published as: CN100345999C

Abstract

The CVD process of depositing TiSiN film for integrated circuit manufacture includes He carrying of Ti containing TDMA and Si containing trimethyl silane or SiCH4, heat decomposition to deposit TiSiN film, and in-situ RE H2-N2 plasma treatment. The TiSiN film thus deposited has excellent step coverage and homogeneous resistance and film thickness. The TiSiN film forms Cu diffusion barrier with stable physical and chemical performance, and can prevent the diffusion of F ion in low dielectric coefficient material. TiSiN has also one characteristic that it has adhesion with both Cu metal film and porous low dielectric coefficient medium, and this is favorable to raising the electric migration resistance to Cu interconnection metal, and is suitable for multilayer Al wiring process and Cu metal Damascus interconnection process.

Description

Adopt the technology of the siliceous titanium nitride of chemical vapour deposition of titaniferous organo metallic material

Technical field

The invention belongs to the semiconductor integrated circuit manufacturing process technology field, be specifically related to a kind of employing titaniferous organo metallic material TDMA and add 3 methyl-monosilanes (3MS) or add a small amount of silane (SiCH4), chemical vapour deposition contains the technology of titanium silicon nitride TiSiN diffusion impervious layer.

Background technology

Along with constantly dwindling of integrated circuit (IC) design rule, the characteristic dimension live width has narrowed down to 0.10 micron, and keeps the continuous trend that reduces downwards.On the other hand, device density constantly increases in the unicircuit, and the metal line number of plies is more and more, and the wiring number of plies of logical circuit has reached the 7-8 layer.Because the resistance of metal interconnection line itself and the increase of stray capacitance thereof, the interconnected delay of consequent RC has surmounted the grid delay of transistor itself greatly, becomes the restraining factors of unicircuit speed.

Present stage unicircuit interconnected mainly be to adopt the Al metal line, metal line itself exists series resistance and stray capacitance in the process of transmission of electric signals.Along with the raising of integrated level, interconnection line length further extends, thereby causes the rapid rising of interconnection line resistance.On the other hand, the width of metal line constantly dwindles, and makes that the electric capacity between the interconnection line increases day by day, causes the further increasing of the interconnected delay of RC.Therefore, reduce the RC interconnect delay and become the focus that people pay close attention to.

On the one hand, people attempt adopting dielectric materials to replace traditional insulating material, to reduce between interconnecting metal and line capacitance.On the other hand, actively seek the metal of deelectric transferred ability, replace having used the Al metal of decades with littler resistivity and Geng Gao.Since the Cu metal have the resistivity littler than Al (resistivity of Cu is 1.68 micro-ohms. centimetre, and the resistivity of Al metal is 2.6 micro-ohms. centimetre), (fusing point of Cu metal is 1083C to higher fusing point, Al then is 660C), lower thermal expansivity (thermal expansivity of Cu is 16.5ppm/C, and the coefficient of expansion of Al is 23.6ppm/C).Thereby the conductivity of Cu and deelectric transferred performance all are superior to the Al metal greatly.Since IBM in 1998 takes the lead in introducing Cu Damascus processing technology in semiconductor production line, replace the Al multi-layer metal wiring with Cu, thereby reduce the performance impact of interconnection resistance greatly to unicircuit, reliability level is significantly improved, make Cu become the very potential novel interconnected metallic substance of following deep-submicron device.

For traditional Al technology, the Cu interconnection technique is a sharp brand-new technology, and great changes have taken place for processing units and material.Continuing to optimize of Cu Damascus technique, the continuous progress of particularly etching suspension layer (Etch-Stop), medium with low dielectric constant deposit, through hole and Wire connection slot photoetching and etching, Cu barrier layer deposition, Cu seed crystal and plating, Cu chemically machinery polished and back cleaning makes Cu technology can adapt to the processing request of super large-scale integration to minimum characteristic dimension and very big depth-width ratio figure.

But Cu is a heavy metal species, under the situation of high temperature and added electric field, can be in semi-conductor silicon chip and silica dioxide medium rapid diffusion, cause the problem of device reliability aspect.So, between Cu and dielectric, must add the barrier material that prevents the Cu diffusion, for example TaN, TiSiN, Ta etc.The purpose on blocking layer mainly contains two, and the firstth, the diffusion of resistance Cu metal in medium, the secondth, the adhesivity of raising Cu and medium.Ta is a kind of very attractive Cu blocking layer, mainly is that Ta has high melt point (2996C), do not melt mutually with Cu, and resistivity is low, and is good with the adhesion property of Cu.TaN then is a kind of Cu and the effective blocking layer of F ionic, just is used widely in the interconnected technology of Cu at present.

Usually, the requirement on Cu blocking layer is comprised following several respects: 1. barrier layer deposition will have good step coverage, particularly for depth-width ratio (A/R) greater than 6 double-deck damascene structure, it is the comparison difficulty that the step of sidewall and bottom covers; 2. the body resistance barrier material of barrier material itself must be very low, to reduce contact resistance and Cu wiring series resistance; 3. good with the insulating medium layer adhesivity, not easily separated and come off; Be the good barrier of Cu, in dielectric, spread, cause between the interconnection line and leak electricity to prevent Cu; 4. road complete processing pyritous tests after standing Cu, and Cu Damascus work flow temperature arrives 420C at 300C usually; 5. good with the dielectric materials compatibility, do not influence the chemical property of dielectric materials; 6. physical property satisfies follow-up CMP (Chemical Mechanical Polishing) process requirement.

Typical C u damascene metallization processes comprises: physical vapor deposition blocking layer, Cu inculating crystal layer, carry out the chemically machinery polished of chemical plating processing, rapid thermal annealing and the Cu of Cu then.

Physical vapor deposition (PVD) is generally adopted on the blocking layer, for 0.13 micron and following deep submicron process, the depth-width ratio of through hole and Wire connection slot often＞6, will be in such figure deposit thin and successive blocking layer, the PVD deposition technology has been proposed harsh more requirement. and because the influence of shade influence, the limitation of physical deposition is in the homogeneity of deposit, particularly the sidewall step coverage in hachure and dark through hole is very low, even adopt ion physical deposition (IPVD) method, under the situation of substrate biasing electric field, the fraction of coverage of sidewall and bottom is still very low.When causing follow-up Cu to electroplate, the cavity can occur, influence the yield rate and the reliability of unicircuit at through hole even at the sidewall of Wire connection slot.

On the other hand, 0.13 micron and following technology, inter-metal medium adopts low-k (Low-к) material more, the surface irregularity of porous low dielectric constant (Low-к) material, the chemical property instability, and physical deposition method and porous low dielectric constant (Low-к) material compatibility is bad, to technological phase below 0.10 micron, Cu is as conductor material, low-k (Low-к) must be considered to come the blocking layer of deposit with chemical vapour deposition (CVD) method of conformal superior performance as the dielectric of metal interlevel.

As the Cu barrier material, need to consider its diffusion barrier capability to Cu.In this respect, TiSiN and Cu and and porous low-k dielectric (Low-к) material good adhesivity is arranged.Preventing metal ion diffusion side, TiSiN is the good barrier material of Cu, and, be rich in N among the TiSiN, can prevent F ionic diffusion in the dielectric materials (Low-к).For the interconnected technology of following deep-submicron Cu multiple layer metal, the blocking layer is just developed towards 3 weight structure directions, has for example introduced the Si atom in the TiSiN lattice, and the Si key can be combined closely with the N key, obviously improve the performance of diffusion impervious layer, improved the anti-Cu diffusion and the anti-F diffusibility on blocking layer.Another characteristics of TiSiN are that the adhesivity of it and Cu metallic film and porous low dielectric constant (Low-к) medium is all fine, help improving the deelectric transferred level of the interconnected metal of Cu.

Summary of the invention

The objective of the invention is to propose a kind of method of the CVD of employing depositing TiSiN, make TiSiN have good step to cover homogeneous resistance and film uniformity.The adhesion property of TiSiN and W metal and dielectric is good.

The processing method of the employing CVD depositing TiSiN that the present invention proposes, the steps include: the first step,, utilize the chemical substance TDMA that contains Ti with chemical vapour deposition (CVD) method, with material 3 methyl-monosilanes (3MS) that contain Si or silane (SiCH4), deposit one deck TiSiN film; In second step, carry out H in position ₂-N ₂Radio frequency plasma is handled.

Adopt He in the first step ₂Gas carries chemical substance TDMA and methyl-monosilane (3MS) or silane (SiCH4), under the rough vacuum condition, by thermal decomposition deposition TiSiN film.Deposition temperature is 400 ℃-450 ℃, and vacuum tightness is 1Torr-5Torr, and each deposition time is 10-15 second.

Carry out H in position in second step ₂-N ₂Radio frequency plasma is handled, and employing low pressure is 1Torr-2Torr, and each treatment time is 30-40 second.

The circulation the first step and described processing step of second step are 30-50nm up to the TiSiN deposition thickness scope that reaches setting.

The ratio of material 3 methyl-monosilanes (3MS) of the above-mentioned Si of containing is 2%-8%; The ratio of the material silane (SiCH4) of the above-mentioned Si of containing is 1%-3%.

The purpose of the first step depositing technics is the TiSiN film of preparing uniformly, having higher step coverage, and the second step H ₂-N ₂The radio frequency plasma processing then is the content for impurity such as carbon, oxygen and hydrogen in the TiSiN film that reduces the CVD deposit, reduces resistivity, makes the growth of TiSiN uniform crystal particles, and makes the density of TiSiN film.

The method of the depositing TiSiN that the present invention proposes, the TiSiN of deposit has good step and covers homogeneous resistance cloth and film uniformity.TiSiN is the stable Cu diffusion impervious layer of a kind of physicals and chemical property, and, be rich in N among the TiSiN, can prevent F ionic diffusion in the dielectric materials (Low-к).Another characteristics of TiSiN are that the adhesivity of it and Cu metallic film and porous low dielectric constant (Low-к) medium is all fine, help improving the deelectric transferred level of the interconnected metal of Cu.

The TiSiN of deposit has good step and covers homogeneous resistance and film uniformity in this way.The adhesion property of TiSiN and W metal and dielectric is good, can be used in the interconnected post technology of W, prevents WF effectively ₆Erosion to silicon chip and medium layer.TiSiN is also good with the adhesion property of Al metal and dielectric, is applied to can significantly improve the electric migration performance of Al plain conductor in the Al metallic multilayer Wiring technique.TiSiN still is the blocking layer of Cu, can be used for the Cu metallization process, realizes Cu metal damascene interconnection technique.

Description of drawings

Fig. 1 represents to adopt the application synoptic diagram of CVD deposit TaSiN blocking layer in the interconnected technology of Cu.

Label declaration: wherein 1 is the TaSiN blocking layer; The 2nd, the Cu metal interconnection layer; The 3rd, insulating medium layer.

Embodiment

1. adopt multi-cavity chamber CVD deposition apparatus, for example the Endura TxZ ﹠amp of company of Applied Materials; HP TxZ equipment utilizes TDMAT to add methyl-monosilane (3MS) or SiCH4, chemical vapour deposition TiSiN film.

2. at first, be set under the 5Torr condition, silicon chip is warmed up to 450C in vacuum.

3. then, use He ₂Carry the methyl-monosilane (3MS) of chemical substance TDMA and 5%, by thermal decomposition deposition TiSiN film.At deposition temperature is 450C, and low vacuum 1.5Torr, TDMAT flow are 225sccm, and the 3MS flow is 11sccm, and the SiCH4 flow is 4.5sccm, He ₂Flow is 275sccm, N ₂Flow be 300sccm, the deposition time that at every turn circulates 15 seconds.

4. original position H ₂-N ₂Radio frequency plasma is handled, and reduces carbon in the TiSiN film of CVD deposit, and the content of impurity such as oxygen and hydrogen reduces resistivity, makes the growth of TiSiN uniform crystal particles, and makes the density of TiSiN film, improves film uniformity.Processing vacuum tightness is 1.5Torr, and the time is 35 seconds.The silicon temperature 20C that can rise during this time;

5. silicon chip is cooled to TiSiN deposit design temperature, and vacuum conditions is to 1.5Torr;

6. repeat the 3rd step process, utilize He ₂Carry TDMAT, by thermal decomposition deposition TiSiN, deposition time is 15 seconds.

7. repeated for 4 steps, in-situ hydrogen-nitrogen radio frequency plasma is handled, 35 seconds time;

8. the depositing TiSiN thickness that at every turn circulates is 1.1nm-1.5nm circulation TiSiN deposit and original position H ₂-N ₂Radio frequency plasma is handled, up to the TiSiN deposition thickness that reaches setting.

Claims

1, a kind of manufacturing process based on the CVD depositing TiSiN film is characterized in that: the first step, use chemical vapor deposition method, and utilize material 3 methyl-monosilanes or the silane that contain the chemical substance TDMA of Ti and contain Si, deposit one deck TiSiN film; In second step, carry out H in position ₂-N ₂Radio frequency plasma is handled.

2, technology according to claim 1 is characterized in that, the ratio of material 3 methyl-monosilanes of the above-mentioned Si of containing is 2%-8%; The ratio of the material silane of the above-mentioned Si of containing is 1%-3%.

3, technology according to claim 1 is characterized in that, adopts He ₂Gas carries chemical substance TDMA and methyl-monosilane or silane, and under 1Torr-5Torr rough vacuum condition, by thermal decomposition deposition TiSiN film, deposition temperature is 400 ℃-450 ℃, and each deposition time is 10-15 second.

4, technology according to claim 1 is characterized in that, carries out H in position ₂-N ₂Radio frequency plasma is handled, and low pressure is 1Torr-2Torr, and each treatment time is 30-40 second.

5, technology according to claim 1 is characterized in that, first and second processing steps that circulate are 30-50nm up to the TiSiN deposition thickness scope that reaches setting.