KR100924556B1 - Metal wiring of semiconductor device and method of manufacturing the same - Google Patents

Metal wiring of semiconductor device and method of manufacturing the same Download PDF

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KR100924556B1
KR100924556B1 KR1020080001376A KR20080001376A KR100924556B1 KR 100924556 B1 KR100924556 B1 KR 100924556B1 KR 1020080001376 A KR1020080001376 A KR 1020080001376A KR 20080001376 A KR20080001376 A KR 20080001376A KR 100924556 B1 KR100924556 B1 KR 100924556B1
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film
forming
semiconductor device
metal
diffusion barrier
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KR20090075499A (en
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정동하
염승진
김백만
김정태
이남열
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 확산방지막의 특성을 개선하여 소자 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 금속배선 및 그 형성방법을 개시한다. 개시된 본 발명에 따른 반도체 소자의 금속배선은, 반도체 기판 상에 형성되며, 배선 형성 영역을 갖는 절연막; 상기 절연막의 배선 형성 영역 표면 상에 형성되며, TaxCry막, TaxCryNz막 및 TaxNy막의 다층 구조를 포함하는 확산방지막; 및 상기 확산방지막 상에 상기 절연막의 배선 형성 영역을 매립하도록 형성된 금속막;을 포함한다.The present invention discloses a metal wiring and a method of forming the semiconductor device that can improve the characteristics and reliability of the device by improving the characteristics of the diffusion barrier. A metal wiring of a semiconductor device according to the present invention, comprising: an insulating film formed on a semiconductor substrate and having a wiring formation region; A diffusion barrier film formed on a surface of a wiring formation region of the insulating film and including a multilayer structure of a Ta x Cr y film, a Ta x Cr y N z film, and a Ta x N y film; And a metal film formed on the diffusion barrier to fill the wiring forming region of the insulating film.

Description

반도체 소자의 금속배선 및 그 형성방법{METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}Metal Wiring of Semiconductor Devices and Formation Method {METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

본 발명은 반도체 소자의 금속배선 및 그 형성방법에 관한 것으로, 보다 상세하게는, 확산방지막의 특성을 개선하여 소자 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 금속배선 및 그 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal wiring of semiconductor devices and methods of forming the same, and more particularly, to metal wiring of semiconductor devices and a method of forming the same, which can improve device characteristics and reliability by improving the characteristics of the diffusion barrier film.

일반적으로, 반도체 소자에는 소자와 소자 간, 또는, 배선과 배선 간을 전기적으로 연결하기 위해 금속배선이 형성되며, 상부 금속배선과 하부 금속배선 간의 연결을 위해 콘택 플러그가 형성된다.In general, a metal element is formed in the semiconductor element to electrically connect the element and the element, or the interconnection and the interconnection, and a contact plug is formed to connect the upper metal interconnection and the lower metal interconnection.

상기 금속배선의 재료로는 전기 전도도가 우수한 알루미늄(Al) 및 텅스텐(W)이 주로 이용되어 왔으며, 최근에는 상기 알루미늄 및 텅스텐보다 전기 전도도가 월등히 우수하고 저항이 낮아 고집적 고속동작 소자에서 RC 신호 지연 문제를 해결할 수 있는 구리(Cu)를 차세대 금속배선 물질로 사용하고자 하는 연구가 진행되고 있다. Aluminum (Al) and tungsten (W), which have excellent electrical conductivity, have been mainly used as the material for the metallization, and in recent years, the RC signal delay in high-integrated high-speed operation devices has much higher electrical conductivity and lower resistance than the aluminum and tungsten. Research into using copper (Cu) as a next-generation metallization material that can solve the problem is being conducted.

그런데, 상기 구리의 경우 배선 형태로 건식 식각하기가 용이하지 않기 때문에, 구리로 금속배선을 형성하기 위해서는 다마신(Damascene)이라는 새로운 공정 기술이 이용된다. 다마신 금속배선 공정은 층간절연막을 식각해서 다마신 패턴을 형성하고, 상기 다마신 패턴을 구리막으로 매립하여 금속배선을 형성하는 기술이며, 싱글-다마신(Single-Damascene) 공정과 듀얼-다마신(Dual-Damascene) 공정으로 나눌 수 있다.However, in the case of copper, since it is not easy to dry-etch in the form of wiring, a new process technology called damascene is used to form metal wiring with copper. The damascene metal interconnection process is a technique of forming a damascene pattern by etching an interlayer insulating film, and forming the metal interconnection by embedding the damascene pattern with a copper film. It can be divided into dual-Damascene process.

상기 다마신 공정의 적용하는 경우에는 다층 금속배선에서 상층 금속배선, 그리고, 상기 상층 금속배선과 하층 금속배선을 콘택시키기 위한 콘택 플러그를 동시에 형성할 수 있을 뿐 아니라, 금속배선에 의해 발생하는 단차를 제거할 수 있으므로 후속 공정을 용이하게 하는 장점이 있다.In the case of applying the damascene process, not only the upper metal wiring and the contact plug for contacting the upper metal wiring and the lower metal wiring in the multi-layer metal wiring can be formed at the same time, but also the steps generated by the metal wiring can be eliminated. As it can be removed, there is an advantage of facilitating subsequent processes.

또한, 상기 금속배선 물질로 구리막을 적용하는 경우에는 알루미늄막을 적용하는 경우와 달리 층간절연막을 통해 기판으로의 구리막 성분이 확산된다. 상기 확산된 구리막 성분은 실리콘으로 이루어진 반도체 기판 내에서 딥 레벨(Deep Level) 불순물로서 작용하여 누설 전류를 유발하므로, 상기 구리막과 층간절연막의 접촉 계면에 확산방지막(Diffusion Barrier)을 형성해주어야 한다. 상기 확산방지막은 통상 PVD(Physical Vapor Deposition) 방식을 통해 Ta막과 TaN막의 단일막, 또는, 이중막 구조로 형성한다.In addition, when the copper film is applied as the metal wiring material, unlike the aluminum film, the copper film component is diffused to the substrate through the interlayer insulating film. Since the diffused copper film component acts as a deep level impurity in a semiconductor substrate made of silicon to cause leakage current, a diffusion barrier must be formed at the contact interface between the copper film and the interlayer insulating film. . The diffusion barrier layer is typically formed of a single layer or a double layer structure of a Ta layer and a TaN layer through PVD (Physical Vapor Deposition).

그러나, 전술한 종래 기술의 경우에는 상기 확산방지막이 결정질상으로 형성되며, 이 때문에, 상기 결정질상의 확산방지막의 결정 입계(Grain Boundary)를 통해 구리막의 성분이 절연막으로 확산된다. 또한, 반도체 소자의 미세화에 따라 상기 확산방지막의 두께 감소가 요구되고 있는 실정이며, 이로 인해, 상기 확산방지막의 특성이 저하되어, 그 결과, 소자 특성 및 신뢰성이 열화된다.However, in the above-described prior art, the diffusion barrier is formed in a crystalline phase, and therefore, a component of the copper film is diffused into the insulating layer through the grain boundary of the diffusion barrier in the crystalline phase. In addition, as the semiconductor device becomes smaller, the thickness of the diffusion barrier is required to be reduced. As a result, the characteristics of the diffusion barrier are reduced, resulting in deterioration of device characteristics and reliability.

본 발명은 확산방지막의 특성을 개선할 수 있는 반도체 소자의 금속배선 및 그 형성방법을 제공한다.The present invention provides a metal wiring of a semiconductor device and a method of forming the same that can improve the characteristics of the diffusion barrier film.

또한, 본 발명은 소자 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 금속배선 및 그 형성방법을 제공한다.In addition, the present invention provides a metal wiring and a method of forming the semiconductor device that can improve device characteristics and reliability.

본 발명의 실시예에 따른 반도체 소자의 금속배선은, 반도체 기판 상에 형성되며, 배선 형성 영역을 갖는 절연막; 상기 절연막의 배선 형성 영역 표면 상에 형성되며, TaxCry막, TaxCryNz막 및 TaxNy막의 다층 구조를 포함하는 확산방지막; 및 상기 확산방지막 상에 상기 절연막의 배선 형성 영역을 매립하도록 형성된 금속막;을 포함한다.A metal wiring of a semiconductor device according to an embodiment of the present invention, an insulating film formed on a semiconductor substrate, the wiring forming region; A diffusion barrier film formed on a surface of a wiring formation region of the insulating film and including a multilayer structure of a Ta x Cr y film, a Ta x Cr y N z film, and a Ta x N y film; And a metal film formed on the diffusion barrier to fill the wiring forming region of the insulating film.

상기 TaxCry막과 TaxCryNz막은 각각 비정질상을 갖는다.The Ta x Cr y film and the Ta x Cr y N z film each have an amorphous phase.

상기 TaxNy막은 결정질상을 갖는다.The Ta x N y film has a crystalline phase.

상기 TaxCry막의 x가 0.3∼0.8의 범위를 갖고, y는 0.2∼0.7의 범위를 갖는다.The x of the Ta x Cr y film has a range of 0.3 to 0.8, and y has a range of 0.2 to 0.7.

상기 TaxCryNz막의 x는 0.2∼0.8의 범위를 갖고, y는 0.1∼0.5의 범위를 가지며, z는 0.1∼0.3의 범위를 갖는다.The x of the Ta x Cr y N z film has a range of 0.2 to 0.8, y has a range of 0.1 to 0.5, and z has a range of 0.1 to 0.3.

상기 TaxNy막의 x는 0.3∼0.5의 범위를 갖고, y는 0.5∼0.7의 범위를 갖는다.The x of the Ta x N y film has a range of 0.3 to 0.5, and y has a range of 0.5 to 0.7.

상기 확산방지막과 금속막 사이에 개재된 씨드막을 더 포함한다.Further comprising a seed film interposed between the diffusion barrier film and the metal film.

상기 씨드막은 구리(Cu)막, 또는, 루테늄(Ru)막을 포함한다.The seed film includes a copper (Cu) film or a ruthenium (Ru) film.

상기 금속막은 구리막을 포함한다.The metal film includes a copper film.

본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법은, 반도체 기판 상에 배선 형성 영역을 갖는 절연막을 형성하는 단계; 상기 배선 형성 영역의 표면을 포함한 절연막 상에 TaxCry막, TaxCryNz막 및 TaxNy막의 다층 구조를 포함하는 확산방지막을 형성하는 단계; 및 상기 확산방지막 상에 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계;를 포함한다.In accordance with another aspect of the present disclosure, a method of forming metal wirings of a semiconductor device may include forming an insulating film having a wiring formation region on a semiconductor substrate; Forming a diffusion barrier film including a multilayer structure of a Ta x Cr y film, a Ta x Cr y N z film, and a Ta x N y film on the insulating film including the surface of the wiring forming region; And forming a metal film to fill the wiring forming region on the diffusion barrier film.

상기 TaxCry막과 TaxCryNz막은 각각 비정질상을 갖는 막으로 형성한다.The Ta x Cr y film and the Ta x Cr y N z film are each formed of a film having an amorphous phase.

상기 TaxNy막은 결정질상을 갖는 막으로 형성한다.The Ta x N y film is formed of a film having a crystalline phase.

상기 TaxCry막은 x가 0.3∼0.8의 범위를 갖고, y가 0.2∼0.7의 범위를 갖는 막으로 형성한다.The Ta x Cr y film is formed of a film in which x has a range of 0.3 to 0.8 and y has a range of 0.2 to 0.7.

상기 TaxCryNz막은 x가 0.2∼0.8의 범위를 갖고, y가 0.1∼0.5의 범위를 가지며, z가 0.1∼0.3의 범위를 갖는 막으로 형성한다.The Ta x Cr y N z film is formed of a film in which x has a range of 0.2 to 0.8, y has a range of 0.1 to 0.5, and z has a range of 0.1 to 0.3.

상기 TaxNy막은 x가 0.3∼0.5의 범위를 갖고, y가 0.5∼0.7의 범위를 갖는 막으로 형성한다.The Ta x N y film is formed of a film in which x has a range of 0.3 to 0.5 and y has a range of 0.5 to 0.7.

상기 확산방지막을 형성하는 단계는, 상기 배선 형성 영역의 표면을 포함한 절연막 상에 TaxCry막을 형성하는 단계; 상기 TaxCry막 상에 TaxNy막을 형성하는 단계; 및 상기 TaxCry막과 상기 TaxNy막을 반응시켜 그 계면에 TaxCryNz막을 형성하는 단계;를 포함한다.The forming of the diffusion barrier layer may include forming a Ta x Cr y film on an insulating film including a surface of the wiring forming region; Forming a Ta x N y film on the Ta x Cr y film; And reacting the Ta x Cr y film with the Ta x N y film to form a Ta x Cr y N z film at an interface thereof.

상기 TaxCry막은 PVD(Physical Vapor Deposition) 방식, 또는 CVD(Chemical Vapor Deposition) 방식으로 형성한다.The Ta x Cr y film is formed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method.

상기 TaxNy막은 PVD 방식, 스퍼터링(Sputtering) 방식 및 ALD(Atomic Layer Deposition) 방식 중 어느 하나의 방식으로 형성한다.The Ta x N y film is formed by any one of a PVD method, a sputtering method, and an atomic layer deposition (ALD) method.

상기 PVD 및 스퍼터링 방식은 N2 및 Ar을 사용하여 수행한다.The PVD and sputtering scheme is performed using N 2 and Ar.

상기 PVD 및 스퍼터링 방식은 1∼99mTorr의 압력 조건으로 수행한다.The PVD and sputtering methods are performed under pressure conditions of 1 to 99 mTorr.

상기 TaxCry막과 상기 TaxNy막의 반응은 열 처리 방식으로 수행한다.The reaction of the Ta x Cr y film and the Ta x N y film is performed by a heat treatment method.

상기 열 처리는 Ar 분위기, 또는, H2+N2 분위기에서 수행한다.The heat treatment is performed in an Ar atmosphere or H 2 + N 2 atmosphere.

상기 열처리는 300∼600℃의 온도 조건으로 수행한다.The heat treatment is carried out under a temperature condition of 300 to 600 ℃.

상기 확산방지막을 형성하는 단계 후, 그리고, 상기 금속막을 형성하는 단계 전, 상기 확산방지막 상에 씨드막을 형성하는 단계;를 더 포함한다.And forming a seed film on the diffusion barrier layer after forming the diffusion barrier layer and before forming the metal layer.

상기 씨드막은 구리막, 또는, 루테늄막을 포함한다.The seed film includes a copper film or a ruthenium film.

상기 구리막은 PVD 방식으로 형성한다.The copper film is formed by PVD method.

상기 루테늄막은 ALD 방식으로 형성한다.The ruthenium film is formed by the ALD method.

상기 금속막은 구리막을 포함한다.The metal film includes a copper film.

본 발명은 구리막을 이용하는 금속배선의 형성시 비정질의 TaCr막과 비정질의 TaCrN막 및 결정질의 TaN막의 다층 구조를 포함하는 확산방지막을 형성함으로써, 상기 확산방지막의 특성을 개선할 수 있다. 이에 따라, 본 발명은 상기 확산방지막의 특성을 개선하여 구리막의 성분이 확산되는 것을 방지할 수 있으며, 이를 통해, 반도체 소자의 특성 및 신뢰성을 향상시킬 수 있다.The present invention can improve the characteristics of the diffusion barrier layer by forming a diffusion barrier layer comprising a multilayer structure of an amorphous TaCr layer, an amorphous TaCrN layer and a crystalline TaN layer when forming a metal wiring using a copper layer. Accordingly, the present invention can prevent the diffusion of components of the copper film by improving the properties of the diffusion barrier, thereby improving the characteristics and reliability of the semiconductor device.

또한, 본 발명은 상기 비정질의 TaCr막과 비정질의 TaCrN막 및 결정질의 TaN막의 다층 구조를 포함하는 확산방지막 중 상기 TaCr막은 절연막과의 접착력이 우수하고, 또한, 상기 TaN막은 구리막과의 접착력이 우수하므로 금속배선의 형성 공정을 안정적이고 용이하게 수행할 수 있다.In the present invention, the TaCr film is excellent in adhesion to the insulating film and the TaN film is excellent in adhesion to the copper film among the diffusion barrier films including the multilayer structure of the amorphous TaCr film, the amorphous TaCrN film and the crystalline TaN film. Since it is excellent, the formation process of metal wiring can be performed stably and easily.

본 발명은 구리막과 절연막 사이에 비정질의 TaCr막과 비정질의 TaCrN막 및 결정질의 TaN막이 순차적으로 적층된 다층 구조를 포함하는 확산방지막을 형성한다. 이렇게 하면, 상기 구리막의 성분이 확산되는 주 경로인 결정립계가 없는 확산방지막이 형성되므로, 상기 확산방지막 자체의 특성이 개선된다. 따라서, 본 발명은 소자 특성 및 신뢰성을 향상시킬 수 있다.The present invention forms a diffusion barrier film including a multilayer structure in which an amorphous TaCr film, an amorphous TaCrN film, and a crystalline TaN film are sequentially stacked between a copper film and an insulating film. In this way, a diffusion barrier film without a grain boundary, which is a main path through which the components of the copper film are diffused, is formed, thereby improving the characteristics of the diffusion barrier film itself. Therefore, the present invention can improve device characteristics and reliability.

이하에서는 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1은 본 발명의 실시예에 따른 반도체 소자의 금속배선을 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a metal wiring of a semiconductor device according to an embodiment of the present invention.

도시된 바와 같이, 소정의 하부 구조물(도시안됨)이 구비된 반도체 기판(100) 상에 배선 형성 영역(D)을 갖는 절연막(102)이 형성되어 있다. 상기 배선 형성 영역(D)은 싱글 다마신 공정 또는 듀얼 다마신 공정에 따라 트렌치 구조, 또는, 트렌치 및 상기 트렌치와 연결되는 적어도 하나 이상의 비아홀을 포함하는 트렌치 및 비아홀 구조로 형성될 수 있다.As illustrated, an insulating layer 102 having a wiring forming region D is formed on the semiconductor substrate 100 provided with a predetermined lower structure (not shown). The wiring forming region D may be formed in a trench structure or a trench and via hole structure including a trench and at least one via hole connected to the trench according to a single damascene process or a dual damascene process.

상기 절연막(102)의 배선 형성 영역(D) 표면 상에 TaCr막(104)과 TaCrN막(108) 및 TaN막(106)이 순차적으로 적층된 다층 구조를 포함하는 확산방지막(110)이 형성되어 있다. 상기 확산방지막(110)의 TaCr막(104)과 TaCrN막(108)은 각각 비정질상을 갖도록 형성되어 있고, 상기 TaN막(106)은 결정질상을 갖도록 형성되어 있다. 또한, 상기 TaCr막(104)은, 바람직하게, TaxCry막(0.3≤x≤0.8, 0.2≤y≤0.7)이고, 상기 TaCrN막(108)은, 바람직하게, TaxCryNz막(0.2≤x≤0.8, 0.1≤y≤0.5, 0.1≤z≤0.3)이며, 상기 TaN막(106)은, 바람직하게, TaxNy막(0.3≤x≤0.5, 0.5≤y≤0.7)이다.On the surface of the wiring forming region D of the insulating layer 102, a diffusion barrier 110 including a multi-layered structure in which the TaCr film 104, the TaCrN film 108, and the TaN film 106 are sequentially stacked is formed. have. The TaCr film 104 and the TaCrN film 108 of the diffusion barrier film 110 are formed to have an amorphous phase, respectively, and the TaN film 106 is formed to have a crystalline phase. The TaCr film 104 is preferably a Ta x Cr y film (0.3 ≦ x ≦ 0.8, 0.2 ≦ y ≦ 0.7), and the TaCrN film 108 is preferably Ta x Cr y N z. film (0.2≤x≤0.8, 0.1≤y≤0.5, 0.1≤z≤0.3), and the TaN film 106 is, preferably, Ta x N y film (0.3≤x≤0.5, 0.5≤y≤0.7 )to be.

상기 확산방지막(110)의 TaN막(106) 상에 씨드막(112)이 형성되어 있으며, 상기 씨드막(112) 상에 상기 절연막(102)의 배선 형성 영역(D)을 매립하도록 금속배선(114)이 형성되어 있다. 상기 씨드막(112)은 구리(Cu)막, 또는, 루테늄(Ru)막을 포함하며, 상기 금속배선(114)은 구리막을 포함한다. 상기 금속배선(114)을 포함한 절연막(102) 상에 캡핑막(116)이 형성되어 있다.The seed film 112 is formed on the TaN film 106 of the diffusion barrier film 110, and the metal wires are embedded to fill the wiring forming region D of the insulating film 102 on the seed film 112. 114) is formed. The seed film 112 may include a copper (Cu) film or a ruthenium (Ru) film, and the metal wire 114 may include a copper film. A capping layer 116 is formed on the insulating layer 102 including the metal line 114.

본 발명의 금속배선(114)은 구리막과 절연막(102) 사이에 결정 입계가 존재하지 않는 비정질상의 TaCr막(104)과 비정질상의 TaCrN막(108) 및 결정질상의 TaN막(106)이 순차적으로 적층된 다층 구조를 포함하는 확산방지막(110)이 형성되므로, 상기 구리막의 성분이 절연막(102)으로 확산되는 것을 방지할 수 있다. 따라서, 본 발명은 상기 확산방지막(110) 자체의 특성을 개선할 수 있으며, 이에 따라, 본 발명은 반도체 소자 특성 및 신뢰성을 향상시킬 수 있다.In the metal wiring 114 of the present invention, an amorphous TaCr film 104 having no grain boundary between the copper film and the insulating film 102, an amorphous TaCrN film 108, and a crystalline TaN film 106 are sequentially formed. Since the diffusion barrier 110 including the stacked multilayer structure is formed, it is possible to prevent the components of the copper film from diffusing into the insulating layer 102. Therefore, the present invention can improve the characteristics of the diffusion barrier 110 itself, and accordingly, the present invention can improve semiconductor device characteristics and reliability.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도이다. 2A through 2G are cross-sectional views illustrating processes of forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 소정의 하부 구조물(도시안됨)이 형성된 반도체 기판(100) 상에 상기 하부 구조물을 덮도록 절연막(102)을 형성한다. 상기 절연막을 식각하여 배선 형성 영역(D)을 형성한다. 상기 배선 형성 영역(D)은 싱글 다마신 공정 또는 듀얼 다마신 공정에 따라 트렌치 구조, 또는, 트렌치 및 상기 트렌치와 연결되는 적어도 하나 이상의 비아홀을 포함하는 트렌치 및 비아홀 구조로 형성할 수 있다.Referring to FIG. 2A, an insulating film 102 is formed to cover the lower structure on the semiconductor substrate 100 on which a predetermined lower structure (not shown) is formed. The insulating layer is etched to form a wiring forming region D. The wiring forming region D may be formed in a trench structure or a trench and via hole structure including a trench and at least one via hole connected to the trench according to a single damascene process or a dual damascene process.

도 2b를 참조하면, 상기 배선 형성 영역(D)의 표면을 포함한 절연막(102) 상에 TaCr막(104)을 형성한다. 상기 TaCr막(104)은, 바람직하게, PVD(Physical Vapor Deposition), 또는, CVD(Chemical Vapor Deposition) 방식으로 형성한다. 또한, 상기 TaCr막(104)은, 예컨대, Ta의 함량이 30∼82%인 막, 바람직하게, TaxCry막(0.3≤x≤0.8, 0.2≤y≤0.7)으로 형성하며, 이 경우, 상기 TaCr막(104)은 비정질상을 갖는다. Referring to FIG. 2B, a TaCr film 104 is formed on the insulating film 102 including the surface of the wiring formation region D. Referring to FIG. The TaCr film 104 is preferably formed by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). Further, the TaCr film 104 is formed of, for example, a film having a Ta content of 30 to 82%, preferably a Ta x Cr y film (0.3 ≦ x ≦ 0.8, 0.2 ≦ y ≦ 0.7). The TaCr film 104 has an amorphous phase.

도 2c를 참조하면, 상기 TaCr막(104) 상에 결정질상을 갖는 TaN막(106)을 형성한다. 상기 TaN막(106)은, 바람직하게, TaxNy막(0.3≤x≤0.5, 0.5≤y≤0.7)으로 형성한다. 또한, 상기 TaN막(106)은, 바람직하게, PVD(Physical Vapor Deposition), 스퍼터링(Sputtering) 및 ALD(Atomic Layer Deposition) 중 어느 하나의 방식으로 형성하며, 결정질상을 갖도록 형성한다. 이때, 상기 PVD 및 스퍼터링 방식은 N2 및 Ar을 사용하는 반응성 스퍼터링 방식으로 1∼99mTorr의 압력 조건으로 수행한다.Referring to FIG. 2C, a TaN film 106 having a crystalline phase is formed on the TaCr film 104. The TaN film 106 is preferably formed of a Ta x N y film (0.3 ≦ x ≦ 0.5, 0.5 ≦ y ≦ 0.7). In addition, the TaN film 106 is preferably formed by any one of physical vapor deposition (PVD), sputtering, and atomic layer deposition (ALD), and has a crystalline phase. At this time, the PVD and the sputtering method is a reactive sputtering method using N 2 and Ar is carried out under a pressure condition of 1 ~ 99mTorr.

도 2d를 참조하면, 상기 TaCr막(104)과 상기 TaN막(106)이 그 계면 부분에서 반응하도록 반도체 기판(100)을 열처리하여, 그 계면에 비정질상을 갖는 TaCrN막(108)을 형성한다. 상기 TaCrN막(108)은, 바람직하게, TaxCryNz막(0.2≤x≤0.8, 0.1≤y≤0.5, 0.1≤z≤0.3)으로 형성한다. 이때, 상기 열 처리는 Ar 분위기, 또는, H2+N2 분위기에서 300∼600℃의 온도 조건으로 수행한다.Referring to FIG. 2D, the semiconductor substrate 100 is heat-treated such that the TaCr film 104 and the TaN film 106 react at an interface portion thereof, thereby forming a TaCrN film 108 having an amorphous phase at the interface. The TaCrN film 108 is preferably formed of a Ta x Cr y N z film (0.2 ≦ x ≦ 0.8, 0.1 ≦ y ≦ 0.5, 0.1 ≦ z ≦ 0.3). At this time, the heat treatment is carried out under an Ar atmosphere, or a temperature condition of 300 ~ 600 ℃ in H 2 + N 2 atmosphere.

그 결과, 상기 배선 형성 영역(D)의 표면을 포함한 절연막(102) 상에 비정질상의 TaCr막(104)과 비정질상의 TaCrN막(108) 및 결정질상의 TaN막(106)이 순차적으로 적층된 다층 구조를 포함하는 확산방지막(110)을 형성한다. As a result, a multi-layer structure in which an amorphous TaCr film 104, an amorphous TaCrN film 108, and a crystalline TaN film 106 are sequentially stacked on the insulating film 102 including the surface of the wiring formation region D. To form a diffusion barrier 110 comprising a.

도 2e를 참조하면, 상기 확산방지막(110) 상에 씨드막(112)을 형성한다. 상기 씨드막(112)은 PVD 방식을 통해 구리막으로 형성하거나, 또는, ALD 방식을 통해 루테늄막으로 형성한다.Referring to FIG. 2E, the seed film 112 is formed on the diffusion barrier film 110. The seed film 112 is formed of a copper film through a PVD method, or a ruthenium film through an ALD method.

도 2f를 참조하면, 상기 씨드막(112) 상에 상기 배선 형성 영역(D)을 매립하 도록 금속막(114a)을 형성한다. 상기 금속막(114a)은, 바람직하게, 구리막으로 형성하며, 상기 구리막은, 예컨대, 전기도금(Electroplating) 방식으로 형성한다.Referring to FIG. 2F, a metal film 114a is formed on the seed film 112 to fill the wiring formation region D. Referring to FIG. The metal film 114a is preferably formed of a copper film, and the copper film is formed by, for example, an electroplating method.

도 2g를 참조하면, 상기 금속막, 씨드막(112) 및 확산방지막(110)을 상기 절연막(102)이 노출되도록 CMP(Chemical Mechanical Polishing)하여 상기 배선 형성 영역(D)을 매립하는 금속배선(114)을 형성한다. 상기 금속배선(114)이 형성된 절연막(102) 상에 캡핑막(116)을 형성한다.Referring to FIG. 2G, a metal wiring for filling the wiring forming region D by CMP (Chemical Mechanical Polishing) of the metal film, the seed film 112, and the diffusion barrier film 110 to expose the insulating film 102 ( 114). The capping layer 116 is formed on the insulating layer 102 on which the metal wiring 114 is formed.

이와 같이, 본 발명은 금속배선의 확산방지막으로서 비정질의 TaCr막과 비정질의 TaCrN막 및 결정질의 TaN막이 순차적으로 적층된 다층 구조를 형성함으로써, 상기 확산방지막의 두께를 종래 보다 증가시키지 않고도 상기 확산방지막의 특성을 개선할 수 있으며, 이를 통해, 구리막의 성분이 절연막으로 확산되는 것을 방지할 수 있다. 따라서, 본 발명은 소자 특성 및 신뢰성을 향상시킬 수 있다.As described above, the present invention forms a multi-layered structure in which an amorphous TaCr film, an amorphous TaCrN film, and a crystalline TaN film are sequentially stacked as a diffusion barrier of a metal wiring, thereby increasing the thickness of the diffusion barrier without further increasing the thickness of the diffusion barrier. It is possible to improve the characteristics of, through which, it is possible to prevent the components of the copper film to diffuse into the insulating film. Therefore, the present invention can improve device characteristics and reliability.

또한, 본 발명은 상기 확산방지막의 상기 TaCr막이 상기 절연막과의 접착력이 우수하며, 상기 확산방지막의 TaN막이 구리막과의 접착력이 우수하므로, 금속배선의 형성 공정을 안정화시킬 수 있다.In addition, the TaCr film of the diffusion barrier film is excellent in adhesion to the insulating film, the TaN film of the diffusion barrier film is excellent in adhesion to the copper film, it is possible to stabilize the formation process of the metal wiring.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1은 본 발명의 실시예에 따른 반도체 소자의 금속배선을 설명하기 위해 도시한 단면도.1 is a cross-sectional view for explaining a metal wiring of a semiconductor device according to an embodiment of the present invention.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정별 단면도.2A to 2G are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 반도체 기판 102 : 절연막100 semiconductor substrate 102 insulating film

D : 배선 형성 영역 104 : TaCr막D: wiring formation region 104: TaCr film

106 : TaN막 108 : TaCrN막106 TaN film 108 TaCrN film

110 : 확산방지막 112 : 씨드막110: diffusion barrier 112: seed film

114 : 금속배선 116 : 캡핑망114: metal wiring 116: capping network

Claims (28)

반도체 기판 상에 형성되며, 배선 형성 영역을 갖는 절연막;An insulating film formed on the semiconductor substrate and having wiring formation regions; 상기 절연막의 배선 형성 영역 표면 상에 형성되며, TaxCry막(0.3≤x≤0.8, 0.2≤y≤0.7), TaxCryNz막(0.2≤x≤0.8, 0.1≤y≤0.5, 0.1≤z≤0.3) 및 TaxNy막(0.3≤x≤0.5, 0.5≤y≤0.7)이 순차적으로 적층된 다층 구조를 포함하는 확산방지막; 및A Ta x Cr y film (0.3 ≦ x ≦ 0.8, 0.2 ≦ y ≦ 0.7) and a Ta x Cr y N z film (0.2 ≦ x ≦ 0.8, 0.1 ≦ y ≦ 0.5) are formed on the wiring formation region surface of the insulating film. A diffusion barrier including a multilayer structure in which 0.1 ≦ z ≦ 0.3 and Ta × N y films (0.3 ≦ x ≦ 0.5, 0.5 ≦ y ≦ 0.7) are sequentially stacked; And 상기 확산방지막 상에 상기 절연막의 배선 형성 영역을 매립하도록 형성된 금속막;A metal film formed on the diffusion barrier to fill a wiring formation region of the insulating film; 을 포함하는 것을 특징으로 하는 반도체 소자의 금속배선.Metal wiring of a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 TaxCry막과 TaxCryNz막은 각각 비정질상을 갖는 것을 특징으로 하는 반도체 소자의 금속배선.The Ta x Cr y film and the Ta x Cr y N z film each have an amorphous phase. 제 1 항에 있어서, The method of claim 1, 상기 TaxNy막은 결정질상을 갖는 것을 특징으로 하는 반도체 소자의 금속배선.The Ta x N y film has a crystalline phase metal wiring of the semiconductor device. 삭제delete 삭제delete 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 확산방지막과 금속막 사이에 개재된 씨드막을 더 포함하는 것을 특징으로 하는 반도체 소자의 금속배선.And a seed film interposed between the diffusion barrier film and the metal film. 제 7 항에 있어서, The method of claim 7, wherein 상기 씨드막은 구리(Cu)막, 또는, 루테늄(Ru)막을 포함하는 것을 특징으로 하는 반도체 소자의 금속배선.The seed film may include a copper (Cu) film or a ruthenium (Ru) film. 제 1 항에 있어서, The method of claim 1, 상기 금속막은 구리막을 포함하는 것을 특징으로 하는 반도체 소자의 금속배선.The metal layer of the semiconductor device, characterized in that the copper film comprises a copper film. 반도체 기판 상에 배선 형성 영역을 갖는 절연막을 형성하는 단계;Forming an insulating film having a wiring formation region on the semiconductor substrate; 상기 배선 형성 영역의 표면을 포함한 절연막 상에 TaxCry막(0.3≤x≤0.8, 0.2≤y≤0.7), TaxCryNz막(0.2≤x≤0.8, 0.1≤y≤0.5, 0.1≤z≤0.3) 및 TaxNy막(0.3≤x≤0.5, 0.5≤y≤0.7)이 순차적으로 적층된 다층 구조를 포함하는 확산방지막을 형성하는 단계; 및Ta x Cr y films (0.3 ≦ x ≦ 0.8, 0.2 ≦ y ≦ 0.7), Ta x Cr y N z films (0.2 ≦ x ≦ 0.8, 0.1 ≦ y ≦ 0.5, on the insulating film including the surface of the wiring formation region) Forming a diffusion barrier layer including a multilayer structure in which 0.1 ≦ z ≦ 0.3 and Ta x N y films (0.3 ≦ x ≦ 0.5, 0.5 ≦ y ≦ 0.7) are sequentially stacked; And 상기 확산방지막 상에 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계;Forming a metal film to fill the wiring forming region on the diffusion barrier film; 를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 10 항에 있어서, The method of claim 10, 상기 TaxCry막과 TaxCryNz막은 각각 비정질상을 갖는 막으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The Ta x Cr y film and the Ta x Cr y N z film are each formed of a film having an amorphous phase. 제 10 항에 있어서, The method of claim 10, 상기 TaxNy막은 결정질상을 갖는 막으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The Ta x N y film is formed by a film having a crystalline phase. 삭제delete 삭제delete 삭제delete 제 10 항에 있어서, The method of claim 10, 상기 확산방지막을 형성하는 단계는, Forming the diffusion barrier film, 상기 배선 형성 영역의 표면을 포함한 절연막 상에 TaxCry막을 형성하는 단계;Forming a Ta x Cr y film on an insulating film including a surface of the wiring forming region; 상기 TaxCry막 상에 TaxNy막을 형성하는 단계; 및 Forming a Ta x N y film on the Ta x Cr y film; And 상기 TaxCry막과 상기 TaxNy막을 반응시켜 그 계면에 TaxCryNz막을 형성하는 단계;Reacting the Ta x Cr y film with the Ta x N y film to form a Ta x Cr y N z film at an interface thereof; 를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 16 항에 있어서, The method of claim 16, 상기 TaxCry막은 PVD(Physical Vapor Deposition) 방식, 또는, CVD(Chemical Vapor Deposition) 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The Ta x Cr y film is formed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method. 제 16 항에 있어서, The method of claim 16, 상기 TaxNy막은 PVD 방식, 스퍼터링(Sputtering) 방식 및 ALD(Atomic Layer Deposition) 방식 중 어느 하나의 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The Ta x N y film is formed by any one of a PVD method, a sputtering method and an atomic layer deposition (ALD) method. 제 18 항에 있어서, The method of claim 18, 상기 PVD 및 스퍼터링 방식은 N2 및 Ar을 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The PVD and sputtering method is a metal wiring formation method of a semiconductor device, characterized in that performed using N 2 and Ar. 제 18 항에 있어서, The method of claim 18, 상기 PVD 및 스퍼터링 방식은 1∼99mTorr의 압력 조건으로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of forming a metal wiring of the semiconductor device, characterized in that the PVD and sputtering method is carried out under a pressure condition of 1 ~ 99mTorr. 제 16 항에 있어서, The method of claim 16, 상기 TaxCry막과 상기 TaxNy막의 반응은 열 처리 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The reaction of the Ta x Cr y film and the Ta x N y film is performed by a heat treatment method. 제 21 항에 있어서, The method of claim 21, 상기 열 처리는 Ar 분위기, 또는, H2+N2 분위기에서 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The heat treatment is a metal wiring forming method of a semiconductor device, characterized in that carried out in an Ar atmosphere, or H 2 + N 2 atmosphere. 제 21 항에 있어서, The method of claim 21, 상기 열처리는 300∼600℃의 온도 조건으로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The heat treatment is a metal wiring forming method of a semiconductor device, characterized in that performed at a temperature condition of 300 ~ 600 ℃. 제 10 항에 있어서, The method of claim 10, 상기 확산방지막을 형성하는 단계 후, 그리고, 상기 금속막을 형성하는 단계 전, After the forming of the diffusion barrier film, and before the forming of the metal film, 상기 확산방지막 상에 씨드막을 형성하는 단계;Forming a seed film on the diffusion barrier film; 를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming a metal wiring of the semiconductor device further comprising. 제 24 항에 있어서, The method of claim 24, 상기 씨드막은 구리막, 또는, 루테늄막을 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the seed film comprises a copper film or a ruthenium film. 제 25 항에 있어서, The method of claim 25, 상기 구리막은 PVD 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The copper film is a metal wire forming method of a semiconductor device, characterized in that formed by the PVD method. 제 25 항에 있어서, The method of claim 25, 상기 루테늄막은 ALD 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The ruthenium film is a metal wiring forming method of the semiconductor device, characterized in that formed by ALD method. 제 10 항에 있어서, The method of claim 10, 상기 금속막은 구리막을 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the metal film comprises a copper film.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101202687B1 (en) 2011-02-16 2012-11-19 에스케이하이닉스 주식회사 Semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862516B2 (en) 2020-10-15 2024-01-02 Changxin Memory Technologies, Inc. Semiconductor structure manufacturing method
CN114373714A (en) * 2020-10-15 2022-04-19 长鑫存储技术有限公司 Method for manufacturing semiconductor structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007204A (en) 1999-06-24 2001-01-12 Nec Corp Structure of multilayer wiring and manufacture thereof
US6258710B1 (en) 1997-05-30 2001-07-10 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US6518668B2 (en) 1999-10-02 2003-02-11 Uri Cohen Multiple seed layers for metallic interconnects
KR20040007421A (en) * 2000-12-06 2004-01-24 에이에스엠 아메리카, 인코포레이티드 Copper interconnect structure having diffusion barrier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6258710B1 (en) 1997-05-30 2001-07-10 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
JP2001007204A (en) 1999-06-24 2001-01-12 Nec Corp Structure of multilayer wiring and manufacture thereof
US6518668B2 (en) 1999-10-02 2003-02-11 Uri Cohen Multiple seed layers for metallic interconnects
KR20040007421A (en) * 2000-12-06 2004-01-24 에이에스엠 아메리카, 인코포레이티드 Copper interconnect structure having diffusion barrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101202687B1 (en) 2011-02-16 2012-11-19 에스케이하이닉스 주식회사 Semiconductor device

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