CN1384979A - 用于生产芯片卡便携存储介质的方法 - Google Patents

用于生产芯片卡便携存储介质的方法 Download PDF

Info

Publication number
CN1384979A
CN1384979A CN00803573A CN00803573A CN1384979A CN 1384979 A CN1384979 A CN 1384979A CN 00803573 A CN00803573 A CN 00803573A CN 00803573 A CN00803573 A CN 00803573A CN 1384979 A CN1384979 A CN 1384979A
Authority
CN
China
Prior art keywords
chip
storage medium
join domain
cavity
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN00803573A
Other languages
English (en)
Inventor
P·帕特里斯
O·布鲁尼特
D·埃尔巴兹
B·卡尔瓦斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus SA filed Critical Gemplus SA
Publication of CN1384979A publication Critical patent/CN1384979A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743External electrical contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85203Thermocompression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01094Plutonium [Pu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

本发明涉及一种芯片卡型的便携存储介质的制造方法,所述存储介质除被设置在形成于该介质中的腔体内的集成电路芯片外,还具有由衬底支撑着的齐平的连接焊盘,芯片配备有和齐平的连接焊盘电连接的连接接线柱。所述方法包括生产所述连接焊盘的步骤以及把所述衬底元件和集成电路芯片装配在腔体中的步骤。根据本发明,在制造连接焊盘期间,在黏性绝缘膜(100)的第一面上印刷导电材料。在装配步骤,把黏性绝缘膜的第二面固定在所述腔体内。本发明可以用于生产芯片卡模块和芯片卡。

Description

用于生产芯片卡便携存储介质的方法
本发明涉及用于制造具有齐平接点的便携存储介质的方法。本发明可以应用于智能卡型的介质。
当前,智能卡被越来越多地用于进行各种操作,例如银行业务操作,电话和通信操作或各种识别操作。
接触智能卡具有和卡的表面齐平的金属化部分,这是通用标准ISO7816规定的。
这些金属化部分旨在用于和阅读器的读取头实现接触以便用电的方式传送数据。
按照当前的生产方法,智能卡是一种薄的便携物体,其尺寸是标准的。通常的标准ISO 7810相应于85mm长,54mmm宽和0.76mm厚的标准格式的卡。
具有若干种制造智能卡的方法。其中主要的方法基于在被称为微型模块的子部件中装配集成电路芯片,其中使用传统方法装配。
图1所示的传统方法包括设置集成电路芯片20,使其具有接触焊盘22的有源表面朝上,然后粘合集成电路芯片20,并相对的一面粘合在绝缘支撑板28上。绝缘板28本身被设置在由镀镍或镀金的铜金属板制成的接触栅格24上。在绝缘板28中形成连接线井21,并借助于所述连接井21利用连线26使芯片20的接触焊盘22和金属栅格24的接触区域相连。最后,最后,基于环氧树脂的封装树脂30保护芯片20和焊接连线26。然后,切割所形成的模块,并将其***预先制成的卡本体的腔体内。
这种方法的缺点是费用高。这是因为,铜、镍和金金属化大大增加了卡的成本。此外,制造步骤太多。
这是因为这种技术需要大量的制造步骤,这也使得制造成本增加。
因此,本发明的一个目的在于以低的成本提供一种能够大量生产的智能卡型的便携存储介质。
本发明的目的在于在尽可能大的程度上减少智能卡的制造成本,并且能够大量生产。
为此目的,本发明提出不使用常规的绝缘支撑,而以绝缘黏性材料代替绝缘支撑,所述绝缘黏性材料在把集成电路芯片***支撑膜上的连接区域时同时用作支撑的固定装置。
因此,本发明的目的在于提供一种具有由衬底支撑着的齐平的连接区域的智能卡型的便携存储介质的制造方法,集成电路芯片被设置在支撑中形成的腔体内,其具有和齐平的连接区域电连接的连接焊盘,所述方法包括生产所述连接区域的步骤以及把所述衬底元件和集成电路芯片装配在腔体中的步骤;其特征在于;
-形成连接区域的步骤借助于在黏性绝缘膜的第一面上印刷导电材料来实现,以及
-装配步骤通过把黏性绝缘膜的第二面固定在所述腔体内进行。
按照本发明的另一个特征,印刷材料是一种导电墨。
在腔体中装配的步骤包括首先把黏性膜围绕印制图形切割从而形成支撑着连接区域的黏性衬底的步骤和用所述黏性衬底的第二面作为粘合胶将黏性衬底粘结在腔体的边缘上的步骤。
黏性膜具有被也作为支撑的带保护的第二表面,以便使得能够在所述膜上连续地印制构成连接区域的图形。
所述黏性膜是可活化的。
具有黏性材料的膜是可以热活化的,并且包括改进的PES(聚乙烯)类,改进的PU(聚氨酯)类,或改进的PP(聚丙烯)类,或者共聚酰胺或酚醛塑料。
所述具有黏性材料的膜具有热固状态。
支撑带是一种由基于无黏性的纤维素或塑料,特别是纸和涂有硅的PET的材料制成的带。
膜的保护带被划痕,使得留出用于芯片的区域,并用于电连接并在带被除去时用于围绕连接区域保持一个刚性框架,所述框架在把元件装配在腔体中之前被除去。
所述方法包括把连接焊盘连接到黏性膜上的印制的图形的连接区域上的步骤。
按照一个实施例,当集成电路芯片被放置在和膜的第二面同一侧时,在芯片的连接焊盘和连接区域之间的电连接通过黏性膜的厚度来实现。
在芯片的连接焊盘上形成有导电凸起。
在集成电路芯片的连接焊盘和连接区域之间的电连接可以借助于被设置在黏性膜的厚度内的导电凸起来实现。
所述导电凸起在绝缘膜的厚度内的设置借助于对集成电路芯片施加压力来实现。
所述导电凸起在绝缘膜的厚度内的设置还通过加热黏性膜帮助进行。
按照另一个实施例,集成电路芯片被这样定向,使得其连接焊盘在印制的连接区域的上方,从而实现在芯片的连接焊盘和;连接区域之间的电连接。
按照一种改型,所述方法包括在黏性膜和连接区域相对的厚度中形成开孔以便露出连接区域的步骤。
在这种情况下,在芯片的连接焊盘和连接区域之间的电连接利用导电树脂来实现,所述导电树脂被施加在所述开孔中直到所述芯片上的连接焊盘。
按照一个实施例,所述方法包括在连接之前在黏性膜上输送集成电路芯片的步骤,以便形成微型模块。
切割膜上的不同的印制图形的步骤在把集成电路芯片输送到衬底上之前或之后进行。
所述把集成电路芯片和印制的黏性衬底装配到在支撑中形成的开口腔体中的步骤包括:
通过在衬底上进行热压把微型模块输送到腔体中,以便使衬底的底面粘结在腔体的壁上,连接区域被置于腔体的外侧,集成电路芯片被置于腔体的内侧。
按照另一个实施例,集成电路芯片首先被完全置于腔体的底部,使其有源的一面朝向腔体的开口,然后,
-黏性衬底被这样输送,使得印制的连接区域对着集成电路芯片的连接焊盘,所述输送包括热模制,以便能够同时实现连接区域和芯片的连接焊盘之间的电连接以及把黏性膜的底面固定在腔体壁上。
集成电路芯片与连接区域的电连接也可以被密封在保护树脂中。
本发明的另一个目的在于提供一种智能卡型的便携支撑模块,其具有由衬底膜的第一面承载着的连接区域,其中衬底是一种黏性物质,并且其中所述连接区域是一种印制的导电材料。
所述便携支撑模块还具有被固定到所述衬底膜的第二面的集成电路芯片。
本发明的另一个目的在于,提供一种包括所述模块的智能卡型的便携存储介质。
本发明的其它目的和优点将通过结合附图阅读下面的非限制性的说明得知,其中:
图1是已经说明的表示常规的制造智能卡的方法的截面图;
图2,3A,3B表示按照本发明的方法生产的图形带,表示连续的微型模块的制造,所述的图形带以截面图、顶视图和底视图的形式表示;
图4是按照本发明的制造方法的连接步骤的第一实施例生产的图2,3A,3B所示的图形带的微型模块的截面图;
图5是按照第二实施例生产的另一种微型模块的截面图;
图6A-6C表示本发明的第三连接方法生产的另一种微型模块的衬底,所述衬底分别以截面图、底视图和底视图表示;
图7是按照本发明的制造方法的连接步骤的第三施例生产的图6A-6C的衬底的微型模块的截面图;
图8是包括图4的微型模块的智能卡的截面图;
图9是包括按照图4的衬底的智能卡的截面图;
图10是包括图5的微型模块的智能卡的截面图;
图11是包括图7微型模块的智能卡的截面图;
图2,3A,3B分别以图形带的截面图、顶视图和底视图的形式示意地表示旨在能够连续地生产微型模块的方法。所述的带包括绝缘材料100,所述绝缘材料由保护材料110支撑着,所述保护层用于对其加固并对其进行连续地驱动。
实际上,绝缘材料100相当精细而柔软,因此必须由刚性较强的材料支撑,以便能够被连续地驱动。所述绝缘材料100用于形成微型模块的支撑。其详细情况在下面说明。
保护材料110最好比绝缘材料100宽,并具有孔111,沿着其长边均匀分布,在其一侧或两侧。这些孔111用于通过一种具有齿轮的***驱动图形带,进行自动的带输送(AST)。使用AST的构思确定微型模块的衬底的尺寸使得能够具有小的间距,例如,在两个图形150之间的距离可以是9.5mm。
还可以使用滚动输送***输送图形带,其中利用指示器图形代替孔,所述指示器图形在把图形150印在绝缘材料100上的同时被印在保护材料110上,其作用是使得能够利用光学装置定位。
按照本发明的一个特征,生产微型模块的步骤包括,首先在所述带上,更具体地说,在绝缘材料100的没有保护材料110覆盖的顶面上,利用导电墨印刷形成图形150。所述各个图形150包括用于连接端接部分的连接区域151。这些连接区域151足够靠近,使得能够和集成电路芯片的相关的连接焊盘充分实现电连接。其厚度一般为大约10mm。
用于形成连接区域151的导电墨的印刷可以按照不同的已知技术来实现。因而,可以利用焊盘印刷、偏移印刷、喷墨印刷、丝网印刷或者使用掩模的喷洒印刷等技术。
不同的印刷技术使得能够利用不同种类的导电墨。因而导电墨可以包括溶解墨,其含有利用具有导电填料的溶剂增溶的聚合物树脂,其通过溶剂的蒸发得到。所述的油墨还可以是一种或两种成分的热固油墨,在UV照射下聚合的油墨,用于铜焊的膏的混合物或金属合金。
因此,所述图形带使得能够由在带上重复印制的图形150和被输送到带上并和每个图形连接的集成电路芯片连续地制造微型模块。
从使印制图形150和带的其余部分分开的观点看来,每个印制的图形150可以在芯片输送的前后被切割。从而获得绝缘衬底,形成用于先前印制的包括连接区域151的端接部分的支撑。
实际上,正是绝缘材料100形成集成电路芯片的主要支撑。
所述绝缘材料100还具有黏性。这种粘结材料例如可以在一定温度下恢复黏性。也可以用另外的方法例如施加压力,使其恢复黏性。
绝缘的粘结材料100的顶面支撑着印制的连接区域151,旨在和智能卡的表面配合齐平,其底面在黏性恢复时具有黏性,使得能够把微型模块固定在卡的本体上。
在印制连接区域151期间,或者在通过输送***驱动图形带期间,有黏性的底面还受到保护材料110的保护,防止其在制造过程中激活太快。
黏性材料100例如是改进的PES(聚乙烯)类,改进的PU(聚氨酯)类,或改进的PP(聚丙烯)类,或者共聚酰胺或酚醛塑料。最好是在环境温度下没有黏性,因而使得能够和常规的塑料板一样进行处理。也可以包括一定数量的热塑材料。
在另一个例子中,使用的黏性材料100是一种非自粘的热塑反应胶,由Beiersdorf公司提供,标号为TESA 8420。其主要含有酚醛树脂和腈橡胶。可以只具有热塑性能,并根据温度呈热塑状态。最好热活化的材料在活化之后具有不可逆状态(或不能再反应状态)。
热粘膜100的厚度相当薄,因而其没有足够的刚性,没有支撑便不能被驱动。所述厚度最好在30和60mm之间。
保护材料110可以包括纸、纸板或PET塑料,并被涂覆少量的硅。其具有足够的刚性使得图形带能够被驱动。
不过,为了处理绝缘的黏性材料100的底面,主要是在其上通过膜100的厚度输送集成电路芯片到连接区域,需要能够除去部分或全部保护材料110。
实际上,最好部分地除去保护材料110,主要除去位于区域113的部分,其被保留用于输送和连接集成电路芯片。这便是所述材料沿着划线112划线的原因,为了保留区域113用于芯片输送,并且为了保持刚性的框架114使图形带具有一定的刚性,并为了同时保护热活化的黏性材料,阻止其过早地活化。
在包括形成微型模块的所述方法的一步中,集成电路芯片被输送便把其连接焊盘连接到先前印制的连接区域151上。
集成电路芯片可以按照不同的固定方式被输送。
第一种方法,如图4所示,包括在热活化的黏性支撑100的底面输送芯片20,使得芯片20的具有连接焊盘210的有源表面向着支撑的底面。
在这种情况下,在集成电路芯片200被输送之前,在其连接焊盘200上形成导电凸起220。这些凸起220最好被嵌入热活化的黏性衬底100的厚度内,因而使得在芯片200的连接焊盘和与其相关的连接区域151之间实现电连接。
导电凸起220最好被形成具有尖的边沿的几何形状,例如形成圆锥形,以便更容易地通过热活化的黏性材料100。这种黏性材料精细柔软,具有容易穿孔的特性。
凸起220例如通过淀积金属而被形成,或者通过丝网印刷导电墨,或者通过生成不可氧化的电解类的涂层而形成。在这种情况下,凸起220的厚度被这样确定,使得其等于或略小于印制的连接区域151的厚度和热活化的黏性材料100的衬底的厚度之和。因此,其厚度最好在40和50mm之间。
为了有助于凸起220穿过衬底的厚度,对要被输送的元件施加一个小的压力。然后,可以利用热压对衬底局部加热,主要通过在被保留用于输送芯片内的区域内的芯片,从而使在该区域内的黏性材料活化,不仅有助于使凸起穿过衬底的厚度,也有助于通过粘连把芯片200固定到衬底100上。
借助于这种芯片输送方法,可以用一种或用相同的操作实现芯片的电连接和固定。此外,在支撑200中***凸起220确保可靠地保持芯片。
这种第一输送方法的一种改型如图5所示。这种改型包括在支撑着先前印制的连接区域151的衬底100的顶面上按照“翻转”型芯片的固定方法输送芯片230。
在这种情况下,在芯片230的连接焊盘上形成的凸起232具有等于或略小于连接区域151的厚度。
为了使凸起容易穿过连接区域,芯片的输送最好通过热压进行。通过加热使构成连接区域151的导电墨软化。
当热压操作结束时,使获得的互连的组件在环境温度下冷却,从而使导电墨恢复固态和初始形状。在这种情况下,最好是用保护树脂235保护芯片20和电连接。
芯片也可以在刚形成的印制导电墨上被输送,并在线进行干燥。
用于输送芯片的另一种方法如图6A-6C和图7所示。在这种情况下,在输送芯片以前,在绝缘的黏性膜100的厚度中对着先前印制的连接区域151形成小孔130,以便把连接区域露出。
这种操作包括通过划刻,或通过激光雕刻或通过任何其它方法除去黏性材料而形成开孔130,最好不破坏连接区域151。
接着使芯片250的后面在对着连接区域的有黏性的一面上被输送。
在刚刚说明的用于输送芯片的一种不同的方法中,芯片及其电连接可以被封装在绝缘树脂中,以便保护其不受外部气候或机械方面的影响。
图8示意地表示按照第一实施例的具有齐平接触部分的智能卡的存储介质的截面图。
这个实施例包括在卡本体300中的敞开的腔体310内输送按照图4所示的第一实施例获得的微型模块M1。
模块M1的顶面被确定为旨在和卡300的表面配合齐平的表面。连接区域151例如按照ISO标准被形成,并作为用于访问智能卡的接点。
卡本体300按照常规方法被形成,例如通过在模具中注入塑料。腔体310通过对卡本体进行研磨或者通过在制造时通过注入模制而形成,这是较经济的。
腔体310具有适合于微型模块的几何形状。例如可以呈星形或碗形,具有两个平的底P1和P2,或者呈具有一个平的底和斜的壁的碗形。
在图8中,所示的卡是具有两个平底的碗形的。在这种情况下,第一个平底P11被形成用于支撑MMM的衬底100,其深度相应于衬底100的厚度。第二个平底P2的一部分用于接收可能涂覆有保护树脂的包括集成电路芯片200的微型模块MI的部分。
在***微型模块M1之前,最后除去在制造微型模块时保留的保护材料的框架。然后,微型模块的衬底100的底面的框架的位置通过加热被局部活化,从而使其具有黏性。
通过热压,微型模块M1被输送到腔体310上,使得通过加热具有黏性的衬底100的底面粘结在第一个平的底P1上,以便固定模块。因此,衬底100具有双重功能;其作为模块的支撑,在把模块***腔体300时,还用于固定模块。
在一种变形中,也可以把模块设置在卡本体的模制空间内,并直接地固定在卡本体上。
图9示意地表示按照图4所示的改型的实施例制造的具有齐平接点的智能卡的截面图。
在这种改型中,模块MP1不包括芯片。在卡本体300中形成被保留用于模块MP1的敞开的腔体310的同时,集成电路芯片200被置于腔体的底部。
被预先印制并切割好的模块的有黏性的支撑100被这样输送,使得印制的连接区域151位于集成电路芯片200的连接焊盘的相对侧。
所述的输送包括热轧,使得借助于导电凸起220能够同时实现连接区域151和芯片200上的连接焊盘之间的电连接,并利用加热产生的黏性把支撑100的底面固定到腔体的壁上。
图10示意地表示按照图5所示的改型的实施例具有齐平接点的智能卡的截面图,其中包括按照图5所示的改型的实施例获得的微型模块M2。在这种改型中,在除去原来保留的任何保护框架之后,利用热轧把微型模块M2输送到卡本体400的腔体410中,所述的热压使支撑100的底面活化,从而具有黏性。热压步骤借助于工具430实现,其形状和腔体410的形状相适应。
在这种改型的情况下,用于热压的工具430最好具有槽431,旨在用于保护微型模块的芯片230。一旦模块M2被固定在腔体410中,芯片也可以被封装在保护树脂420中。
图11示意地表示按照第二改型的实施例具有齐平接点的智能卡的截面图,其中包括按照图7所示的改型的实施例获得的微型模块M2。在这种情况下,按照前述的方法,即借助于其形状和腔体510的形状相适应的工具,把微型模块M3输送到卡本体500的腔体510内。
按照本发明的用于制造智能卡的方法包括较少的步骤,并且不使用任何成本高的材料。此外,支撑连接区域的膜能够把微型模块固定在卡本体的腔体内而不使用黏胶。因而,按照本发明的方法生产的微型模块和智能卡的制造成本被大大降低。
在应用本发明时,粘结材料可以被机械地加强,尤其是利用玻璃纤维制造的加强纤维进行加强。

Claims (26)

1.一种具有由衬底支撑着的齐平的连接区域的智能卡型的便携存储介质的制造方法,集成电路芯片被设置在支撑中形成的腔体内,其具有和齐平的连接区域电连接的连接焊盘,所述方法包括生产所述连接区域的步骤以及把所述衬底元件和集成电路芯片装配在腔体中的步骤;其特征在于;
-形成连接区域(150)的步骤借助于在黏性绝缘膜(100)的第一面上印刷导电材料来实现,以及
-装配步骤通过把黏性绝缘膜(100)的第二面固定在所述腔体内进行。
2.如权利要求1所述的用于制造存储介质的方法,其特征在于,印刷材料是一种导电墨。
3.如权利要求1或2所述的用于制造存储介质的方法,其特征在于,在腔体中装配的步骤包括首先把黏性膜围绕印制图形切割从而形成支撑着连接区域的黏性衬底的步骤和用所述黏性衬底的第二面作为粘合胶将黏性衬底粘结在腔体的边缘上的步骤。
4.如权利要求1或2或3所述的用于制造存储介质的方法,其特征在于,黏性膜具有被也作为支撑的带(110)保护的第二表面,以便使得能够在所述膜上连续地印制构成连接区域的图形。
5.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,所述黏性膜是可活化的。
6.如权利要求5所述的用于制造存储介质的方法,其特征在于,具有黏性材料的膜是可以热活化的,并且包括改进的PE(聚乙烯)类,改进的PU(聚氨酯)类,或改进的PP(聚丙烯)类。
7.如权利要求6所述的用于制造存储介质的方法,其特征在于,所述具有黏性材料的膜具有热固状态。
8.如权利要求4所述的用于制造存储介质的方法,其特征在于,支撑带(110)是一种涂有硅的纸或PET的材料制成的带。
9.如权利要求4到6任何一个所述的用于制造存储介质的方法,其特征在于,膜的保护带被划痕,使得留出用于芯片的区域,并用于电连接并在带被除去时用于围绕连接区域保持一个刚性框架,所述框架在把元件装配在腔体中之前被除去。
10.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,所述方法包括把连接焊盘连接到黏性膜上印制的图形的连接区域上的步骤。
11.如权利要求10所述的用于制造存储介质的方法,其特征在于,当集成电路芯片被放置在和膜的第二面同一侧时,在芯片的连接焊盘和连接区域之间的电连接通过黏性膜的厚度来实现。
12.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,在芯片的连接焊盘上形成有导电凸起。
13.如权利要求11或12所述的用于制造存储介质的方法,其特征在于,在集成电路芯片的连接焊盘和连接区域之间的电连接可以借助于被设置在黏性膜的厚度内的导电凸起来实现。
14.如权利要求10到13任何一个所述的用于制造存储介质的方法,其特征在于,所述导电凸起在绝缘膜的厚度内的设置借助于对集成电路芯片施加压力来实现。
15.如权利要求11到14任何一个所述的用于制造存储介质的方法,其特征在于,所述导电凸起在绝缘膜的厚度内的设置还通过加热黏性膜帮助进行。
16.如权利要求10到14任何一个所述的用于制造存储介质的方法,其特征在于,集成电路芯片被这样定向,使得其连接焊盘在印制的连接区域的上方,从而实现在芯片的连接焊盘和连接区域之间的电连接。
17.如权利要求8到14任何一个所述的用于制造存储介质的方法,其特征在于,所述方法包括在黏性膜和连接区域相对的厚度中形成开孔以便露出连接区域的步骤。
18.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,在芯片的连接焊盘和连接区域之间的电连接利用导电树脂来实现,所述导电树脂被施加在所述开孔中直到所述芯片上的连接焊盘。
19.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,所述方法包括在连接之前在黏性膜上输送集成电路芯片的步骤,以便形成微型模块。
20.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,切割膜上的不同的印制图形的步骤在把集成电路芯片输送到衬底上之前或之后进行。
21.如权利要求6或20所述的用于制造存储介质的方法,其特征在于,所述把集成电路芯片和印制的黏性衬底装配到在支撑中形成的开口腔体中的步骤包括:
通过在衬底上进行热压把微型模块输送到腔体中,以便使衬底的底面粘结在腔体的壁上,连接区域被置于腔体的外侧,集成电路芯片被置于腔体的内侧。
22.如权利要求1到16任何一个所述的用于制造存储介质的方法,其特征在于,
-集成电路芯片首先被完全置于腔体的底部,使其有源的一面朝向腔体的开口,然后,
-黏性衬底被这样输送,使得印制的连接区域对着集成电路芯片的连接焊盘,所述输送包括热模制,以便能够同时实现连接区域和芯片的连接焊盘之间的电连接以及把黏性膜的底面固定在腔体壁上。
23.如前面任何一个权利要求所述的用于制造存储介质的方法,其特征在于,集成电路芯片与连接区域的电连接也可以被密封在保护树脂中。
24.一种智能卡型的便携支撑模块,其具有由衬底膜的第一面承载着的连接区域,其中衬底是一种黏性物质,并且其中所述连接区域是一种印制的导电材料。
25.如权利要求24所述的便携支撑模块,其特征在于,所述便携支撑模块还具有被固定到所述衬底膜的第二面的集成电路芯片。
26.一种智能卡型的便携存储介质,其特征在于其包括所述模块。
CN00803573A 1999-02-08 2000-01-24 用于生产芯片卡便携存储介质的方法 Pending CN1384979A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9901454A FR2789505B1 (fr) 1999-02-08 1999-02-08 Procede de fabrication de support de memorisation portable de type carte a puce
FR99/01454 1999-02-08

Publications (1)

Publication Number Publication Date
CN1384979A true CN1384979A (zh) 2002-12-11

Family

ID=9541732

Family Applications (1)

Application Number Title Priority Date Filing Date
CN00803573A Pending CN1384979A (zh) 1999-02-08 2000-01-24 用于生产芯片卡便携存储介质的方法

Country Status (5)

Country Link
EP (1) EP1153432A1 (zh)
CN (1) CN1384979A (zh)
AU (1) AU3059000A (zh)
FR (1) FR2789505B1 (zh)
WO (1) WO2000048250A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702658A (zh) * 2014-11-12 2016-06-22 矽品精密工业股份有限公司 半导体封装件及其制法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10208168C1 (de) 2002-02-26 2003-08-14 Infineon Technologies Ag Datenträgerkarte
FR2846446B1 (fr) * 2002-10-28 2005-02-18 Oberthur Card Syst Sa Carte a puce comportant un composant debouchant et un procede de fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3123198C2 (de) * 1980-12-08 1993-10-07 Gao Ges Automation Org Trägerelemente für einen IC-Baustein
DE3639630A1 (de) * 1986-11-20 1988-06-01 Gao Ges Automation Org Datentraeger mit integriertem schaltkreis und verfahren zur herstellung desselben
FR2684471B1 (fr) * 1991-12-02 1994-03-04 Solaic Procede de fabrication d'une carte a memoire et carte a memoire ainsi obtenue.
DE19713641A1 (de) * 1997-04-02 1998-10-08 Ods Gmbh & Co Kg Minichipkarte sowie Verfahren zu ihrer Herstellung

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702658A (zh) * 2014-11-12 2016-06-22 矽品精密工业股份有限公司 半导体封装件及其制法
CN105702658B (zh) * 2014-11-12 2019-04-05 矽品精密工业股份有限公司 半导体封装件及其制法

Also Published As

Publication number Publication date
WO2000048250A1 (fr) 2000-08-17
FR2789505A1 (fr) 2000-08-11
FR2789505B1 (fr) 2001-03-09
EP1153432A1 (fr) 2001-11-14
AU3059000A (en) 2000-08-29

Similar Documents

Publication Publication Date Title
KR100846272B1 (ko) Rfid 태그 및 그 제조 방법
US7352588B2 (en) Semiconductor device and a method for manufacturing the same
US8819918B2 (en) Manufacturing method for a dual interface card
CN1969287A (zh) 复合卡及其制造方法
EP1890340B1 (en) Method for producing a porcelain enameled substrate for light-emitting device mounting.
CN101562191B (zh) 带腔体的光电封装件及其生产方法
CN1591884A (zh) 固态象传感装置的制造方法
US20060172464A1 (en) Method of embedding semiconductor element in carrier and embedded structure thereof
CN1050681C (zh) 非接触型集成电路卡及其制造方法和设备
CN1280693A (zh) 制造一种带芯片和/或天线的电子器件的方法以及用该方法获得的器件
CN1977282A (zh) 天线电路、ic***物、ic标签
CN107209870B (zh) 芯片卡制造方法和利用该方法获得的芯片卡
JP2007042087A (ja) Rfidタグ及びその製造方法
CN1351733A (zh) 一种采用廉价绝缘材料的便携式集成电路电子设备的制造方法
US7431218B2 (en) RFID tag, module component, and RFID tag fabrication method
US20190026621A1 (en) Method for Manufacturing a Smart Card Module and a Smart Card
CN1384979A (zh) 用于生产芯片卡便携存储介质的方法
CN1309796A (zh) 制造包括至少一个集成电路芯片的便携式电子装置的方法
JPH09286187A (ja) Icカード、icカード製造用中間体およびicカードの製造方法
JP2007310482A (ja) Icカード、icカードの製造方法、icカードの製造装置、icカード用基材の製造方法、およびicカード用基材の製造装置
CN1351732A (zh) 制造带有低成本介电质的接触型智能卡的方法
JP3769332B2 (ja) Icカードの製造方法
CN108960006B (zh) 指纹识别模块及其制作方法
CN100346452C (zh) 电子零件及其制造方法
CN1303521A (zh) 制造微模块方法和制造含有微模块的存储媒体的方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication