CN1340211A - 具有深衬底接触的半导体器件 - Google Patents

具有深衬底接触的半导体器件 Download PDF

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CN1340211A
CN1340211A CN00803688A CN00803688A CN1340211A CN 1340211 A CN1340211 A CN 1340211A CN 00803688 A CN00803688 A CN 00803688A CN 00803688 A CN00803688 A CN 00803688A CN 1340211 A CN1340211 A CN 1340211A
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semiconductor device
substrate
ground connection
connection
semiconductor
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CN1160786C (zh
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T·约翰松
C·尼斯特伦
A·赖丁
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Infineon Technologies AG
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Telefonaktiebolaget LM Ericsson AB
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Abstract

本发明涉及到一种排列在具有初始掺杂(p+)的半导体衬底(102)的表面(106)处的半导体器件(100),所述器件具有一种电连接(101),它包含至少一个由高电导率材料特别是不同于衬底的材料制作,在所述初始掺杂的衬底(102)与衬底的所述表面(106)之间的柱,特别是金属柱。此器件具有至少一个安排成连接到封装件(300)上的接地插脚(301)的接地连接(E)。此接地连接(E)被安排成用所述电连接(101)连接到所述接地插脚(301),其中初始掺杂的衬底(102)被安排成经由与所述表面(106)相反的衬底反面(124)连接到所述接地插脚(301),从而被安排来建立所述接地连接(E)与所述接地插脚(301)之间的连接。

Description

具有深衬底接触的半导体器件
发明的技术领域
本发明涉及到半导体器件以及安装在封装件中的包含至少具有一个半导体器件的半导体电路的半导体集成电路。
相关技术的描述
现代通信电子学的工作频率范围从几百兆周直到进入千兆周。功率晶体管在大信号电平和高电流密度下工作最有效。目前的高压硅射频功率晶体管能够在高于2GHz的频率下提供几百瓦的输出功率，并典型地在25V下工作。这些晶体管通常被用于象蜂窝基站、数字广播、或电视发射机中的输出放大器那样的固定式应用中。
对于无线手机这样的应用，电源电压被限制在2-6V范围(电池工作)，输出功率在0.1-4W范围，而工作频率在1-3GHz范围。
这一领域中占优势的技术是GaAs基的，但硅基电路目前正在这一领域发展。硅的主要优点是价格显著地更低，而其缺点是高频性能更为有限。
所有射频应用的一个普遍困难是当工作频率提高而电源电压降低时要保持功率增益和输出功率。来自键合引线的发射极/源寄生电感，由于它构成向负载传送功率的关键部分而对这一性能特别有害。这最终将导致对器件尺寸和器件在某些应用中用途的限止。这对于具有较低电压和较低功率的集成放大器以及对于双极和MOS技术中的高压射频功率晶体管，都是适用的。对于这些类型的器件，到地的低阻抗连接是至关重要的。
制造在半导体衬底上的包含多个半导体器件的集成电路，通常被置于具有插脚或用来接触集成电路的其它装置的封装件中。插脚一般经由能够具有不同长度的键合金属丝被连接到集成电路。接地的插脚可以被连接到其上安装集成电路的引线框即所谓熔合引线框，其中衬底的反面与引线框电接触。
从集成电路上的键合焊点到插脚的正常连接是经由长的键合金属丝得到的，对于直径为10-30μm(1-2mil)的键合金属丝，其电感约为1nH/mm，而直流电阻约为3mΩ/mm。为了尽量减小电感和电阻而采用平行的键合金属丝。
封装件中的键合金属丝的典型长度是1-2mm，每个金属丝引起的电感为1-2nH。借助于从键合焊点向下到用于接地连接的引线框引入短的键合引线，可以将电感减小到0.2nH，在2GHz下产生大约2.5欧姆的阻抗。用来在横向DMOS晶体管的源与衬底之间产生低阻抗接触的现有技术包含高掺杂的扩散柱或包括如D’Anna等人的美国专利5821144中所述的包括用导体填充的沟槽在内的接触结构。
用于GaAs MESFET的产生低阻抗接触的其它类型的接触，具有贯穿衬底的由金属填充的腐蚀孔。
Norstrom等人在专利申请WO 97/35344中描述了高频应用的半导体器件的钨填充的深衬底接触。此接触提供了第一金属层和高掺杂的衬底之间通过其中实现所述器件的低掺杂的外延层的直接耦合装置。此专利申请包含用作地平面、降低干扰和串扰和屏蔽的方法和器件。
发明的概述
本发明的目的是提供一种具有接地连接的半导体器件，其中所述接地连接被安排成特别是在高频下经由低阻抗连接而连接到封装件的接地插脚。
本发明的另一目的是提供一种集成电路，它包含半导体电路，其安装在封装件中的至少一个半导体器件在所述器件的接地连接与所述封装件上的接地插脚之间具有低阻抗连接。
利用排列在具有初始掺杂的半导体衬底表面处的半导体器件，达到了这些目的，所述器件包含至少一个由高电阻率材料制作在所述初始掺杂的衬底与衬底的所述表面之间包含制成的柱的电连接，且所述器件具有至少一个安排成连接到封装件上的接地插脚的接地连接，所述至少一个接地连接被安排成用所述电连接连接到所述接地插脚，其中所述衬底被安排成经由与所述表面相反的衬底反面连接到所述接地插脚，从而被安排来建立所述接地连接与所述接地插脚之间的连接。
本发明的优点是可以在器件的接地连接与封装件上的接地插脚之间建立低阻抗接触。，特别是对于高频应用。
另一优点是，由于接地连接经由衬底的反面被连接，故半导体衬底表面上所需的用来连接半导体器件的键合焊点较少。
再一个优点是，由于所需的键合焊点较少，故根据本发明，封装件中的电路的键合金属丝连接得更快。
本发明还有一个优点是，借助于使每个接地连接具有多个柱，大量电流可以通过接地连接传导。
另一优点是，通过至少一个柱，可以容易地连接具有接地连接的任何类型的器件，而无须对根据本发明具有至少一个半导体器件的集成电路上的键合焊点建立导电图形。
下面参照附图来描述本发明。
附图的简要描述
图1示出了半导体电路的局部剖面图，它包含具有根据本发明的接地连接的双重多晶硅自对准双极晶体管。
图2a-2e示出了图1的半导体器件和电连接的制造步骤。
图3示出了安装在封装件中的集成电路的透视图，其半导体电路具有根据本发明的连接到接地插脚的接地连接。
优选实施方案的详细描述
图1示出了半导体电路的局部剖面图，它包含至少一个具有根据本发明的电连接101的双重多晶硅自对准双极晶体管100。
半导体器件100，在此实施例中是双极NPN晶体管，被制造在具有第一类型p+初始高掺杂的衬底102上，其上生长第一外延层，以形成具有与所述第一类型p+相反的第二类型n+高掺杂的掩埋层103。在掩埋层103的顶部上生长第二外延层，以形成n阱104，其中第二外延层具有第二类型n掺杂。掩埋层103和n阱104一起代表双极晶体管100的收集极区。
半导体器件区被从衬底表面106向下延伸到掩埋层103下方进入初始掺杂的衬底的隔离装置105确定。具有收集极C的第一窗口以及发射极E和双重基极B的第二窗口的场氧化物107覆盖衬底的表面。如同通常在这种半导体器件中那样，第二掺杂类n+的高掺杂区108从第一窗口的表面向下延伸到掩埋层103。收集极C经由诸如钨的高电导率的导体110、金属接触111、和掺杂的多晶硅层125，被连接到高掺杂区108。
在第二窗口中的表面处制作薄的区域109，它具有第一类型p掺杂，代表基区。在这一区域109的表面处，制作3个分隔的区域112、113。具有第二类型n+掺杂的高掺杂区被制作在中央，形成发射极区112。此发射极区被连接到掺杂的多晶硅层114，多晶硅层114又经由高电导率的金属接触115和连接体116被连接到发射极E。
基极接触区113被制作在发射极区112的二侧，其上经由高电导率的掺杂的多晶硅层117、金属接触118、和连接体119而连接每一个基极B。基极接触区113向下延伸穿过基极区109进入n阱104。
器件被氧化物120和PSG(磷硅酸盐玻璃)层覆盖。
然后，在半导体器件区外腐刨沟槽，以形成柱121作为电连接101的一部分。此沟槽从PSG层向下延伸到初始掺杂的衬底，其中制作具有第一类型P++高掺杂的柱接触区122。柱121由诸如金属，特别是钨的高电导率材料制成。柱经由连接体123被连接到需要接地的半导体器件的任何部分，在此情况是发射极接触E。
以这种方式，建立了从发射极接触E经由连接体123以及包含柱121和柱接触区122的电连接101到可被接地的衬底的反面124的连接。若大电流要通过建立的连接，则此电连接可以包含多个柱。
图2a-2e示出了包括图1的电连接的半导体器件的制造步骤。此图主要示出了半导体器件，在此实施例中是双极晶体管被制作在隔离装置105之间的区域，柱121位于此区域外面。
图2a示出了已经被加工到直至完成下列部分工艺时的衬底102(p+型)：生长第一外延层以形成掩埋层103(n+型)，生长第二外延层以形成n阱104(n型)，引入隔离装置105，淀积具有第一和第二窗口的第一氧化物107，产生从第一窗口表面106向下延伸到掩埋层103的高掺杂区(n+型)，在第二窗口表面处产生基极区109(p型)，淀积第一类型p+高掺杂的多晶硅层117，以及在多晶硅层117上淀积第一氧化物层201。所有这些步骤都以本技术领域熟练人员熟悉的方式执行。
图2b示出了半导体器件的剖面图，其中发射极窗口202和收集极窗口被制作在第一氧化物层201和多晶硅层117中，向下达及基极区109。第二氧化物层203则被淀积在半导体器件的顶部上。
图2c示出了半导体器件的剖面图，其中第二氧化物层203已经被腐蚀掉，仅仅留下二个间隔204，使发射极窗口变窄。具有第二类型n+高掺杂的第二多晶硅层被淀积在器件上，并如图2d所示被腐蚀，以形成发射极窗口202上的多晶硅层114和作为收集极窗口的第一窗口上的多晶硅层125。对衬底进行退火，致使3个区域112、113进入基极区109。发射极区112被直接形成在发射极窗口202中的多晶硅层下方，而基极接触区113被形成在第一多晶硅层117下方的发射极区112二侧，其中所述基极接触区113向下延伸穿过基极区109进入n阱104。
图2e示出了一个剖面图，其中金属接触111、115、118被制作，以建立到双极晶体管100的电接触。本技术领域熟练人员对这一工艺是众所周知的。
图1示出了了得到的半导体器件100，它包括从发射极连接E到衬底反面124的连接。
图1和2a-2e仅仅描述了NPN双极晶体管，但当然可以有其接地连接被连接到衬底反面的图1所示的其它类型的半导体器件，例如PNP双极晶体管、MOS晶体管、或分立元件。半导体器件当然可以是由多个不同的半导体器件组成的半导体电路的一部分。主要的优点是可以用数目更少的接触焊点来获得半导体电路的更紧密的布局。
图3示出了包含封装件302的集成电路300的透视图，它包括插脚和接触焊点303、键合金属丝304、以及至少包含一个具有根据本发明的连接到接地插脚301的接地连接E的半导体器件100的半导体电路306。
除了接地插脚301之外，各个插脚经由接触焊点303和键合金属丝304分别被连接到半导体电路306上的至少一个焊点。接地插脚301最好被直接连接到其上电学上固定半导体电路306的反面124的引线框305。
现有技术集成电路通常具有大量键合金属丝来建立从集成电路到封装件的接地连接。用来实现所有连接的时间，取决于要固定的键合金属丝的数目。借助于减少所需键合焊点的数目，并根据本发明实现接地连接，由于要固定的键合金属丝较少，故用来将键合金属丝固定到电路上的键合焊点的过程被显著地加快。
可以采用其它的电连接半导体电路反面的方法，例如经由至少一个分立的键合金属丝来连接引线框。

Claims (10)

1.一种排列在具有初始掺杂(p+)的半导体衬底(102)的表面(106)处的半导体器件(100)，所述器件具有一种电连接(101)，它包含至少一个由高电导率材料制作，在所述初始掺杂的衬底与衬底的所述表面(106)之间的柱(121)，所述器件具有至少一个安排成连接到封装件(300)上的接地插脚(301)的接地连接(E)，其特征在于，所述至少一个接地连接(E)被安排成用所述电连接(101)连接到所述接地插脚(301)，其中所述衬底(102)被安排成经由与所述表面(106)相反的衬底反面(124)连接到所述接地插脚(301)，从而被安排来建立所述接地连接(E)与所述接地插脚(301)之间的连接。
2.根据权利要求1的半导体器件，其特征在于，所述材料的类型不同于衬底(102)。
3.根据权利要求2的半导体器件，其特征在于，所述至少一个柱(121)是金属柱。
4.根据权利要求1-3中任何一个的半导体器件，其特征在于，所述柱(121)延伸进入衬底(102)，其延伸深度比其中引入和/或存在PN结的位置更深。
5.根据权利要求1-4中任何一个的半导体器件，其特征在于，各个柱(121)的上端经由导电材料(123)，特别是高电导率的材料，特别是金属材料，被连接到所述接地连接(E)。
6.根据权利要求1-5中任何一个的半导体器件，其特征在于，所述半导体器件是高频器件。
7.根据权利要求6的半导体器件，其特征在于，所述器件是功率器件。
8.根据权利要求6或7的半导体器件，其特征在于，所述器件是双极晶体管，且所述接地连接是发射极连接。
9.根据权利要求6或7的半导体器件，其特征在于，所述晶体管是MOS晶体管，且所述接地连接是源连接。
10.一种安装在封装件(302)中的半导体集成电路，所述封装件具有多个连接到半导体电路(306)的插脚，且所述电路具有多个半导体器件，其特征在于，至少一个所述半导体器件是根据 1-9中任何一个的半导体器件。
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