CN1314109C - 多层芯片载体及其基板和在芯片载体上展开信号焊盘的重新分配方法 - Google Patents
多层芯片载体及其基板和在芯片载体上展开信号焊盘的重新分配方法 Download PDFInfo
- Publication number
- CN1314109C CN1314109C CNB2004100868608A CN200410086860A CN1314109C CN 1314109 C CN1314109 C CN 1314109C CN B2004100868608 A CNB2004100868608 A CN B2004100868608A CN 200410086860 A CN200410086860 A CN 200410086860A CN 1314109 C CN1314109 C CN 1314109C
- Authority
- CN
- China
- Prior art keywords
- signal pad
- signal
- dielectric material
- group
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
- Y10T29/4916—Simultaneous circuit manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (30)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/722,226 US7214886B2 (en) | 2003-11-25 | 2003-11-25 | High performance chip carrier substrate |
US10/722,226 | 2003-11-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1622315A CN1622315A (zh) | 2005-06-01 |
CN1314109C true CN1314109C (zh) | 2007-05-02 |
Family
ID=34591986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100868608A Active CN1314109C (zh) | 2003-11-25 | 2004-11-02 | 多层芯片载体及其基板和在芯片载体上展开信号焊盘的重新分配方法 |
Country Status (4)
Country | Link |
---|---|
US (4) | US7214886B2 (zh) |
JP (1) | JP4528098B2 (zh) |
KR (1) | KR100724505B1 (zh) |
CN (1) | CN1314109C (zh) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7214886B2 (en) * | 2003-11-25 | 2007-05-08 | International Business Machines Corporation | High performance chip carrier substrate |
US7191422B1 (en) * | 2004-05-26 | 2007-03-13 | Sun Microsystems, Inc. | System and method for determining a carrier layout using cornered chip-to-chip input/output |
US7414322B2 (en) * | 2005-07-29 | 2008-08-19 | Lsi Corporation | High speed interface design |
US7871831B1 (en) | 2006-03-01 | 2011-01-18 | Cadence Design Systems, Inc. | Method for connecting flip chip components |
DE102007003182B4 (de) * | 2007-01-22 | 2019-11-28 | Snaptrack Inc. | Elektrisches Bauelement |
US7757196B2 (en) * | 2007-04-04 | 2010-07-13 | Cisco Technology, Inc. | Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards |
US7979983B2 (en) * | 2007-04-04 | 2011-07-19 | Cisco Technology, Inc. | Connection an integrated circuit on a surface layer of a printed circuit board |
US7872350B2 (en) * | 2007-04-10 | 2011-01-18 | Qimonda Ag | Multi-chip module |
US8106496B2 (en) * | 2007-06-04 | 2012-01-31 | Stats Chippac, Inc. | Semiconductor packaging system with stacking and method of manufacturing thereof |
JP2011082450A (ja) | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム |
US20130105063A1 (en) * | 2011-11-02 | 2013-05-02 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | System and method for fabricating a laminate structure |
JP6098285B2 (ja) * | 2013-03-28 | 2017-03-22 | 富士通株式会社 | 配線基板及び電子装置 |
JP2015153808A (ja) * | 2014-02-12 | 2015-08-24 | ソニー株式会社 | 半導体チップ、および、半導体モジュール |
CN109509737B (zh) * | 2017-09-15 | 2020-09-08 | 瑞昱半导体股份有限公司 | 电子封装构件以及电路布局结构 |
US10021784B1 (en) * | 2017-12-19 | 2018-07-10 | Powertech Technology Inc. | Electronic device and electronic circuit board thereof |
CN112242375A (zh) * | 2020-10-19 | 2021-01-19 | Oppo广东移动通信有限公司 | 芯片和电子设备 |
TWI769063B (zh) * | 2021-03-25 | 2022-06-21 | 嘉雨思科技股份有限公司 | 訊號傳輸電路封裝結構 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5258648A (en) * | 1991-06-27 | 1993-11-02 | Motorola, Inc. | Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery |
CN1326592A (zh) * | 1998-11-20 | 2001-12-12 | 索尼计算机娱乐公司 | 集成电路芯片、集成电路元件、印刷电路板及电子设备 |
US6479758B1 (en) * | 2000-01-21 | 2002-11-12 | Kabushiki Kaisha Toshiba | Wiring board, semiconductor package and semiconductor device |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2783651B2 (ja) * | 1989-05-31 | 1998-08-06 | 富士通株式会社 | 半導体装置 |
JPH05144971A (ja) * | 1991-11-18 | 1993-06-11 | Nec Corp | チツプキヤリア構造 |
JPH0645401A (ja) * | 1992-07-23 | 1994-02-18 | Nec Corp | 半導体装置用パッケージ |
US5900675A (en) * | 1997-04-21 | 1999-05-04 | International Business Machines Corporation | Organic controlled collapse chip connector (C4) ball grid array (BGA) chip carrier with dual thermal expansion rates |
JP3732927B2 (ja) * | 1997-07-31 | 2006-01-11 | 京セラ株式会社 | 多層配線基板 |
CN1971899B (zh) * | 1997-10-17 | 2010-05-12 | 揖斐电株式会社 | 封装基板 |
JPH11289025A (ja) * | 1998-04-01 | 1999-10-19 | Ngk Spark Plug Co Ltd | ビルドアップ多層配線基板 |
US6548907B1 (en) * | 1998-04-28 | 2003-04-15 | Fujitsu Limited | Semiconductor device having a matrix array of contacts and a fabrication process thereof |
DE19831634B4 (de) * | 1998-07-15 | 2005-02-03 | Pac Tech - Packaging Technologies Gmbh | Chipträgeranordnung sowie Verfahren zur Herstellung einer Chipträgeranordnung mit elektrischem Test |
JP2000077819A (ja) * | 1998-08-31 | 2000-03-14 | Toshiba Corp | プリント基板および電子ユニット |
US6310398B1 (en) * | 1998-12-03 | 2001-10-30 | Walter M. Katz | Routable high-density interfaces for integrated circuit devices |
JP2000277652A (ja) * | 1999-03-23 | 2000-10-06 | Nagase & Co Ltd | 半導体パッケージ |
US6373717B1 (en) * | 1999-07-02 | 2002-04-16 | International Business Machines Corporation | Electronic package with high density interconnect layer |
US6351393B1 (en) * | 1999-07-02 | 2002-02-26 | International Business Machines Corporation | Electronic package for electronic components and method of making same |
US6538213B1 (en) * | 2000-02-18 | 2003-03-25 | International Business Machines Corporation | High density design for organic chip carriers |
JP2001339009A (ja) * | 2000-03-24 | 2001-12-07 | Ngk Spark Plug Co Ltd | 配線基板 |
JP3587451B2 (ja) * | 2000-03-31 | 2004-11-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 多層相互接続構造および電子パッケージ |
US6518516B2 (en) * | 2000-04-25 | 2003-02-11 | International Business Machines Corporation | Multilayered laminate |
JP2004507625A (ja) | 2000-08-22 | 2004-03-11 | エクソンモービル・ケミカル・パテンツ・インク | ポリプロピレン繊維及び布 |
US6417463B1 (en) * | 2000-10-02 | 2002-07-09 | Apple Computer, Inc. | Depopulation of a ball grid array to allow via placement |
JP2002246759A (ja) * | 2000-12-12 | 2002-08-30 | Ngk Spark Plug Co Ltd | 配線基板 |
JPWO2003021668A1 (ja) * | 2001-08-31 | 2004-12-24 | 日立化成工業株式会社 | 配線基板、半導体装置及びそれらの製造方法 |
US6528735B1 (en) * | 2001-09-07 | 2003-03-04 | International Business Machines Corporation | Substrate design of a chip using a generic substrate design |
US6762489B2 (en) * | 2001-11-20 | 2004-07-13 | International Business Machines Corporation | Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules |
JP2003229672A (ja) * | 2001-11-30 | 2003-08-15 | Ngk Spark Plug Co Ltd | 配線基板 |
US6800944B2 (en) * | 2001-12-19 | 2004-10-05 | Texas Instruments Incorporated | Power/ground ring substrate for integrated circuits |
JP3864836B2 (ja) * | 2002-04-19 | 2007-01-10 | 株式会社デンソー | 回路基板の配線構造 |
US6744067B1 (en) * | 2003-01-17 | 2004-06-01 | Micron Technology, Inc. | Wafer-level testing apparatus and method |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
JP4190957B2 (ja) * | 2003-06-20 | 2008-12-03 | 株式会社ルネサステクノロジ | 半導体装置 |
US7317165B2 (en) * | 2003-06-24 | 2008-01-08 | Ngk Spark Plug Co., Ltd. | Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure having semiconductor element, intermediate substrate and substrate |
US7214886B2 (en) * | 2003-11-25 | 2007-05-08 | International Business Machines Corporation | High performance chip carrier substrate |
-
2003
- 2003-11-25 US US10/722,226 patent/US7214886B2/en not_active Expired - Fee Related
-
2004
- 2004-10-28 KR KR1020040086531A patent/KR100724505B1/ko not_active IP Right Cessation
- 2004-11-02 CN CNB2004100868608A patent/CN1314109C/zh active Active
- 2004-11-19 JP JP2004335584A patent/JP4528098B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-09 US US11/651,631 patent/US7454833B2/en not_active Expired - Fee Related
-
2008
- 2008-06-30 US US12/164,478 patent/US7886435B2/en not_active Expired - Fee Related
- 2008-08-06 US US12/186,767 patent/US7863526B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5258648A (en) * | 1991-06-27 | 1993-11-02 | Motorola, Inc. | Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery |
CN1326592A (zh) * | 1998-11-20 | 2001-12-12 | 索尼计算机娱乐公司 | 集成电路芯片、集成电路元件、印刷电路板及电子设备 |
US6479758B1 (en) * | 2000-01-21 | 2002-11-12 | Kabushiki Kaisha Toshiba | Wiring board, semiconductor package and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2005159354A (ja) | 2005-06-16 |
KR20050050532A (ko) | 2005-05-31 |
US20050109535A1 (en) | 2005-05-26 |
JP4528098B2 (ja) | 2010-08-18 |
US7863526B2 (en) | 2011-01-04 |
KR100724505B1 (ko) | 2007-06-04 |
US7886435B2 (en) | 2011-02-15 |
US20070175658A1 (en) | 2007-08-02 |
CN1622315A (zh) | 2005-06-01 |
US7214886B2 (en) | 2007-05-08 |
US7454833B2 (en) | 2008-11-25 |
US20080308923A1 (en) | 2008-12-18 |
US20080296054A1 (en) | 2008-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1314109C (zh) | 多层芯片载体及其基板和在芯片载体上展开信号焊盘的重新分配方法 | |
US7129574B2 (en) | Multi-power ring chip scale package for system level integration | |
US6594811B2 (en) | Routable high-density interfaces for integrated circuit devices | |
CN100407877C (zh) | 用于减少多层电路板的层数的技术 | |
US6657130B2 (en) | Electrical and physical design integration method and apparatus for providing interconnections on first level ceramic chip carrier packages | |
CN1951161A (zh) | 区域阵列零件的共用通路退耦 | |
CN1146977C (zh) | 安装倒装片的结构和防止倒装片键合区起伏的图案 | |
CN1429407A (zh) | 组件中的嵌入式电容部件 | |
CN1577993A (zh) | 具有栅格阵列接口的折叠式柔性电路互连器 | |
CN101043033A (zh) | 半导体集成电路装置 | |
CN1732567A (zh) | 半导体装置电源互连条纹 | |
TW200531611A (en) | Method and apparatus for increasing routing density for a circuit board | |
CN1624912A (zh) | 器件封装件和印刷电路板及电子装置 | |
JPH1065044A (ja) | スタガ配列されたボンド・パッドを有する半導体ダイ | |
CN1614757A (zh) | 具有高可布线性的高密度微过孔基板 | |
US20090174072A1 (en) | Semiconductor system having bga package with radially ball-depopulated substrate zones and board with radial via zones | |
CN1510982A (zh) | 电子元件和多层信号路由装置之间的电信号电气互连技术 | |
CN1178295C (zh) | 倒装芯片及倒装芯片式封装基板 | |
US20050110167A1 (en) | Routing scheme for differential pairs in flip chip substrates | |
CN1185703C (zh) | 倒装芯片式封装基板 | |
US8013253B2 (en) | Electrical connection board and assembly of such a board and a semiconductor component comprising an integrated circuit chip | |
CN1194410C (zh) | 倒装芯片导电凸块与再分布导线层配置 | |
CN1568544A (zh) | 高密度倒装芯片的互连 | |
CN1689154A (zh) | 倒装芯片管芯键合焊盘、管芯键合焊盘布局及布线优化 | |
CN2569340Y (zh) | 覆晶芯片 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171108 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171108 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
TR01 | Transfer of patent right |