CN1303557C - 引入了晶体管的扩散长度依赖性的电路仿真装置以及用于生成晶体管模型的方法 - Google Patents
引入了晶体管的扩散长度依赖性的电路仿真装置以及用于生成晶体管模型的方法 Download PDFInfo
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- CN1303557C CN1303557C CNB031598285A CN03159828A CN1303557C CN 1303557 C CN1303557 C CN 1303557C CN B031598285 A CNB031598285 A CN B031598285A CN 03159828 A CN03159828 A CN 03159828A CN 1303557 C CN1303557 C CN 1303557C
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- diffusion
- length
- dependence
- diffusion length
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002279398A JP4408613B2 (ja) | 2002-09-25 | 2002-09-25 | トランジスタの拡散層長依存性を組み込んだ回路シミュレーション装置およびトランジスタモデル作成方法 |
JP279398/2002 | 2002-09-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1497481A CN1497481A (zh) | 2004-05-19 |
CN1303557C true CN1303557C (zh) | 2007-03-07 |
Family
ID=31987090
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031598285A Expired - Fee Related CN1303557C (zh) | 2002-09-25 | 2003-09-25 | 引入了晶体管的扩散长度依赖性的电路仿真装置以及用于生成晶体管模型的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7222060B2 (zh) |
JP (1) | JP4408613B2 (zh) |
KR (1) | KR100517766B1 (zh) |
CN (1) | CN1303557C (zh) |
DE (1) | DE10344570A1 (zh) |
TW (1) | TWI247223B (zh) |
Families Citing this family (31)
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CN101006204A (zh) * | 2004-06-22 | 2007-07-25 | Bhp比利顿创新公司 | 金属氧化物的电化学还原 |
KR100716912B1 (ko) * | 2004-06-30 | 2007-05-10 | 동부일렉트로닉스 주식회사 | 횡형 이중 확산 모스 트랜지스터의 시뮬레이션 방법 |
BRPI0513992A (pt) * | 2004-07-30 | 2008-05-20 | Bhp Billiton Innovation Pty | processo para minimização da re-oxidação de material reduzido e processo para redução eletroquìmica de um material de alimentação de óxido metálico |
JP2006178907A (ja) * | 2004-12-24 | 2006-07-06 | Matsushita Electric Ind Co Ltd | 回路シミュレーション方法および装置 |
JP4544631B2 (ja) | 2005-07-04 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | トランジスタモデル生成装置、および、トランジスタモデル生成方法 |
CN100416576C (zh) * | 2005-08-31 | 2008-09-03 | 上海华虹Nec电子有限公司 | 一种横向三极管仿真模型及其实现方法 |
US8407634B1 (en) * | 2005-12-01 | 2013-03-26 | Synopsys Inc. | Analysis of stress impact on transistor performance |
JP5020562B2 (ja) * | 2006-07-25 | 2012-09-05 | 株式会社 液晶先端技術開発センター | シミュレーション装置、シミュレーション方法、及び半導体装置の製造方法 |
US8346831B1 (en) * | 2006-07-25 | 2013-01-01 | Vivante Corporation | Systems and methods for computing mathematical functions |
TW200809748A (en) * | 2006-08-09 | 2008-02-16 | Ind Tech Res Inst | Method for simulating circuit reliability and system thereof |
KR100850092B1 (ko) * | 2006-08-31 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Cmos 소자의 spice 모델링 방법 |
KR100859475B1 (ko) * | 2006-12-29 | 2008-09-24 | 동부일렉트로닉스 주식회사 | 파라미터의 직접 추출법으로 가변 커패시터를 모델링하는방법 |
US7949985B2 (en) * | 2007-06-01 | 2011-05-24 | Synopsys, Inc. | Method for compensation of process-induced performance variation in a MOSFET integrated circuit |
JP2008311361A (ja) * | 2007-06-13 | 2008-12-25 | Nec Electronics Corp | 半導体集積回路、半導体集積回路のレイアウト設計方法、及び半導体集積回路の自動レイアウトプログラム |
JP4874207B2 (ja) * | 2007-10-01 | 2012-02-15 | ルネサスエレクトロニクス株式会社 | 回路シミュレーション方法、回路シミュレーション装置、及びプログラム |
CN101251864B (zh) * | 2008-03-25 | 2012-06-06 | 上海集成电路研发中心有限公司 | 锗硅hbt雪崩外延层有效厚度计算方法及雪崩电流计算方法 |
US20100088083A1 (en) * | 2008-10-08 | 2010-04-08 | Vns Portfolio Llc | Method and Apparatus for Circuit Simulation |
US8362622B2 (en) * | 2009-04-24 | 2013-01-29 | Synopsys, Inc. | Method and apparatus for placing transistors in proximity to through-silicon vias |
JP5560700B2 (ja) * | 2009-12-24 | 2014-07-30 | 富士通セミコンダクター株式会社 | 設計支援装置、設計支援方法及び設計支援プログラム |
US8785291B2 (en) | 2011-10-20 | 2014-07-22 | International Business Machines Corporation | Post-gate shallow trench isolation structure formation |
US8466496B2 (en) | 2011-11-17 | 2013-06-18 | International Business Machines Corporation | Selective partial gate stack for improved device isolation |
US9817928B2 (en) | 2012-08-31 | 2017-11-14 | Synopsys, Inc. | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits |
US9190346B2 (en) | 2012-08-31 | 2015-11-17 | Synopsys, Inc. | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits |
US8847324B2 (en) | 2012-12-17 | 2014-09-30 | Synopsys, Inc. | Increasing ION /IOFF ratio in FinFETs and nano-wires |
US9379018B2 (en) | 2012-12-17 | 2016-06-28 | Synopsys, Inc. | Increasing Ion/Ioff ratio in FinFETs and nano-wires |
KR101244702B1 (ko) * | 2012-12-27 | 2013-03-18 | 서울과학기술대학교 산학협력단 | 트랜지스터에서의 문턱 전압 이동 시뮬레이션 방법 |
CN103778297B (zh) * | 2014-01-27 | 2017-04-12 | 中国科学院微电子研究所 | Mos器件的sti应力效应建模方法及装置 |
KR101506902B1 (ko) * | 2014-02-03 | 2015-03-30 | 서울시립대학교 산학협력단 | 평판 트랜지스터의 일함수 분산 결정 장치 및 방법 |
KR101532579B1 (ko) * | 2014-02-10 | 2015-06-30 | 서울시립대학교 산학협력단 | 3차원 구조 트랜지스터의 일함수 분산 결정 장치 및 방법 |
KR101580828B1 (ko) * | 2014-11-11 | 2015-12-29 | 서울시립대학교 산학협력단 | 대칭형 터널 전계 효과 트랜지스터의 임의 변화 최소화를 위한 디자인 파라미터 결정 장치 및 결정 방법 |
JP2021140845A (ja) * | 2020-03-05 | 2021-09-16 | 株式会社東芝 | 磁気ディスク装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694579A (en) * | 1993-02-18 | 1997-12-02 | Digital Equipment Corporation | Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation |
US5751593A (en) * | 1996-04-10 | 1998-05-12 | Motorola, Inc. | Accurate delay prediction based on multi-model analysis |
US5761481A (en) * | 1995-05-04 | 1998-06-02 | Advanced Micro Devices, Inc. | Semiconductor simulator tool for experimental N-channel transistor modeling |
Family Cites Families (7)
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---|---|---|---|---|
US5648920A (en) * | 1994-11-22 | 1997-07-15 | Texas Instruments Incorporated | Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors |
US6314390B1 (en) * | 1998-11-30 | 2001-11-06 | International Business Machines Corporation | Method of determining model parameters for a MOSFET compact model using a stochastic search algorithm |
JP2000322456A (ja) | 1999-05-10 | 2000-11-24 | Hitachi Ltd | モデルパラメータ抽出方法及び装置 |
JP2001035930A (ja) | 1999-07-19 | 2001-02-09 | Mitsubishi Electric Corp | 特性抽出装置、特性評価装置、および、半導体装置 |
US6618837B1 (en) * | 2000-09-14 | 2003-09-09 | Cadence Design Systems, Inc. | MOSFET modeling for IC design accurate for high frequencies |
US6441396B1 (en) * | 2000-10-24 | 2002-08-27 | International Business Machines Corporation | In-line electrical monitor for measuring mechanical stress at the device level on a semiconductor wafer |
JP3653485B2 (ja) * | 2001-08-31 | 2005-05-25 | 株式会社半導体理工学研究センター | ポケット注入mosfetのしきい値電圧の計算方法 |
-
2002
- 2002-09-25 JP JP2002279398A patent/JP4408613B2/ja not_active Expired - Fee Related
-
2003
- 2003-09-22 KR KR10-2003-0065689A patent/KR100517766B1/ko not_active IP Right Cessation
- 2003-09-24 US US10/668,974 patent/US7222060B2/en not_active Expired - Fee Related
- 2003-09-24 TW TW092126348A patent/TWI247223B/zh not_active IP Right Cessation
- 2003-09-25 DE DE10344570A patent/DE10344570A1/de not_active Withdrawn
- 2003-09-25 CN CNB031598285A patent/CN1303557C/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694579A (en) * | 1993-02-18 | 1997-12-02 | Digital Equipment Corporation | Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation |
US5761481A (en) * | 1995-05-04 | 1998-06-02 | Advanced Micro Devices, Inc. | Semiconductor simulator tool for experimental N-channel transistor modeling |
US5751593A (en) * | 1996-04-10 | 1998-05-12 | Motorola, Inc. | Accurate delay prediction based on multi-model analysis |
Also Published As
Publication number | Publication date |
---|---|
US20040059559A1 (en) | 2004-03-25 |
TW200411448A (en) | 2004-07-01 |
TWI247223B (en) | 2006-01-11 |
US7222060B2 (en) | 2007-05-22 |
KR20040027359A (ko) | 2004-04-01 |
DE10344570A1 (de) | 2004-05-13 |
KR100517766B1 (ko) | 2005-09-28 |
CN1497481A (zh) | 2004-05-19 |
JP4408613B2 (ja) | 2010-02-03 |
JP2004119608A (ja) | 2004-04-15 |
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