CN1302405A - Memory control unit - Google Patents
Memory control unit Download PDFInfo
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- CN1302405A CN1302405A CN00800757A CN00800757A CN1302405A CN 1302405 A CN1302405 A CN 1302405A CN 00800757 A CN00800757 A CN 00800757A CN 00800757 A CN00800757 A CN 00800757A CN 1302405 A CN1302405 A CN 1302405A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
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Abstract
To provide a memory control unit which prevents continuous accesses to the same bank of SDRAM to increase its processing speed. The memory control unit (3) of the present invention controls SDRAM (2) which has two banks 0, 1 and can be continuously accessed in multiple-bank mode in which address inputs to the banks 0, 1 are seamlessly alternated between the banks by precharging the banks individually. The memory addresses provided by a block (4, 5) accessing the SDRAM (2) through the memory control unit (3) are converted into addresses such that the memory addresses are input to the banks of the SDRAM (2) alternately.
Description
Invention field
The present invention relates to control the memory control unit of Synchronous Dynamic Random Access Memory (below be abbreviated as SDRAM).
Background of invention
In recent years, SDRAM comes into operation, its allow cache memory commonly used in personal computer with clock speed synchronous carry out burst pulse string pattern data transfer at a high speed.SDRAM allows to switch between multiple memory cell consecutive access pattern and random access mode.In the multiple memory cell pattern, adopt two storage unit, storage unit 0 and storage unit 1.The highest significant position of the storage address of storage unit 0 (MSB) is " 0 ", and the MSB of the storage address of storage unit 1 is " 1 ".By the control clock to the access that hockets of storage unit 0 and storage unit 1, thereby in the storage address that obtains another storage unit, can read the data in the storage unit.
The memory control unit of control SDRAM, for example these memory control units of describing in open communique 8-111090 of Jap.P. and the open communique 8-212170 of Jap.P. are known.
The memory control unit 11 of the control SDRAM that describes among the open communique 8-212170 of Jap.P. comprises storage control device 12 and arbitration/waiting signal generation device 13, and as shown in Figure 8, control is to a plurality of 14 to 17 the access of SDRAM2.
The memory controller that memory address signal (MADD), data-signal (DATA) and read (RD/WR) are input to respectively corresponding to each piece 14 to 17 divides among the 18a-18d.
Memory access requests signal (CS) from each piece 14 to 17 is input to arbitration/waiting signal generation device 13, waiting signal (Wait) is returned to each piece 14 to 17 from it.
Divide control from being activated the access of piece corresponding to memory controller to SDRAM2 from the piece of arbitration/waiting signal generation device 13 reception memorizer access enable signals (Enable).
The example of reading the access timing of the SDRAM2 that utilizes memory control unit 11 below will be described.In this example, suppose that SDRAM2 adopts the multiple memory cell pattern.
When the MSB of the storage address that provides by piece select storage unit 0 during for " 0 ", and when MSB is " 1 " select storage unit 1.
As shown in Figure 9, according to clock CK alternately the row address R0/ column address C0 of storage unit 0 to the row address R1/ column address C1 of storage unit 1 to reading among the SDRAM.Regularly locate to export the data D00 and the D01 of storage unit 0 at the clock of row address R1 that imports storage unit 1 and column address C1.D01 is that the data after the D00 address are followed in its address.This means by an address input and can export two digital data.When only needing word of data, do not need data D01.
At the output final data, promptly automatically carry out the precharge of each storage unit on the time point of the data D01 of two digital data.Equally also be applied to the precharge of storage unit 1.
In this way, alternately and seamlessly storage unit 0 and the storage unit 1 of access SDRAM.
Memory control unit for traditional prior art, adopt in multiple memory cell pattern and the single situation of making at SDRAM the SDRAM access, if from the single storage address of exporting continuously same memory cell (for example setting storage unit is 0) consecutive access, just storage unit 0 is done access continuously.In this case, the precharge operation on storage unit 0 finishes, and just has the address can output to storage unit 0.That is, with exist can not access SDRAM null cycle.
A kind of way that addresses this problem is, if single memory cell access SDRAM, thus alternately access memory cell 0 and storage unit 1 then are created in the storage address in single.Yet if a plurality of block access SDRAM, it is very difficult making a plurality of storage addresss that provide relevant.So the same storage unit of access continuously is because uncorrelated each other from the storage address of each piece.
For example, when piece A access block 0 back piece B attempts access block 0 immediately, same (piece 0) made consecutive access.Precharge operation on storage unit 0 finishes, and could offer storage unit 0 to the address.This means the null cycle that existence can not access SDRAM.
The purpose of this invention is to provide a kind of same storage unit of consecutive access SDRAM that stops to increase the memory control unit of its processing speed.
Summary of the invention
Memory control unit of the present invention is so to arrange, and the memory address translation that each piece is provided becomes such address, promptly alternately changes the address input between the storage unit of SDRAM.
According to the present invention, a kind of memory control unit is provided, it stops the same storage unit of consecutive access SDRAM, to increase its processing speed.
The invention provides the memory control unit of a kind of SDRAM of control, SDRAM has a plurality of storage unit and permission is carried out consecutive access with the multiple memory cell pattern, in the multiple memory cell pattern by to storage unit precharge and seamlessly alternately change to the address input of described storage unit respectively, here, arrange memory control unit, thereby the memory address translation by the piece by memory control unit access SDRAM is become such address, promptly make these addresses alternately be input to the storage unit of SDRAM.Storage address from each piece is changed, thereby can between them, alternately be input to storage unit, even each piece provides the storage address that not so can cause the same storage unit consecutive access of SDRAM, therefore, access memory cell alternately always.Therefore, eliminated can not access SDRAM unused period, and can be to the continuous issue an order of SDRAM, to increase its processing speed.From the angle of the piece that produces storage address, they can produce storage address and not have the storage unit of noting.
The present invention further provides a kind of memory control unit that is used to control SDRAM, SDRAM is divided at least two storage unit, it allows to switch between multiple memory cell consecutive access pattern and multiple memory cell random access mode, by storage unit is distinguished precharge, the feasible address input to storage unit of multiple memory cell consecutive access pattern can seamlessly replace change, it is characterized in that memory control unit comprises: arbitration is from the moderator of the memory access requests of the piece of a plurality of memory control unit access SDRAM of passing through; The order that generation is distributed to the memory command of SDRAM produces piece; Address conversion block, being used for the memory address translation of coming free moderator to provide the piece of access right is the row and column address, makes these addresses alternately be input to the storage unit of SDRAM; And the data latches piece, be used for temporarily latching by moderator provide access right piece provided writes data or from the SDRAM sense data, so that transmit data between piece and SDRAM.Even uncorrelated each other by a plurality of storage addresss that provide, to the discontinuous access of same storage unit of SDRAM, be easy to guarantee storage access, and can give the storer issue an order continuously with the multiple memory cell pattern, cause processing speed to improve.
Thereby the present invention further provides and a kind ofly in each storage unit, match the storage unit of access SDRAM alternately by the memory access unit that each piece is provided and control the memory control unit of SDRAM.The same single storage unit of discontinuous access SDRAM and a plurality of storage unit of access alternately.
The present invention further provides a kind of memory control unit; wherein; if it is unpaired in storage unit separately by the memory access unit that piece provided that provides access right; then will order to produce piece and be arranged to and produce the shielded signal of forbidding access data, described access data is corresponding to superfluous or not enough from the storage access of piece in SDRAM.This has exempted needs a plurality of signals of control or stipulates the burst pulse string length again, and this is essential in traditional prior art.Utilize shielded signal control store access simply, and need not to change the memory access unit of storage unit, cause the simplification of memorizer control circuit.
The accompanying drawing summary
Fig. 1 is a block scheme, shows the structure according to the memory control unit of the embodiment of the invention 1.
Fig. 2 is the figure that describes according to the address translation in the address conversion block of the embodiment of the invention 1.
Fig. 3 is a sequential chart, shows according to the timing of the embodiment of the invention 1 to each memory cell access.
Fig. 4 is the figure that describes the address translation example that is different from embodiment 1.
Fig. 5 is the figure that describes the address translation example that is different from embodiment 1.
Fig. 6 is a sequential chart, shows the memory access unit according to each piece of the embodiment of the invention 2.
Fig. 7 is a sequential chart, shows the different memory access unit according to the embodiment of the invention 3.
Fig. 8 is a block scheme, shows the structure according to the memory control unit of traditional prior art.
Fig. 9 is a sequential chart, shows according to the timing of traditional prior art to each memory cell access.
Below will memory control unit of the present invention be described at specific embodiment.
Embodiment
(embodiment 1)
The memory control unit control according to embodiment 1 shown in Fig. 1 has two storage unit 0,1 SDRAM2 also allows with the access of multiple memory cell mode continuous, in the multiple memory cell pattern, import, with the same in traditional prior art by respectively storage unit precharge seamlessly alternately being changed the address between storage unit 0 and 1.Different with traditional prior art, the memory control unit of embodiment 1 is arranged to the piece 4 that passes through memory control unit 3 access SDRAM2 as shown in Figure 1,5 memory address translation that provide are in the address, thereby an address that is converted alternately is input to storage unit 0 and storage unit 1.
As shown in Figure 1, memory control unit 3 comprises from the moderator 6 of a plurality of 4, the 5 arbitration memory access requests of access SDRAM2; Produce to the order generation piece 7 of the memory command of SDRAM2; Address conversion block 8 is used for storage address is transformed into the row and column address from the piece that is provided access right by moderator 6, so that alternately the address is input to the storage unit of SDRAM2; Data latches piece 9 latchs and comes free moderator 6 to provide the writing data or latch sense data from SDRAM2 of piece of access right, to transmit data between this piece and SDRAM2.
Below will describe with the multiple memory cell pattern data will be written to the operation of the memory control unit 3 the SDRAM2 from piece 4.
Here, suppose SDRAM2 to be programmed with respect to " 2 " burst pulse string length, that is, when specified address, two words of access data, one is the address of defined, one is one address, back.
When piece 4 access SDRAM2, address, data and control signal are offered SDRAM2 by memory control unit 3.
If do not have other piece just at access SDRAM2, then moderator 6 returns to piece 4 to enable signal, and perhaps if block 5 is also exported request signal simultaneously with piece 4 and then enable signal returned to the piece with higher priority.In this example, suppose that piece 4 has limit priority and can pass through the access that moderator 6 starts SDRAM2.
Moderator 6 commander's address conversion block 8 are obtained from the storage address of startup piece 4 outputs, and command data latch piece 9 obtains from the data that will write of piece 4 outputs.Simultaneously, moderator 6 order commands produce piece 7 and produce memory command, comprise row address strobe (RAS) and column address strobe (CAS).
To be described in the address translation of carrying out in the address conversion block 8 below.
Address conversion block 8 becomes such address to the memory address translation that receives from piece 4, makes address, conversion back alternately be input to storage unit 0 and the storage unit 1 of SDRAM2.
Owing to respect to " 2 " burst pulse string length SDRAM2 is programmed, it is increased 2 when piece 4 is exported when storage address, shown in Fig. 2 (a).The MSB of storage address represents memory unit address.If MSB is " 0 ", select storage unit 0 so, and if it is " 1 ", so then select storage unit 1.Therefore, select the storage unit 0 of SDRAM2 continuously, because the MSB of all storage addresss is " 0 " before the conversion shown in Fig. 2 (a), unless they are changed.
Therefore, as second the MSB before conversion shown in Fig. 2 (a) as conversion background storage address from each storage address least significant bit (LSB) (LSB), position before the conversion more than the 3rd is moved one to LSB, produces the conversion background storage address shown in Fig. 2 (b).
Shown in Fig. 2 (b), the MSB of the storage address of generation is alternate between 0 and 1.Therefore, storage unit 0 and storage unit 1 are always by alternately access, and each piece can produce storage address and not have the storage unit of noting.
In this way, address conversion block 8 execute store address translation, and, they are outputed to SDRAM2 based on generation row and column address, the conversion background storage address shown in Fig. 2 (b).
Data latches piece 9 outputs to SDRAM2 to the data that write that each has latched, and order produces piece 7 above-mentioned memory command is outputed to SDRAM2.
Now, will be described below to the access timing of each storage unit of SDRAM2.
Alternately obtain the row address R00 of storage unit 0 and the row address R10 and the column address C10 of column address C00 and storage unit 1 according to clock CK as shown in Figure 3.Data D00, D01 in the clock sequential place of row address R10 that imports storage unit 1 and column address C10 output storage unit 0.D01 is the data of following the address after D00.This means, by the input of address can output data two words.At output final data, the i.e. D01 of two digital data, D11, D03 ... the precharge of each storage unit is automatically carried out in timing place of data.
Because this configuration, can change storage address from each piece, thereby alternately be input to storage unit,, so prevent the storage unit that consecutive access is identical even can cause the storage address of consecutive access SDRAM2 same memory cell from each piece output.That is, access memory cell has alternately always been eliminated null cycle that can not access SDRAM2 and can have been given the SDRAM2 issue an order continuously, increases its processing speed.From the angle of the piece that produces storage address, can produce storage address and need not to pay close attention to storage unit.
In the description of embodiment 1, the SDRAM2 at the burst pulse string length programming of " 2 " has been described by way of example.If the burst pulse string length at for example " 4 " is programmed to SDRAM2, make so before the conversion shown in Fig. 4 (a) from the 3rd MSB that becomes the conversion background storage address shown in Fig. 4 (b) of the LSB of storage address.Before the conversion from the position more than the 4th of the LSB of storage address to one of the low displacement that will produce the background storage of conversion shown in Fig. 4 (b) address.
If the burst pulse string length at " 1 " is programmed to SDRAM2, make the LSB of storage address before the conversion shown in Fig. 5 (a) become the MSB of the conversion background storage address shown in Fig. 5 (b) so, shown in Fig. 5 (a) before the conversion from the position more than second of the LSB of storage address to one of low displacement, therefore produce the conversion background storage address shown in Fig. 5 (b).
(embodiment 2)
Similar according to the memory control unit of the embodiment of the invention 2 to embodiment described above 1, different is has increased a feature to the memory control unit 3 of embodiment 1, make different storage unit pairings, as unit by each piece 4,5 access so that storage unit 0 and 1 each other alternately by access with control SDRAM2.
Thereby memory control unit 3 by storage unit 0 and storage unit 1 are paired into by the memory access unit of each block access alternately access memory cell control SDRAM2.For example, if SDRAM2 is programmed at the burst pulse string length of " 2 " with the multiple memory cell pattern, the access unit of each piece 4,5 is four words so, so that each piece uses two words of two words of storage unit 0 and storage unit 1 as a pair of.
Therefore, with multiple memory cell pattern access SDRAM2, the data of piece 4,5 are written in the situation of SDRAM2, will describe the operation of memory control unit 3 a plurality of (for example piece 4,5).Suppose that SDRAM2 is " 2 " burst pulse string length pattern.
Because output on the SDRAM2 this point in the data that order produced piece 7, address conversion block 8 and data latches piece 9, process is identical with the situation of embodiment 1 described above, the descriptions thereof are omitted here.
Even piece 5 immediate access SDRAM2 after piece 4 access SDRAM2, as shown in Figure 6, always between storage unit 0 and storage unit 1, hocket in access when piece 4 switches to piece 5 because each piece by two digital data pairings of two digital data of storage unit 0 and storage unit 1 as a unit and four words of access.
Therefore, because this structure, even a plurality of 4,5 access SDRAM2 and uncorrelated each other from a plurality of 4,5 storage address also can stop the consecutive access to the SDRAM2 same memory cell.That is, storage unit is always by alternately access, can eliminate the generation of null cycle that can not access SDRAM2, and can give the SDRAM2 issue an order continuously, causes processing speed to increase.
(embodiment 3)
Here,, continuously the data of piece 4,5 are written in the situation of SDRAM2 in piece 4 only storage unit 0 and piece 5 access memory cells 0 and the storage unit 1 of the SDRAM2 of access multiple memory cell pattern, the operation of memory control unit 3, as shown in Figure 7.Suppose that SDRAM2 is with burst pulse string length " 2 " pattern.
Shown in Fig. 7 (b), not plumber block 4 be the access random address or with two words as cell access data, memory control unit 3 is always issued corresponding to the memory command of storage unit 1 (writing WRITE) and address (R10, C10).
When carrying out write operation in this example, order produces piece 7 and produces shielded signals, and it forbids writing data (D10, D11) in SDRAM2, and this is the short access data from piece 4.
The data (D10, D11) that write shown in Fig. 7 (b) can be any other values.
At shielded signal is that SDRAM2 does not write data (D10, D11) in the high interval.
With traditional prior art, must control store order (comprising RAS and CAS) thereby and the address do not issue, promptly must control store order (WRITE) and address (R10, C10) do not issue, shown in Fig. 7 (a).Since memory command provide many signals to SDRAM2 (/CS ,/RAS ,/CAS ,/WE and address) combination, and must control all these signals or must stipulate the burst pulse string length of SDRAM2 again, so in traditional prior art, it is quite complicated that circuit becomes.On the contrary, having eliminated needs according to the memory control unit 3 of embodiment 3 controls a plurality of signals or stipulates the burst pulse string length again.Can make control obtain simplifying, because it is realized by utilizing shielded signal to need not to change memory access unit simply.So, can make circuit reduction.
Though in the description of above embodiment, described the operation that is written to SDRAM2 from the data of piece, the situation that the data of reading from SDRAM2 is input to piece, can obtain similar effect.
Claims (4)
1. memory control unit that is used to control SDRAM (2), described SDRAM (2) has a plurality of storage unit and permission is carried out consecutive access with the multiple memory cell pattern, in the multiple memory cell pattern by to the precharge and seamlessly alternately change to the address input of described storage unit respectively of described storage unit, it is characterized in that
The storage address that is provided by the piece (4,5) by the described SDRAM of described memory control unit (3) access (2) is changed, made these addresses alternately be input in each storage unit of SDRAM (2).
2. memory control unit (3) that is used to control SDRAM (2), the inside of described SDRAM (2) is divided at least two storage unit and allows between multiple memory cell consecutive access pattern and multiple memory cell random access mode, switch, by respectively to described storage unit precharge, described multiple memory cell consecutive access pattern starts the address input to described storage unit, make it seamlessly alternately to change, it is characterized in that it comprises:
Moderator (6) is used for the memory access requests of passing through described memory control unit (3) access described SDRAM (2) of arbitration from a plurality of (4,5);
Order produces piece (7), is used for producing the memory command to described SDRAM (2);
Address conversion block (8), be used for a memory address translation of coming free described moderator (6) to provide the piece (4,5) of access right is embarked on journey and column address, make these addresses alternately be input to the storage unit of described SDRAM (2) and export from described SDRAM (2); And
Data latches piece (9), be used for temporarily latching by described moderator (6) provide that the piece (4,5) of access right provided write data or from the sense data of described SDRAM (2), so that between piece (4,5) and described SDRAM (2), transmit data.
3. memory control unit as claimed in claim 2 is characterized in that: by making each piece (4,5) thus the memory access unit that provides in each storage unit, match alternately access memory cell and control described SDRAM (2).
4. memory control unit as claimed in claim 2; it is characterized in that: if the memory access unit that is provided by the piece that provides access right (4,5) is unpaired in storage unit separately; then will order to produce piece (7) and be arranged to and produce the shielded signal of forbidding access data, described access data is corresponding to superfluous or not enough from the storage access of piece (4,5) in described SDRAM (2).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP123294/1999 | 1999-04-30 | ||
| JP11123294A JP2000315173A (en) | 1999-04-30 | 1999-04-30 | Memory control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1302405A true CN1302405A (en) | 2001-07-04 |
Family
ID=14856994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN00800757A Pending CN1302405A (en) | 1999-04-30 | 2000-04-21 | Memory control unit |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP2000315173A (en) |
| KR (1) | KR20010053272A (en) |
| CN (1) | CN1302405A (en) |
| ID (1) | ID27447A (en) |
| WO (1) | WO2000067129A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300707C (en) * | 2002-07-23 | 2007-02-14 | 华为技术有限公司 | External memory storage SDRAM read-write processing method |
| CN100353348C (en) * | 2004-01-07 | 2007-12-05 | 松下电器产业株式会社 | DRAM controller and DRAM control method |
| CN100432958C (en) * | 2003-01-27 | 2008-11-12 | 松下电器产业株式会社 | Memory controller |
| US7570873B2 (en) | 2004-10-22 | 2009-08-04 | Via Technologies, Inc. | Subtitle file loading method and system thereof |
| CN101840375A (en) * | 2009-03-11 | 2010-09-22 | 株式会社东芝 | Semiconductor storage |
| CN101903868B (en) * | 2007-12-21 | 2012-07-04 | 松下电器产业株式会社 | Memory device and memory device control method |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002342164A (en) * | 2001-05-22 | 2002-11-29 | Hitachi Ltd | Storage device, data processor, and method for controlling storing part |
| AU2002326118A1 (en) | 2001-08-14 | 2003-03-03 | Quigo Technologies, Inc. | System and method for extracting content for submission to a search engine |
| AU2003256468A1 (en) * | 2002-07-09 | 2004-01-23 | Globespanvirata Incorporated | Method and system for improving access latency of multiple bank devices |
| JP4499982B2 (en) * | 2002-09-11 | 2010-07-14 | 株式会社日立製作所 | Memory system |
| KR100539964B1 (en) * | 2003-06-27 | 2005-12-28 | 주식회사 하이닉스반도체 | Apparatus and method for precharging of semiconductor memory device |
| EP1513157A1 (en) * | 2003-09-02 | 2005-03-09 | Deutsche Thomson-Brandt GmbH | Method for multibank memory scheduling |
| EP1513072A3 (en) * | 2003-09-02 | 2009-10-21 | Thomson Licensing | Method for multibank memory scheduling |
| KR100666929B1 (en) | 2004-10-30 | 2007-01-11 | 주식회사 하이닉스반도체 | Memory bank structure |
| JP4690424B2 (en) * | 2005-12-26 | 2011-06-01 | パナソニック株式会社 | Command processing apparatus, method, and integrated circuit device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0261751A3 (en) * | 1986-09-25 | 1990-07-18 | Tektronix, Inc. | Concurrent memory access system |
| JPH03248243A (en) * | 1990-02-26 | 1991-11-06 | Nec Corp | Information processor |
| US5226134A (en) * | 1990-10-01 | 1993-07-06 | International Business Machines Corp. | Data processing system including a memory controller for direct or interleave memory accessing |
| WO1994008295A1 (en) * | 1992-10-01 | 1994-04-14 | Flavors Technology Inc. | Method and apparatus for memory interleave reduction |
-
1999
- 1999-04-30 JP JP11123294A patent/JP2000315173A/en active Pending
-
2000
- 2000-04-21 ID IDW20002698A patent/ID27447A/en unknown
- 2000-04-21 KR KR1020007014977A patent/KR20010053272A/en not_active Application Discontinuation
- 2000-04-21 WO PCT/JP2000/002654 patent/WO2000067129A1/en not_active Application Discontinuation
- 2000-04-21 CN CN00800757A patent/CN1302405A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300707C (en) * | 2002-07-23 | 2007-02-14 | 华为技术有限公司 | External memory storage SDRAM read-write processing method |
| CN100432958C (en) * | 2003-01-27 | 2008-11-12 | 松下电器产业株式会社 | Memory controller |
| CN100353348C (en) * | 2004-01-07 | 2007-12-05 | 松下电器产业株式会社 | DRAM controller and DRAM control method |
| US7562184B2 (en) | 2004-01-07 | 2009-07-14 | Panasonic Corporation | DRAM controller for graphics processing operable to enable/disable burst transfer |
| US7570873B2 (en) | 2004-10-22 | 2009-08-04 | Via Technologies, Inc. | Subtitle file loading method and system thereof |
| CN101903868B (en) * | 2007-12-21 | 2012-07-04 | 松下电器产业株式会社 | Memory device and memory device control method |
| CN101840375A (en) * | 2009-03-11 | 2010-09-22 | 株式会社东芝 | Semiconductor storage |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000315173A (en) | 2000-11-14 |
| WO2000067129A1 (en) | 2000-11-09 |
| ID27447A (en) | 2001-04-12 |
| KR20010053272A (en) | 2001-06-25 |
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