CN1291466C - Semiconductor package with radiator - Google Patents
Semiconductor package with radiator Download PDFInfo
- Publication number
- CN1291466C CN1291466C CN 01139258 CN01139258A CN1291466C CN 1291466 C CN1291466 C CN 1291466C CN 01139258 CN01139258 CN 01139258 CN 01139258 A CN01139258 A CN 01139258A CN 1291466 C CN1291466 C CN 1291466C
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- CN
- China
- Prior art keywords
- fin
- chip
- packing described
- substrate
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention relates to a semiconductor package mode which comprises a chip, a base board, a plastic package body, a metal wire communicating a chip circuit and the base board, and a tin ball connected with an external circuit, wherein a heat sink is additionally arranged above the chip; the lower end of the heat sink is stuck on the base board and is fixed in the plastic package body. The heat sink rapidly dissipates heat generated by the chip to prevent the temperature of the chip from being over-high. The heat sink is made of heat conduction materials, and has the structures of a lug boss, a side wall opening, a bottom gap, a circular groove on the top end, etc. The present invention has the functions of promoting injection molding, fixing positions, preventing from overflowing glue, etc.
Description
(1) technical field:
The present invention relates to a kind of method for packaging semiconductor, particularly a kind of method for packaging semiconductor that improves the chip cooling performance.
(2) background technology:
Below, with reference to accompanying drawing conventional semiconductor packages is described.
Fig. 1 shows existing conventional ball grid array (BGA) semiconductor packaged type cross-section structure, and Fig. 2 shows existing conventional ball grid array (BGA) semiconductor packaged type planar structure, and this encapsulation comprises:
By silver slurry or other binding agent 2 chip 1 is bonded to substrate 3 tops, is connected with substrate circuit by the interior circuit of gold thread 4 with chip.Base circuit is made up of two layers of wiring up and down, between the wiring by having the via hole connection that metal crosses layer.Upper strata wiring is connected with gold thread, and lower circuit has outside pad is exposed to.Chip and gold thread are sealed with plastic packaging material 5.Weld tin ball 6 below the substrate on the pad as input and output side, substrate circuit, chip circuit and external circuit are coupled together.
In the encapsulation field of integrated circuit, along with the dense degree of integrated circuit in continuous increase, package dimension is constantly diminishing simultaneously, the heat that causes chip to produce is just more and more concentrated.Heat dissipation problem in the encapsulation is just crucial all the more.Existing packing forms is because the conductive coefficient of plastic packaging material is not high, and the heat that chip produces can not in time distribute, and has caused chip temperature too high easily, has reduced the power that chip can be supported.Though and some packing forms can improve heat dispersion, cost is very high.
(3) summary of the invention:
The object of the present invention is to provide a kind of semiconductor packages mode that installs heat abstractor additional, realize the low-cost heat dispersion that promotes product.
Another object of the present invention is to and the particular design by structure, can prevent that plastic packaging material from overflowing in the plastic packaging process influences the chip cooling performance to the top of exposing of fin.
In order to achieve the above object, encapsulating structure of the present invention is:
With bonding agent with die bonding to substrate, be communicated with chip circuit and substrate circuit by gold thread.Bonding one heat abstractor---fin on substrate.And then plastic packagings such as chip, gold thread, fin are got up with plastic packaging glue.The working portion of fin is arranged in the chip top, and height is identical with the plastic-sealed body height, and its upper surface is exposed in the air.Fin can be dispersed the heat that chip produces fast, and entire chip is cooled off rapidly, prevents that chip temperature is too high.Be welded with the tin ball under the substrate, substrate circuit is communicated with external circuit.Some downward projections have been adopted in the coupling part of fin and substrate, make between the bottom of fin and the substrate and form certain clearance, in injection moulding process, air can be discharged by the gap, and plastic packaging material also can be full of cavity below the fin by this gap.Make some breach in the lower edge of fin, when the pressure that is subjected to from the mould upper surface, indentation, there produces micro-strain, thereby reduces the stress that sidewall is subjected in injection moulding process.Some openings are arranged on the sidewall of fin, and plastic packaging material can be smoothly pours into cavity below the fin by these openings in the injection moulding process, air also thus opening discharge smoothly, prevent the generation of cavity and air pocket.Adopt the structure of a cannelure in the tip edges of fin, in the plastic packaging process,, hold the plastic packaging glue that covers bossing with a bigger cavity volume then by the slow down flow velocity of plastic packaging material of a projection, and plastic packaging glue is at high temperature solidified fast, thereby prevent the generation of excessive glue situation.
(4) description of drawings:
Understanding now is described with reference to the accompanying drawings as the back with understanding for purpose, feature and the effect that makes the present invention can have further:
Fig. 1 is the ball grid array (BGA) semiconductor encapsulation sectional structure chart of known technology;
Fig. 2 is the ball grid array (BGA) semiconductor encapsulation outside drawing of known technology;
Fig. 3 is the ball grid array (BGA) semiconductor encapsulation sectional structure chart of finned;
Fig. 4 is the ball grid array (BGA) semiconductor encapsulation outside drawing of finned;
Fig. 5 is the structure chart of a kind of specific form of fin;
Fig. 6 is that the A-A of fin shown in Figure 5 is to sectional structure chart;
Indentation, there produced the schematic diagram that distortion reduces stress when Fig. 7 was the fin pressurized;
Fig. 8 sentences the cross-section structure and the action principle figure of specific groove shape for the fin tip edge.
The present invention imbeds fin 7 (Fig. 3) in plastic-sealed body 5 on traditional ball grid array (BGA) semiconductor packing forms basis, the bottom of fin has some protruding 8,3 corresponding positions will apply binding agent 9 on substrate, and these several projectioies 8 are exactly the place that fin 7 is connected with substrate 3.These several boss have also guaranteed to leave certain clearance 11 between the lower edge 10 of fin and the substrate, allow plastic packaging material 5 can flow into and be full of the cavity 12 of fin inside smoothly in the process of injection moulding.Behind the plastic packaging, the top 13 of fin will be exposed to (Fig. 4) in the air, and will be identical with the height on plastic-sealed body top 14.Because fin is made by the material (copper, aluminium etc.) of good heat conductivity, has adopted such structure, the heat that chip produces just can diffuse in the air apace by fin.There are some through holes 15 (Fig. 5) on boss 8 next doors of fin, and in the process of injection moulding, plastic packaging material flows through through hole, and the adhesion between lamellar body and the plastic-sealed body of can strengthening dispelling the heat makes the fin location more firm.Some breach 16 are arranged at the bottom 10 of fin.It mainly acts on is exactly that fin can be subjected to the pressure from the die cavity upper surface in the plastic packaging process.These breach have been arranged, just can absorb a part of stress during the fin pressurized, avoided causing fin conquassation (Fig. 7) because of mold pressing is excessive in these local distortion that produces jaggy.Some openings 17 are arranged on the sidewall of fin, these openings have guaranteed that plastic packaging material can pass through, and being full of cavity 12 between entire heat dissipation sheet and the substrate smoothly, the air in the cavity also can be discharged by these aperture positions simultaneously, avoid the generation of hole and pore.In fin tip edges 21, the groove 18 of a circle annular is arranged, can also can there be other form in its cross section shown in (Fig. 8).
For as (Fig. 8) cross section structure, have a little projection 19 on the next door of groove, the distance 20 between the extreme higher position of projection and fin is very little.If do not adopt special structure, in common injection moulding process, because plastic packaging material has certain speed and pressure when flowing to the fin top, the glue that overflows can take place, colloid overflows to the airborne part of being exposed to of fin, influence the fin outward appearance, also can influence the performance of its heat dispersion simultaneously.Adopt fin top structure as shown in the figure, when plastic packaging material reaches fin top position, because projection is very little with the spacing 20 of mould upper surface, can only allow a spot of colloid to pass through, the speed that colloid flows will slow down.After colloid passes through, a cavity volume 18 that volume is relatively large will be run into, the effect of a similar cistern can be played.And colloid is close to the mould upper surface of high temperature, and this a small amount of colloid is subjected to the influence of high temperature, will be solidified rapidly, and mobile the reduction farthest suppressed the generation of excessive glue phenomenon.Can also when being bonded in fin on the substrate, use the bonding agent of conduction, with the earth polar conducting of fin and substrate.Like this, inner circuit just is surrounded by fin and ground pole plate, can play the effect of electrostatic screen, prevents the interference of the outside signal of telecommunication, promotes the electrical property of chip and circuit.
Semiconductor packages according to the present invention as mentioned above has following effect, promptly by in the packing forms of ball grid array, installing a fin additional, fin is arranged in the chip top, and a large amount of heat conduction that chip produces is diffused in the air by the fabulous fin of heat dispersion then to fin; Fin has adopted the structure of boss and sidewall opening to guarantee that plastic packaging material is full of whole cavity volume; The design of fin lower through-hole has guaranteed fin fixing in plastic-sealed body; Particularly the top of fin adopts the structure of cannelure, has solved the problem of colloid overflow to the fin top.
Aforesaid preferred embodiment should be noted the invention is not restricted to, clearly various remodeling, additional and replace and do not break away from the invention spirit and scope that appended claims of the present invention limits can be made by those of ordinary skill in the art.
Claims (8)
1. method for packaging semiconductor is characterized in that:
On chip, cover a fin;
The lower end of this fin is connected with substrate with bonding agent;
The packaging body surface is exposed on the top of fin, and the heat that chip is produced is dispersed in the air;
Resin or similar substance are full of between fin and the chip, and the fin sidewall, with the protection chip circuit;
At the sidewall opening of fin, be beneficial in the plastic packaging process, colloid injects and air is discharged;
The fin lower edge has some breach, can produce distortion in the fin pressurized, alleviates the stress that the fin sidewall produces.
2. according to the method for packing described in the claim 1, it is characterized in that fin is made by Heat Conduction Material.
3. according to the method for packing described in the claim 2, it is characterized in that fin material can be copper.
4. according to the method for packing described in the claim 2, it is characterized in that fin material can be aluminium.
5. according to the method for packing described in the claim 1, it is characterized in that a plurality of projectioies are arranged at the bottom of fin, are used for supporting fin.In the middle of fin and substrate, produce at interval simultaneously, help plastic packaging glue and pour into.
6. according to the method for packing described in the claim 5, it is characterized in that the next door of bossing has some through holes, passes through in order to plastic packaging material, make the fin location more accurate, firm.
7. according to the method for packing described in the claim 1, it is characterized in that the fin tip edge has an annular vallecular cavity, play and avoid colloid to rush to the effect on fin top.
8. according to the method for packing described in the claim 1, it is characterized in that the fin lower end is electrical connected by circuit and substrate earth polar, plays the electrostatic screen effect, circuit electrical property in improving.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01139258 CN1291466C (en) | 2001-12-27 | 2001-12-27 | Semiconductor package with radiator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01139258 CN1291466C (en) | 2001-12-27 | 2001-12-27 | Semiconductor package with radiator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1428830A CN1428830A (en) | 2003-07-09 |
| CN1291466C true CN1291466C (en) | 2006-12-20 |
Family
ID=4675180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01139258 Expired - Fee Related CN1291466C (en) | 2001-12-27 | 2001-12-27 | Semiconductor package with radiator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1291466C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025072B (en) * | 2009-09-15 | 2012-11-21 | 东莞莫仕连接器有限公司 | Cable connector |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3854957B2 (en) * | 2003-10-20 | 2006-12-06 | 三菱電機株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP4407489B2 (en) * | 2004-11-19 | 2010-02-03 | 株式会社デンソー | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
| CN103021902A (en) * | 2011-09-21 | 2013-04-03 | 国碁电子(中山)有限公司 | Mould casting device and method for semiconductor package |
| TWI479615B (en) * | 2012-08-17 | 2015-04-01 | 矽品精密工業股份有限公司 | Semiconductor package and heat sink thereof |
| CN102931160A (en) * | 2012-11-02 | 2013-02-13 | 敦南微电子（无锡）有限公司 | Flat foot structure of semiconductor device for removing defective gum |
| CN103978871B (en) * | 2013-02-08 | 2018-09-28 | 法国圣戈班玻璃公司 | Quarter window and injection molding assembly forming method, guide rail, quarter window, car door and automobile |
| CN104968179A (en) * | 2015-04-22 | 2015-10-07 | 惠州智科实业有限公司 | Insert injection molding radiator and preparation technology thereof |
| CN106298695B (en) * | 2015-06-05 | 2019-05-10 | 台达电子工业股份有限公司 | Encapsulation module, encapsulation module stacked structure and preparation method thereof |
| CN106531701B (en) * | 2016-12-07 | 2019-10-18 | 江苏长电科技股份有限公司 | A kind of dissipating cover ground connection encapsulating structure and its process |
| CN107835581B (en) * | 2017-11-06 | 2019-10-18 | 上海航天科工电器研究院有限公司 | A kind of encapsulating method of printed board sensitizing range |
| CN108493176B (en) * | 2018-03-27 | 2020-07-10 | 浙江中正智能科技有限公司 | Fingerprint identification chip device and manufacturing method thereof |
| TWI695466B (en) * | 2019-05-31 | 2020-06-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| CN113276348B (en) * | 2020-02-19 | 2023-01-24 | 长鑫存储技术有限公司 | Injection mold and injection molding method |
| CN114613266A (en) * | 2022-03-07 | 2022-06-10 | 深圳市华星光电半导体显示技术有限公司 | Display module and display device |
| CN114999934B (en) * | 2022-07-18 | 2022-10-21 | 威海艾迪科电子科技股份有限公司 | Semiconductor packaging structure and forming method thereof |
-
2001
- 2001-12-27 CN CN 01139258 patent/CN1291466C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102025072B (en) * | 2009-09-15 | 2012-11-21 | 东莞莫仕连接器有限公司 | Cable connector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1428830A (en) | 2003-07-09 |
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| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: Shanghai Guo Shou Jing Road, Pudong Zhangjiang hi tech Park No. 669 Patentee after: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. Address before: No. 5, building 1, building 200, Newton Road, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: GLOBAL ADVANCED PACKAGING TECH |
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| TR01 | Transfer of patent right |
Effective date of registration: 20081205 Address after: No 188, West Rainbow Road, Suzhou Industrial Park, Jiangsu Patentee after: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd. Address before: Shanghai Guo Shou Jing Road, Pudong Zhangjiang hi tech Park No. 669 Patentee before: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. |
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| ASS | Succession or assignment of patent right |
Owner name: SUZHOU RIYUEXIN SEMICONDUCTOR CO., LTD. Free format text: FORMER OWNER: RIYUEGUANG ENCAPSULATION TESTING ( SHANGHAI ) CO., LTD. Effective date: 20081205 |
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| C56 | Change in the name or address of the patentee |
Owner name: RIYUEGUANG ENCAPSULATION TESTING ( SHANGHAI ) CO., Free format text: FORMER NAME: WEIYU TECHNOLOGY TEST ENCAPSULATION CO., LTD. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20061220 Termination date: 20151227 |
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| EXPY | Termination of patent right or utility model |