TWI695466B - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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TWI695466B
TWI695466B TW108118986A TW108118986A TWI695466B TW I695466 B TWI695466 B TW I695466B TW 108118986 A TW108118986 A TW 108118986A TW 108118986 A TW108118986 A TW 108118986A TW I695466 B TWI695466 B TW I695466B
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wall
electronic package
heat dissipation
item
patent application
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TW108118986A
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TW202046468A (en
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蕭玟泓
林興豐
林榮政
陳漢宏
余國華
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矽品精密工業股份有限公司
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Priority to CN201910506545.2A priority patent/CN112018056B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

This invention provides an electronic package and a manufacturing method thereof, which provides a heat dissipation structure surrounding an electronic component on a carrier member provided with the electronic component; and the heat dissipation structure has a passage, such that when performing a molding operation, the flow path of the encapsulating material can flow through the passage to increase the flow smoothness of the encapsulating material.

Description

電子封裝件及其製法 Electronic package and its manufacturing method

本發明係有關一種封裝結構，尤指一種具散熱件之電子封裝件及其製法。 The invention relates to a packaging structure, in particular to an electronic packaging part with heat dissipation parts and a manufacturing method thereof.

隨著電子產品在功能及處理速度之需求的提升，作為電子產品之核心組件的半導體晶片需具有更高密度之電子元件(Electronic Components)及電子電路(Electronic Circuits)，故半導體晶片在運作時將隨之產生更大量的熱能。再者，由於傳統包覆該半導體晶片之封裝膠體係為一種導熱係數僅0.8Wm-1k-1之不良傳熱材質(即熱量之逸散效率不佳)，因而若不能有效逸散半導體晶片所產生之熱量，將會造成半導體晶片之損害與產品信賴性問題。 With the increasing demand for functions and processing speed of electronic products, semiconductor chips as the core components of electronic products need to have higher density of electronic components (Electronic Components) and electronic circuits (Electronic Circuits). A larger amount of heat energy is then generated. Furthermore, since the conventional encapsulant system covering the semiconductor chip is a poor heat transfer material with a thermal conductivity of only 0.8Wm-1k-1 (that is, the heat dissipation efficiency is not good), if the semiconductor chip cannot be effectively dissipated, The heat generated will cause damage to the semiconductor chip and product reliability issues.

因此，為了迅速將熱能散逸至外部，業界通常在半導體封裝件中配置散熱片(Heat Sink或Heat Spreader)，以藉散熱片逸散出半導體晶片所產生之熱量。 Therefore, in order to quickly dissipate heat energy to the outside, the industry usually disposes a heat sink (Heat Sink or Heat Spreader) in the semiconductor package to dissipate the heat generated by the semiconductor chip through the heat sink.

如第1及1’圖所示，習知半導體封裝件1之製法係先將至少一半導體晶片11設於一封裝基板10上，再將一散熱結構1a結合於該封裝基板10上。接著，進行模壓(molding)作業，以令封裝膠體12包覆該半導體晶片 11及散熱結構1a。之後，於該封裝基板10之植球側設置複數銲球15，以供該半導體封裝件1藉由該些銲球15結合至一電路板(圖略)上。 As shown in FIGS. 1 and 1', the conventional manufacturing method of the semiconductor package 1 is to first place at least one semiconductor chip 11 on a package substrate 10, and then combine a heat dissipation structure 1a on the package substrate 10. Next, a molding operation is performed to cover the semiconductor wafer with the encapsulant 12 11 and heat dissipation structure 1a. After that, a plurality of solder balls 15 are provided on the ball-mounting side of the packaging substrate 10 for the semiconductor package 1 to be bonded to a circuit board (not shown) through the solder balls 15.

惟，習知半導體封裝件1中，於進行模壓作業時，由於該散熱結構1a之形狀並無特殊之設計，故該封裝膠體12之膠流於遇到阻礙時容易發生各處流率不一致之問題，因而容易產生氣泡(void)A或該封裝膠體12未填滿之情形，致使該封裝膠體12在熱效應下產生氣爆(popcorn)，導致產品可靠性不佳問題。 However, in the conventional semiconductor package 1, when the molding operation is performed, since the shape of the heat dissipation structure 1a has no special design, the glue flow of the packaging gel 12 is prone to inconsistent flow rates when encountering obstacles As a result, the void A or the encapsulant 12 is not fully filled, which causes the encapsulant 12 to generate popcorn under the thermal effect, resulting in poor product reliability.

因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become a problem that the industry urgently needs to overcome.

鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：一承載結構，係具有相對之第一側與第二側；至少一電子元件，係設於該承載結構之第一側上；一散熱結構，係設於該承載結構之第一側上且具有至少一貫穿之通道；以及一封裝層，係形成於該承載結構之第一側上以包覆該電子元件與散熱結構。 In view of the above-mentioned defects of the prior art, the present invention provides an electronic package including: a supporting structure having opposite first and second sides; and at least one electronic component provided on the first side of the supporting structure On the side; a heat dissipation structure, which is provided on the first side of the carrying structure and has at least one through channel; and an encapsulation layer, which is formed on the first side of the carrying structure to cover the electronic components and heat dissipation structure.

本發明亦提供一種電子封裝件之製法，係包括：提供一具有相對之第一側與第二側之承載結構，並於該第一側上配置至少一電子元件與一散熱結構，其中，該散熱結構具有至少一貫穿之通道；以及形成封裝層於該承載結構之第一側上，以令該封裝層包覆該電子元件與該散熱結構。 The invention also provides a method for manufacturing an electronic package, which comprises: providing a supporting structure having opposite first and second sides, and at least one electronic component and a heat dissipation structure are arranged on the first side, wherein the The heat dissipation structure has at least one through channel; and an encapsulation layer is formed on the first side of the carrying structure, so that the encapsulation layer covers the electronic component and the heat dissipation structure.

前述之電子封裝件及其製法中，該電子元件之部分表面係外露出該封裝層。 In the aforementioned electronic package and its manufacturing method, part of the surface of the electronic component is exposed to the packaging layer.

前述之電子封裝件及其製法中，該散熱結構之部分表面係外露出該封裝層。 In the aforementioned electronic package and its manufacturing method, part of the surface of the heat dissipation structure exposes the package layer.

前述之電子封裝件及其製法中，該散熱結構係包含至少一圍繞該電子元件之牆體，且該牆體係設有複數開口，以令該複數開口作為該通道之埠口。例如，該牆體形成有缺口以作為該開口，且該牆體係以該缺口朝向及/或該承載結構之方式作設置。或者，該通道係延伸至該承載結構內。 In the aforementioned electronic package and its manufacturing method, the heat dissipation structure includes at least one wall surrounding the electronic component, and the wall system is provided with a plurality of openings, so that the plurality of openings serve as ports of the channel. For example, the wall body is formed with a notch as the opening, and the wall system is arranged in such a manner that the notch faces and/or the bearing structure. Alternatively, the channel extends into the carrying structure.

前述之電子封裝件及其製法中，復包括將散熱件結合於該電子元件上。 In the aforementioned electronic package and its manufacturing method, the heat dissipation component is combined with the electronic component.

前述之電子封裝件及其製法中，復包括形成複數導電元件於該承載結構之第二側上。 In the aforementioned electronic package and its manufacturing method, the method includes forming a plurality of conductive elements on the second side of the supporting structure.

由上可知，本發明之電子封裝件及其製法，主要藉由該散熱結構具有通道之設計，以於進行模壓作業時，令封裝層之流動路徑能流通該通道而增加該封裝層之流動順暢度，故相較於習知技術，本發明之封裝層於各處之膠體之流率大致相同，避免產生氣泡或該封裝層未填滿之問題，以在熱效應下不會產生氣爆，進而提高產品可靠性，以利於量產。 It can be seen from the above that the electronic package and its manufacturing method of the present invention mainly use the design of the heat dissipation structure with channels, so that when the molding operation is performed, the flow path of the packaging layer can flow through the channel to increase the smooth flow of the packaging layer Compared with the conventional technology, the flow rate of the colloid in the encapsulation layer of the present invention is almost the same, to avoid the problem of bubbles or the encapsulation layer is not filled, so that no gas explosion will occur under the thermal effect, and Improve product reliability to facilitate mass production.

1‧‧‧半導體封裝件 1‧‧‧Semiconductor package

1a,3a,3a’,4a‧‧‧散熱結構 1a,3a,3a’,4a‧‧‧radiating structure

10‧‧‧封裝基板 10‧‧‧Package substrate

11‧‧‧半導體晶片 11‧‧‧Semiconductor chip

12‧‧‧封裝膠體 12‧‧‧Packing colloid

15‧‧‧銲球 15‧‧‧solder ball

2‧‧‧電子封裝件 2‧‧‧Electronic package

20‧‧‧承載結構 20‧‧‧bearing structure

20a‧‧‧第一側 20a‧‧‧First side

20b‧‧‧第二側 20b‧‧‧Second side

200‧‧‧第三開口 200‧‧‧ third opening

21‧‧‧電子元件 21‧‧‧Electronic components

21a,22a‧‧‧表面 21a, 22a‧‧‧surface

22‧‧‧封裝層 22‧‧‧Encapsulation layer

23‧‧‧散熱件 23‧‧‧Cooling parts

230‧‧‧散熱體 230‧‧‧heat radiator

231‧‧‧支撐腳 231‧‧‧support feet

24‧‧‧結合層 24‧‧‧Combination layer

25‧‧‧導電元件 25‧‧‧Conducting element

30‧‧‧通道 30‧‧‧channel

31‧‧‧第一牆體 31‧‧‧The first wall

310,310’,40a‧‧‧第一開口 310,310’,40a‧‧‧First opening

32‧‧‧第二牆體 32‧‧‧Second wall

320,320’,40b‧‧‧第二開口 320,320’,40b‧‧‧Second opening

9‧‧‧電子裝置 9‧‧‧Electronic device

A‧‧‧氣泡 A‧‧‧Bubble

S‧‧‧容置空間 S‧‧‧accommodation space

Y‧‧‧模流方向 Y‧‧‧mold flow direction

第1圖係為習知半導體封裝件之剖視示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.

第1’圖係為第1圖之局部上視示意圖。 Figure 1'is a schematic partial top view of Figure 1.

第2A至2C圖係為本發明之電子封裝件之製法之剖視示意圖。 2A to 2C are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

第2A-1、2A-2及2A-3圖係為第2A圖之其它態樣之局部示意圖。 Figures 2A-1, 2A-2 and 2A-3 are partial schematic views of other aspects of Figure 2A.

第2B’圖係為第2B圖之另一態樣之局部示意圖。 Figure 2B' is a partial schematic view of another aspect of Figure 2B.

第2B”圖係為第2B圖之上視示意圖。 Figure 2B" is a schematic top view of Figure 2B.

第3圖係為本發明之散熱結構之立體示意圖。 FIG. 3 is a three-dimensional schematic diagram of the heat dissipation structure of the present invention.

第3’圖係為第3圖之另一實施例的立體示意圖。 Fig. 3'is a schematic perspective view of another embodiment of Fig. 3.

第4A圖係為第3圖之另一實施例的立體示意圖。 FIG. 4A is a schematic perspective view of another embodiment of FIG. 3.

第4B至4D圖係為第4A圖之孔端形狀之其它態樣的局部平面圖。 Figures 4B to 4D are partial plan views of other aspects of the hole end shape of Figure 4A.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之 範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the content disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions do not have technical significance. Any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, not for limiting the invention. The scope, the change or adjustment of its relative relationship, without substantial changes in the technical content, should also be regarded as the scope of the invention.

第2A至2C圖係為本發明之電子封裝件2之製法之剖面示意圖。 2A to 2C are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

如第2A圖所示，提供一具有相對之第一側20a與第二側20b之承載結構20，其第一側20a係配置有至少一電子元件21及一具有通道30之散熱結構3a。 As shown in FIG. 2A, a supporting structure 20 having a first side 20a and a second side 20b opposite to each other is provided. The first side 20a is configured with at least one electronic component 21 and a heat dissipation structure 3a having a channel 30.

所述之承載結構20係為整版面基板形式，即該整版面基板包含複數基板單元，例如為具有核心層與線路結構之封裝基板或無核心層(coreless)之線路結構，其包含至少一絕緣層及至少一結合該絕緣層之線路層，如至少一扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該承載結構20亦可為其它承載晶片之板材，如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。 The supporting structure 20 is in the form of a full-page substrate, that is, the full-page substrate includes a plurality of substrate units, such as a package substrate with a core layer and a circuit structure or a coreless circuit structure, which includes at least one insulation Layer and at least one circuit layer combined with the insulating layer, such as at least one fan-out type redistribution layer (RDL). It should be understood that the supporting structure 20 may also be other boards carrying chips, such as lead frames, wafers, or other carrier boards with metal routing, etc., which are not limited to the above.

於本實施例中，該承載結構20之製程方式繁多，例如，可採用晶圓製程製作線路層，而以化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽以作為絕緣層；或者，可採用一般非晶圓製程方式形成線路層，即採用成本較低之高分子介電材作為絕緣層，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、預浸材(Prepreg，簡稱PP)、封裝膠體(molding compound)、感光型介電層或其它材質等以塗佈方式形成之。 In this embodiment, the carrier structure 20 has a variety of manufacturing methods. For example, a wafer process may be used to form a circuit layer, and chemical vapor deposition (Chemical Vapor Deposition, CVD for short) is used to form silicon nitride or silicon oxide as insulation Or, a non-wafer process can be used to form the circuit layer, that is, a low-cost polymer dielectric material is used as the insulating layer, such as polyimide (Polyimide, PI), polybenzoxazole (Polybenzoxazole) , Referred to as PBO), prepreg (Prepreg, PP), molding compound, photosensitive dielectric layer or other materials are formed by coating.

所述之電子元件21係為主動元件、被動元件或其組合者，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該電子元件21係為半導體晶片，其可藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊以覆晶方式設於該承載結構之線路層上並電性連接該線路層；或者，該電子元件21可藉由複數銲線以打線方式電性連接該承載結構20之線路層；亦或，該電子元件21可直接接觸該承載結構20之線路層。因此，可於該承載結構20上接置任意種類或數量之電子元件，以提升其電性功能，且有關電子元件21電性連接承載結構20之方式繁多，並不限於上述。 The electronic component 21 is an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which can be flip-chip mounted on the circuit layer of the carrier structure by a plurality of conductive bumps such as solder material, metal pillars or other The circuit layer is electrically connected; alternatively, the electronic component 21 can be electrically connected to the circuit layer of the carrier structure 20 by a plurality of bonding wires; or, the electronic component 21 can directly contact the circuit layer of the carrier structure 20 . Therefore, any type or number of electronic components can be connected to the supporting structure 20 to enhance its electrical function. There are many ways for the electronic components 21 to electrically connect to the supporting structure 20, which is not limited to the above.

所述之散熱結構3a係位於該電子元件21之外圍，如圍繞該電子元件21之四個側邊，且該散熱結構3a係具有至少一貫穿其中之通道30，以供後續封裝層22之材質流過。 The heat dissipation structure 3a is located at the periphery of the electronic component 21, such as surrounding the four sides of the electronic component 21, and the heat dissipation structure 3a has at least one channel 30 therethrough for the material of the subsequent packaging layer 22 flow past.

於本實施例中，如第3及3’圖所示，該散熱結構3a係為金屬體，如銅材，其包含相互呈內、外配置之第一牆體31與第二牆體32，以令該些電子元件21容置於該散熱結構3a(或該第二牆體32)所圍束之容置空間S中，其中，該第一牆體31於至少一側設有複數第一開口310,310’(於本實施例中係於第一牆體之相對兩側具有相互對應之複數第一開口)，且該第二牆體32於至少一側設有複數第二開口320,320’(於本實施例中係於第二牆體之相對兩側具有相互對應之複數第二開口)，使位於外牆之第一開口310,310’作為該通道30之埠口，且令該第一開口310,310’與第二開口320,320’相互連通(如對齊)而形成該通道30。例如，該第一牆體31之其 中一側之第一開口310係作為供封裝層22流入之入口，而該第一牆體31之另一側之第一開口310’係作為供封裝層22流出之出口。 In this embodiment, as shown in Figures 3 and 3', the heat dissipation structure 3a is a metal body, such as copper, which includes a first wall 31 and a second wall 32 that are arranged inside and outside each other, To allow the electronic components 21 to be accommodated in the accommodating space S surrounded by the heat dissipation structure 3a (or the second wall 32), wherein the first wall 31 is provided with a plurality of first on at least one side Openings 310, 310' (in this embodiment, there are plural first openings corresponding to each other on opposite sides of the first wall), and the second wall 32 is provided with plural second openings 320, 320' (at In this embodiment, there are a plurality of second openings corresponding to each other on opposite sides of the second wall, so that the first openings 310, 310' located on the outer wall serve as the ports of the passage 30, and the first openings 310, 310' The second openings 320, 320' communicate with each other (eg, align) to form the channel 30. For example, the first wall 31 has The first opening 310 on the middle side serves as an inlet for the encapsulation layer 22 to flow in, and the first opening 310' on the other side of the first wall 31 serves as an outlet for the encapsulation layer 22 to flow out.

再者，本實施例中主要於該第一牆體31與第二牆體32上形成複數缺口以作為該第一開口310,310’及第二開口320,320’。例如，該第一牆體31與第二牆體32以該第一開口310,310’及第二開口320,320’朝向該承載結構20之方式作設置，如第2A及3圖所示；或者，該第一牆體31與第二牆體32以該第一開口310,310’及第二開口320,320’背向該承載結構20之方式作設置，如第2A-1及3’圖所示；亦或，該通道30可延伸至該承載結構20內，如第2A-2圖所示，即該承載結構20之第一側20a於對應該第一開口310,310’及第二開口320,320’處可形成第三開口200。 Furthermore, in this embodiment, a plurality of notches are mainly formed on the first wall 31 and the second wall 32 to serve as the first openings 310, 310' and the second openings 320, 320'. For example, the first wall 31 and the second wall 32 are arranged with the first openings 310, 310' and the second openings 320, 320' facing the bearing structure 20, as shown in FIGS. 2A and 3; or, the first A wall 31 and a second wall 32 are arranged with the first openings 310, 310' and the second openings 320, 320' facing away from the carrying structure 20, as shown in Figures 2A-1 and 3'; or, the The channel 30 can extend into the supporting structure 20, as shown in FIG. 2A-2, that is, the first side 20a of the supporting structure 20 can form a third opening at the position corresponding to the first opening 310, 310' and the second opening 320, 320' 200.

又，於其它實施例中，可將散熱結構3a’之部分通道30之部分缺口朝上而部分通道30之缺口朝下，如第2A-3圖所示。 Moreover, in other embodiments, the partial notch of the partial channel 30 of the heat dissipation structure 3a' may be directed upward and the notch of the partial channel 30 may be directed downward, as shown in FIGS. 2A-3.

另外，該第一牆體31之第一開口40a與第二牆體32之第二開口40b可呈穿孔狀，其孔端形狀可依需求設計為圓形、方形、三角形或任意幾何圖形，並無特別限制，如第4A至4D圖所示之散熱結構4a。 In addition, the first opening 40a of the first wall 31 and the second opening 40b of the second wall 32 can be perforated, and the shape of the hole end can be designed as a circle, square, triangle or any geometric shape according to requirements, and There is no particular limitation, as shown in Figures 4A to 4D of the heat dissipation structure 4a.

如第2B圖所示，形成封裝層22於該承載結構20之第一側20a上，以令該封裝層22經由該通道30包覆該電子元件21與散熱結構3a。 As shown in FIG. 2B, an encapsulation layer 22 is formed on the first side 20 a of the carrier structure 20 so that the encapsulation layer 22 covers the electronic component 21 and the heat dissipation structure 3 a through the channel 30.

於本實施例中，形成該封裝層22之材質係為絕緣材，如聚醯亞胺(PI)、環氧樹脂(epoxy)之封裝膠體或封裝材，其可用模壓(molding)、壓合(lamination)或塗佈(coating)之方式形成之。 In this embodiment, the material forming the encapsulation layer 22 is an insulating material, such as polyimide (PI), epoxy encapsulation gel or encapsulation material, which can be molded or pressed ( It is formed by lamination) or coating.

再者，可藉由如研磨方式之整平製程移除該封裝層22之部分材質，使該電子元件21之表面21a齊平該封裝層22之表面22a，以令該電子元件21外露於該封裝層22之表面22a。 Furthermore, part of the material of the encapsulation layer 22 can be removed by a leveling process such as grinding, so that the surface 21a of the electronic component 21 is flush with the surface 22a of the encapsulation layer 22, so that the electronic component 21 is exposed to the The surface 22a of the encapsulation layer 22.

又，該散熱結構3a未外露於該封裝層22之表面22a；於另一實施例中，如第2B’圖所示，該散熱結構3a之部分表面亦可外露於該封裝層22之表面22a。 Moreover, the heat dissipation structure 3a is not exposed on the surface 22a of the encapsulation layer 22; in another embodiment, as shown in FIG. 2B', part of the surface of the heat dissipation structure 3a may also be exposed on the surface 22a of the encapsulation layer 22 .

另外，可形成複數導電元件25於該承載結構20下側。例如，該導電元件25可為如銅柱之金屬柱、包覆有絕緣塊之金屬凸塊、銲球(solder ball)、具有核心銅球(Cu core ball)之銲球或其它導電構造等。 In addition, a plurality of conductive elements 25 can be formed on the lower side of the supporting structure 20. For example, the conductive element 25 may be a metal pillar such as a copper pillar, a metal bump coated with an insulating block, a solder ball, a solder ball with a core copper ball, or other conductive structures.

如第2C圖所示，設置一散熱件23於該封裝層22之表面22a上，且該散熱件23藉由結合層24結合該電子元件21之表面21a。 As shown in FIG. 2C, a heat dissipation element 23 is provided on the surface 22a of the encapsulation layer 22, and the heat dissipation element 23 is coupled to the surface 21a of the electronic component 21 through the bonding layer 24.

於本實施例中，該散熱件23係具有一散熱體230與複數設於該散熱體230下側之支撐腳231，該散熱體230係為散熱片型式，並以下側接觸該結合層24，且該支撐腳231係結合於該封裝層22之表面22a上。 In this embodiment, the heat dissipation element 23 has a heat dissipation body 230 and a plurality of support legs 231 provided on the lower side of the heat dissipation body 230. The heat dissipation body 230 is a heat sink type, and contacts the bonding layer 24 on the lower side. And the supporting leg 231 is coupled to the surface 22a of the encapsulation layer 22.

再者，該結合層24係為導熱介面材(Thermal Interface Material，簡稱TIM)或導熱膠，但並無特別限制。 Furthermore, the bonding layer 24 is a thermal interface material (TIM) or thermally conductive adhesive, but it is not particularly limited.

又，該散熱結構3a之材質可相同或不同於該散熱件23(或該散熱體230)之材質。 In addition, the material of the heat dissipation structure 3a may be the same as or different from the material of the heat dissipation element 23 (or the heat dissipation body 230).

另外，該電子封裝件2可藉由該些導電元件25接置一如電路板之電子裝置9。 In addition, the electronic package 2 can be connected to an electronic device 9 such as a circuit board through the conductive elements 25.

本發明之製法中，主要藉由散熱結構3a形成有貫穿之通道30之設計，以於進行模壓作業時，令封裝層22之膠流能流通該通道30，且利 用該散熱結構3a之第一開口310,310’,40a與第二開口320,320’,40b之開口方向與該封裝層22之模流方向Y(如第2B”圖所示)一致，使該封裝層22之膠體之流率一致，避免產生氣泡或該封裝層22未填滿之問題，故相較於習知技術，本發明之電子封裝件2之封裝層22在熱效應下不會產生氣爆，因而能提高可靠性，以利於量產。 In the manufacturing method of the present invention, the design of the through channel 30 is mainly formed by the heat dissipation structure 3a, so that when the molding operation is performed, the glue flow of the encapsulation layer 22 can flow through the channel 30, and the Use the opening directions of the first openings 310, 310', 40a and the second openings 320, 320', 40b of the heat dissipation structure 3a to be consistent with the mold flow direction Y (as shown in FIG. 2B) of the packaging layer 22, so that the packaging layer 22 The flow rate of the colloid is consistent, to avoid the problem of bubbles or the encapsulation layer 22 is not filled, so compared with the conventional technology, the encapsulation layer 22 of the electronic package 2 of the present invention will not produce gas explosion under the thermal effect, so It can improve reliability and facilitate mass production.

本發明復提供一種電子封裝件2，係包括：一承載結構20、至少一電子元件21、一散熱結構3a,3a’,4a以及一封裝層22。 The present invention further provides an electronic package 2 comprising: a supporting structure 20, at least one electronic component 21, a heat dissipation structure 3a, 3a', 4a and a packaging layer 22.

所述之承載結構20係具有相對之第一側20a與第二側20b。 The supporting structure 20 has a first side 20a and a second side 20b opposite to each other.

所述之電子元件21係設於該承載結構20之第一側20a上。 The electronic component 21 is disposed on the first side 20a of the supporting structure 20.

所述之散熱結構3a,3a’,4a係設於該承載結構20之第一側20a上且具有至少一貫穿之通道30。 The heat dissipation structure 3a, 3a', 4a is disposed on the first side 20a of the carrying structure 20 and has at least one channel 30 therethrough.

所述之封裝層22係形成於該承載結構20之第一側20a上以包覆該電子元件21與散熱結構3a,3a’,4a。 The encapsulation layer 22 is formed on the first side 20a of the carrier structure 20 to cover the electronic component 21 and the heat dissipation structure 3a, 3a', 4a.

於一實施例中，該電子元件21之部分表面係外露於該封裝層22之表面22a。 In one embodiment, a part of the surface of the electronic component 21 is exposed on the surface 22a of the packaging layer 22.

於一實施例中，該散熱結構3a之部分表面係外露於該封裝層22之表面22a。 In one embodiment, a part of the surface of the heat dissipation structure 3a is exposed on the surface 22a of the packaging layer 22.

於一實施例中，該散熱結構3a,3a’,4a係包含至少一圍繞該電子元件21之第一牆體31與第二牆體32，且該第一牆體31與第二牆體32係分別設有複數第一開口310,310’,40a與第二開口320,320’,40b，以令該複數第一開口310,310’,40a與第二開口320,320’,40b作為該通道30之埠口。例如，該第一牆體31與第二牆體32形成有缺口以作為該複數第一開口310,310’與 第二開口320,320’，且該散熱結構3a,3a’係以該缺口朝向及/或背向該承載結構20之方式作設置。或者，該通道30可延伸至該承載結構20內。 In an embodiment, the heat dissipation structure 3a, 3a', 4a includes at least a first wall 31 and a second wall 32 surrounding the electronic component 21, and the first wall 31 and the second wall 32 A plurality of first openings 310, 310', 40a and second openings 320, 320', 40b are respectively provided, so that the plurality of first openings 310, 310', 40a and second openings 320, 320', 40b serve as ports of the channel 30. For example, the first wall 31 and the second wall 32 are formed with gaps to serve as the plurality of first openings 310, 310’ and The second opening 320, 320', and the heat dissipation structure 3a, 3a' are arranged in such a manner that the notch faces and/or faces away from the carrying structure 20. Alternatively, the channel 30 can extend into the carrying structure 20.

於一實施例中，所述之電子封裝件2復包括一結合於該電子元件21上之散熱件23。 In one embodiment, the electronic package 2 includes a heat sink 23 coupled to the electronic component 21.

於一實施例中，所述之電子封裝件2復包括形成於該承載結構20之第二側20b上的複數導電元件25。 In one embodiment, the electronic package 2 includes a plurality of conductive elements 25 formed on the second side 20b of the supporting structure 20.

綜上所述，本發明之電子封裝件及其製法，係藉由設在承載結構上之散熱結構形成有通道之設計，以於進行該模壓作業時，令封裝層之膠流能流通該通道，因而不會產生氣泡或該封裝層未填滿之問題，故本發明之電子封裝件在熱效應下不會產生氣爆，因而能提高可靠性，以利於量產。 In summary, the electronic package of the present invention and its manufacturing method are designed with channels formed by the heat dissipation structure provided on the supporting structure, so that when the molding operation is performed, the glue flow of the packaging layer can flow through the channels Therefore, the problem of bubbles or the underfill of the packaging layer is not generated. Therefore, the electronic package of the present invention does not generate gas explosion under the thermal effect, and thus can improve reliability and facilitate mass production.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.

3a‧‧‧散熱結構 3a‧‧‧heat dissipation structure

21‧‧‧電子元件 21‧‧‧Electronic components

22‧‧‧封裝層 22‧‧‧Encapsulation layer

30‧‧‧通道 30‧‧‧channel

Y‧‧‧模流方向 Y‧‧‧mold flow direction

Claims (14)

一種電子封裝件，係包括：一承載結構，係具有相對之第一側與第二側；至少一電子元件，係設於該承載結構之第一側上；一散熱結構，係包含圍繞該電子元件之牆體，其中，該牆體設於該承載結構之第一側上且具有至少一貫穿之通道，其中，該牆體之至少兩側係設有開口，使該兩側之開口作為該通道之埠口；以及一封裝層，係形成於該承載結構之第一側上以包覆該電子元件與散熱結構，其中，該牆體之其中一側之開口作為供該封裝層流入之入口，而該牆體之另一側之開口作為供該封裝層流出之出口。 An electronic package includes: a supporting structure having opposite first and second sides; at least one electronic component disposed on the first side of the supporting structure; and a heat dissipating structure including surrounding the electronic A wall of elements, wherein the wall is provided on the first side of the bearing structure and has at least one channel therethrough, wherein at least two sides of the wall are provided with openings, so that the openings on both sides serve as the A port of the channel; and an encapsulation layer formed on the first side of the carrying structure to cover the electronic component and the heat dissipation structure, wherein the opening on one side of the wall serves as an entrance for the inflow of the encapsulation layer The opening on the other side of the wall serves as an outlet for the encapsulation layer. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件之部分表面係外露出該封裝層。 The electronic package as described in item 1 of the patent application scope, wherein part of the surface of the electronic component is exposed to the packaging layer. 如申請專利範圍第1項所述之電子封裝件，其中，該散熱結構之部分表面係外露出該封裝層。 The electronic package as described in item 1 of the patent application scope, wherein part of the surface of the heat dissipation structure exposes the packaging layer. 如申請專利範圍第1項所述之電子封裝件，其中，該牆體形成有缺口以作為該開口，且該缺口係以朝向及/或背向該承載結構之方式設置於該牆體。 The electronic package as described in item 1 of the patent application scope, wherein the wall is formed with a notch as the opening, and the notch is disposed on the wall in a manner facing and/or away from the carrying structure. 如申請專利範圍第1項所述之電子封裝件，其中，該通道係延伸至該承載結構內。 The electronic package as described in item 1 of the patent application scope, wherein the channel extends into the carrying structure. 如申請專利範圍第1項所述之電子封裝件，復包括結合於該電子元件上之散熱件。 The electronic package described in item 1 of the scope of the patent application includes a heat sink bonded to the electronic component. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該承載結構之第二側上的複數導電元件。 The electronic package as described in item 1 of the scope of the patent application includes a plurality of conductive elements formed on the second side of the carrier structure. 一種電子封裝件之製法，係包括：提供一具有相對之第一側與第二側之承載結構，並於該第一側上配置至少一電子元件與一散熱結構，其中，該散熱結構係包含圍繞該電子元件之牆體，且該牆體具有至少一貫穿之通道，其中，該牆體之至少兩側係設有開口，使該兩側之開口作為該通道之埠口；以及形成封裝層於該承載結構之第一側上，以令該封裝層包覆該電子元件與該散熱結構，其中，該牆體之其中一側之開口作為供該封裝層流入之入口，而該牆體之另一側之開口作為供該封裝層流出之出口。 A method for manufacturing an electronic package includes: providing a supporting structure having opposite first and second sides, and at least one electronic component and a heat dissipation structure are disposed on the first side, wherein the heat dissipation structure includes A wall surrounding the electronic component, and the wall has at least one through channel, wherein at least two sides of the wall are provided with openings, so that the openings on both sides serve as ports of the channel; and forming an encapsulation layer On the first side of the carrying structure, the encapsulation layer covers the electronic component and the heat dissipation structure, wherein the opening on one side of the wall serves as an entrance for the encapsulation layer to flow in, and the wall The opening on the other side serves as an outlet for the encapsulation layer to flow out. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該電子元件之部分表面係外露出該封裝層。 The method for manufacturing an electronic package as described in item 8 of the patent application scope, wherein part of the surface of the electronic component is exposed to the packaging layer. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該散熱結構之部分表面係外露出該封裝層。 The method for manufacturing an electronic package as described in item 8 of the patent application scope, wherein part of the surface of the heat dissipation structure exposes the packaging layer. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該牆體形成有缺口以作為該開口，且該缺口係以朝向及/或背向該承載結構之方式設置於該牆體。 The method for manufacturing an electronic package as described in item 8 of the patent application scope, wherein the wall is formed with a notch as the opening, and the notch is disposed on the wall in a manner facing and/or away from the carrying structure . 如申請專利範圍第8項所述之電子封裝件之製法，其中，該通道係延伸至該承載結構內。 The method of manufacturing an electronic package as described in item 8 of the patent application scope, wherein the channel extends into the carrying structure. 如申請專利範圍第8項所述之電子封裝件之製法，復包括將一散熱件結合於該電子元件上。 The method of manufacturing an electronic package as described in item 8 of the scope of the patent application includes combining a heat sink on the electronic component. 如申請專利範圍第8項所述之電子封裝件之製法，復包括形成複數導電元件於該承載結構之第二側上。 According to the method of manufacturing an electronic package described in item 8 of the patent application scope, the method includes forming a plurality of conductive elements on the second side of the carrier structure.
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