CN1287514C - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN1287514C CN1287514C CNB2004100287351A CN200410028735A CN1287514C CN 1287514 C CN1287514 C CN 1287514C CN B2004100287351 A CNB2004100287351 A CN B2004100287351A CN 200410028735 A CN200410028735 A CN 200410028735A CN 1287514 C CN1287514 C CN 1287514C
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Abstract
本发明的课题是,提供一种不受接地用导线的离散性影响、实现了小型-轻量化及低成本化的半导体装置,该半导体装置配备平衡型匹配电路。放大用半导体芯片(FET4)被连接在输入匹配电路(12)与输出匹配电路(15)之间,各匹配电路被设置在配备了从输入信号产生的信号的相位相差180度的平衡型电路的IPD上,将能够连接两匹配电路的虚拟接地点(VE)用作对RF特性敏感的接地点。
Description
技术领域
本发明涉及半导体装置,特别是涉及在800MHz以上高频段使用的具有平衡型电路的半导体装置。
背景技术
现在,作为将多个IC芯片安装在一个封装内的半导体装置,为了获得IC芯片之间的电连接,在中间设置中继电极部,通过该中继电极部在进行IC芯片间的电连接的同时,也进行与外部的连接,将中继电极部以对称形状配置在绝缘基板上,在绝缘基板的表面固定并形成各种电路图形,用焊料等在各电路图形上连接安装多个半导体芯片。
作为现有的高频-高输出功率用半导体装置,例如,提出了使用推挽型大功率放大器的半导体装置的建议(例如,参照专利文献1及专利文献2)。图14是表示现有的半导体装置的一例的俯视图,图15是图14所示的推挽型大功率放大器的等效电路图。在该现有例中,公开了移动通信的基站用推挽型大功率放大器,主要使用在0.8~2.4GHz的高频段。
在图14、15中,符号1是PCB绝缘性基板,全部的电路部件都安装在该基板上,用锡焊将半导体芯片部件等安装在布线上。输入信号由输入侧的平衡-不平衡变换器2分割成相位相差180度的2个信号分量,被各个半导体芯片(例如,场效应晶体管FET)4放大,并被右侧的输出侧平衡-不平衡变换器2合成。由于使用这样的推挽型结构,在FET4中产生的畸变分量被消除,降低因畸变引起的次品。
图中的符号6、6′表示2级结构的内部匹配电路基板,将各FET4的低阻抗变换成高阻抗。11是金属线等的导电性导线,3是封装,5是封装的引线。布线10在PCB基板1上形成,在布线上安装作为芯片电容部的电容器9和芯片电阻器8。另外,用设置在基板内的通孔布线7连接基板上表面的各电极与背面的接地电极。
〔专利文献1〕
特开平6-6151号公报(段落0022、图1)
〔专利文献2〕
特开平7-263634号公报(段落0011、图1)
但是,在上述现有的推挽型大功率放大器中,由于电路部件的大部分在PCB基板1上形成,存在器件尺寸及重量增大、成本增高的问题。另外,由于是用焊料将芯片部件等安装在布线上,存在对位误差大、高频特性(RF特性)的离散度增大的问题。特别是在由从平衡-不平衡变换器到封装引线的部分的扼流圈L和电容器C等构成的匹配电路部中,当芯片电容部9(电容器C)的位置产生偏离时,等效地扼流圈L的值产生改变,匹配将产生偏离,其结果是,存在大功率放大器的特性产生很大偏离的问题。
发明内容
本发明是为了解决上述问题而进行的,其目的在于:提供一种在使半导体装置能够小型-轻量化的同时、能够降低成本、并降低了因部件的对位误差引起的RF特性离散度的半导体装置。
为达上述目的,本发明的半导体装置,在输入匹配电路与输出匹配电路之间连接放大器用半导体芯片,以上述输入匹配电路接收相位相差180度的两个信号分量,并且由上述放大器用半导体芯片放大,其特征在于:上述输入匹配电路与上述输出匹配电路分别具有在高频无源元件(IPD)上设置的一对平衡型电路,上述各匹配电路,在包含串联连接的电感器时,在上述一对平衡型电路之间设置单一的接地电容器或一对互相连接的接地电容器,而且将上述单一的接地电容器的中心部或上述一对连接的接地电容器之间的连线部分作为虚拟接地点,上述各匹配电路,在包含串联连接的电容器时,在上述一对平衡型电路之间设置单一的接地电感器或一对互相连接的接地电感器,而且将上述单一的接地电感器的中心部或上述一对互相连接的接地电感器之间的连线部分作为虚拟接地点。
根据上述结构,由于能够将能连接各匹配电路的两平衡型电路之间的虚拟接地点用作对RF特性敏感的接地点,因而消除接地电感的离散性,能够不受接地用导线离散性的影响、在IPD上构成匹配电路,在能够实现半导体装置的小型-轻量化、低成本化的同时,能够降低因部件的对位精度引起的RF特性的离散度。
附图说明
图1是本发明实施例1的半导体装置的俯视图。
图2是图1的输出侧平衡型匹配电路的俯视图。
图3是图2的等效电路图。
图4是表示用各自的IPD构成各匹配电路的比较例的半导体装置的俯视图。
图5是图4的输出侧IPD的俯视图。
图6是图5的等效电路图。
图7是本发明实施例2的半导体装置的输出侧IPD的俯视图。
图8是图7的等效电路图。
图9是本发明实施例3的半导体装置的俯视图。
图10是图9的输出侧内置平衡-不平衡变换器的IPD的俯视图。
图11是图10的等效电路图。
图12是本发明实施例4的半导体装置的俯视图。
图13是图12的相邻的IPD部分的放大俯视图。
图14是表示现有的半导体装置一例的俯视图。
图15是图14的等效电路图。
具体实施方式
以下,参照附图说明本发明的实施例。虽然在本发明的实施例中、将使用了图示的半导体装置的情形作为示例进行说明,但是,本发明并不限于这些示例,它也能够应用于使用了将其他的半导体芯片安装在一个封装中的其他的复合半导体装置的情形。此外,在各图中,对共同的要素标以同一的符号而省略其重复的说明。
实施例1
以下,参照图1至图3说明本发明的实施例1。图1是表示本发明实施例1的半导体装置的俯视图,图2是其输出侧平衡型匹配电路的俯视图,图3是其等效电路图。
图示的结构例就使用推挽型大功率放大器的情况进行说明,该大功率放大器主要使用在0.8~2.4GHz的高频段。图中的参考符号1是PCB基板(绝缘性基板)的机壳,电路部件安装在该基板上。2是平衡-不平衡变换器(balun),是使用于从平衡线路向不平衡线路的连接(变换)或者与其相反的连接(变换)的无源分布常数电路。3是封装,4是高频放大用半导体芯片,分别用场效应晶体管(以下称为FET)构成。
由兼作输入侧(图中是左侧)的功率分配器的端子部的平衡-不平衡变换器2将输入信号分割成相位相差180度的2个信号分量。被分割的信号分量各自通过后述的IPD12输入到FET4上,在由FET4放大后,再通过后述的IPD15,由兼作输出侧(图中是右侧)的功率合成器的端子部的平衡-不平衡变换器2合成。由于使用这样的推挽型结构,在FET4中产生的信号的畸变分量被消除,降低了畸变次品。
图中的符号5是封装的引线,6是内部匹配电路基板,将FET4的低阻抗变换成高阻抗。10是在基板上形成的布线,11是包含电感器要素的金属线等的导电性导线。12是输入侧IPD,13是MIM电容器(C)、14是IPD的绝缘性基板,15是输出侧IPD,16是接地用导线。用该接地用导线连接IPD基板上表面的电极与封装侧的接地电极。
这里,IPD是在玻璃基板或者具有SiO2氧化膜的Si基板上一体地形成了MIM电容器、布线、电阻器等的高频无源元件(IntegratedPassive Device),意味着是没有通路孔(Via hole)的器件。在本实施例中,输入侧IPD12及输出侧IPD15安装在封装3的内部。
在图3所示的输出侧IPD15的等效电路结构中,借助于平衡型电路的各串联连接的电感L1、L2、L3和接地电容C1、C2,将FET4的输出侧内部匹配电路基板6的阻抗变换成输出侧平衡-不平衡变换器2的阻抗。这样,由于各IPD设置2级LC型匹配电路,以将内部匹配电路基板6比现有的结构减少一级的结构,将匹配电路设置在PCB基板1上的封装内。
一般在IPD的制造中,由于使用与硅(Si)晶片工艺相同的工艺,能够以布线精度2微米以下、MIM电容器13的电容精度和电阻的电阻值精度5~10%以下的高精度,形成上述各部件。与芯片部件相比,由于图形的形成精度高、能够进行微细加工,因而能够小型化,其结果是能够实现低成本化。在本实施例中,能够将现有的数厘米量级的PCB基板上的电路小型化到几毫米量级大小。进而,在IPD中,由于基板的电阻比Si基板高,还具有在高频段的损耗小的优点。另外,由于将多个电路要素形成为单片,能够将电路要素间的距离形成为恒定值,得到RF特性稳定的效果。
但是,在IPD中,为了低成本化,一般不设置通路孔。因此,在接地电极上需要通过接地用导线与封装侧的接地电极连接。接地用导线的长度因导线键合机的组装精度产生50~100微米以上的离散度。另外,就导线的形状来说,组装离散度大、特别是在模制(模塑)的情况下,树脂密封时导线形状发生变化,也成为不能得到稳定的RF特性的一个原因。在高频段,因导线长度-形状的变动引起寄生电感成分变化,产生使RF特性变动增大的问题,其中特别是用于LC匹配电路中的接地电容C1、C2部分对半导体装置的RF特性有很大的影响。
因此,在本实施例中,由于在同一IPD内形成平衡型电路的两频道电路,在并联连接两频道间的部分设置接地电容C1和互相相向连接的一对接地电容C2,C1的中心部和2个C2间的连线部成为所谓的虚拟接地点VE(GND)。因此,与接地用导线16的长度-形状等无关地(即使不使用导线16),能够得到理想的接地电极,能够实现没有组装离散性的IPD型匹配电路。
应该注意,图3所示配置可修改为用接地电感器代替接地电容器。特别是在该修改中,每一个输入侧匹配电路和输出侧匹配电路包括串联连接的电容器和连接在一对平衡线路之间的接地电感器,使得一对平衡型电路接收相位相差180度的信号,连接导线将接地电感器连接在一对平衡型电路之间,并接至虚拟接地点。
图4表示用各自的IPD(12a、12b;15a、15b)构成各频道的匹配电路的比较例,图5表示其输出侧IPD15a、15b的俯视图,图6表示其等效电路图。在图6的比较例中,通过使设置在电感器L1和L2间的连线上的电容器的接地电容成为图3的电容器C1的2倍,作为电路实现与图3相同的电路。在该比较例中,将IPD15a、15b分别设置在各自的平衡型电路上,没有连接两频道间的部分,没有使用图3所示的虚拟电极(VE)。因此,在接地电容2C1、C2、C3的接地(GND)侧,全部用接地用导线16连接在位于IPD基板下部的封装3的接地电极上。
但是,在这样的比较例中,由于将平衡型电路的各频道匹配电路(LC电路)设置在各自的IPD15a、15b上,没有设置连接图6的(a)和(b)两匹配电路的虚拟接地点,从而受接地用导线16的影响。在这样的电路结构中,由于是用L1、L2、L3及2C1、C2来变换阻抗的匹配电路,特别是,受连接在2C1、C2上的接地导线16的长度及形状的离散性的很大影响,半导体装置的RF特性显著地离散。
与此相反,在本实施例1中,如图1~3所示,将平衡型电路的匹配电路设置在一体构成的IPD上,由于将能够连接两匹配电路的虚拟接地点VE用作对RF特性特别敏感的接地点,消除了作为IPD课题的接地电感的离散性。因此,由于不受接地用导线的离散性的影响、用一体结构的IPD构成匹配电路,从而能够实现半导体装置的小型-轻量化、实现低成本化,同时能够降低因部件对位精度引起的RF特性的离散度。
此外,在本实施例1中,如图1~3所示,将一对接地电容C2间的连接点用作虚拟接地点VE(GND),用接地用导线16与接地电极连接,但是从高频特性的观点看,也不见得需要将虚拟接地点连接在接地电极上。但是,由于该虚拟接地电极VE的电位被2个电容器C2以DC方式隔离,在DC方式下成为浮置电位。因此,当因来自外部的静电等供给电荷时,就成为高电位,超过了MIM电容器的耐压,存在达到击穿的问题。为了防止这样的静电击穿,以使电荷逃逸为目的、用导线16将虚拟接地点连接在接地电极上。
在这种情况下,从RF特性的观点看,由于形成虚拟接地点,即使在导线16的长度-形状存在离散性的情况下,对RF特性也没有影响。另一方面,在DC方式下,由于设置接地用导线16,能够使静电等电荷逃逸,具有防止静电击穿的效果。此外,在本实施例中,用导线16将虚拟接地点VE接地,但即使连接在FET的供电电源上、也具有同等的效果。或者,通过大电阻接地或者连接在FET的供电电源上,也具有同等的效果。
此外,在本实施例中,作为放大器是将使用了FET4的放大器的情况作为例示进行说明的,本发明并不限于这种情况,也可以是使用了异质结双极晶体管HBT(Heterojuction Bipolar Transistor)等其他的晶体管的结构。
实施例2
以下,参照图7及图8,说明本发明的实施例2。图7是表示本发明实施例2的半导体装置输出侧IPD的俯视图,图8是表示其等效电路图。在实施例1中,用串联的L1、L2、L3与接地电容C1、C2构成匹配电路,在本实施例2中,用串联的电容器C4与接地电感器L5构成匹配电路,电感器L5连接在两频道匹配电路之间。
在图7及图8所示的结构中,由于使用上部电路与下部电路的相位相差180度的平衡型电路,连接两匹配电路的电感器L5的中点成为虚拟接地点,以L5的一半的电感接地那样地工作。因此,在高频段成为理想的接地,由于不使用接地导线16、将接地电路在IPD上形成,能够消除作为IPD课题的接地电感的离散性。
另外,用IPD能够使半导体装置的匹配电路小型-轻量化、降低成本,同时能够降低因部件的对位精度引起的RF特性的离散度。
此外,在本实施例的电路结构中,电感器L5部分用MIM电容器13(C4)以DC方式隔离、在DC方式下成为浮置电位,我们认为这是不适当的。为了防止产生这种情况,设置数MΩ的大电阻30,连接在FET的供电电源上。由于该电阻30是大电阻,对RF特性没有影响,但对防止DC方式的静电击穿是有效的。
实施例3
以下,参照图9至图11说明本发明的实施例3。图9是本发明实施例3的半导体装置的俯视图,图10是其输出侧内置平衡-不平衡变换器的IPD的俯视图,图11是表示图10所示的等效电路图的图。
在本实施例3中,在图9至图11中,20是输入侧内置平衡-不平衡变换器的IPD,21是输出侧内置平衡-不平衡变换器的IPD,在输入侧及输出侧,采用将平衡-不平衡变换器2分别包含在IPD20及IPD21中的结构。
这样,通过将平衡-不平衡变换器2在IPD内的基板上形成,与实施例1的情况相比,更能够使半导体装置小型-轻量化、低成本化。另外,用上述结构没有必要在PCB基板上直接设置平衡-不平衡变换器和匹配电路,只要将这些平衡-不平衡变换器和匹配电路等的元件安装在封装3上的半导体装置安装在PCB基板1上即可。因此,能够削减部件数目,也能够降低安装成本。进而,即使在安装在封装内的半导体装置中,由于能够不通过导线而直接用IPD基板上的布线与平衡型匹配电路和平衡-不平衡变换器2连接,也具有能够消除因导线的离散性引起的两电路之间的相位离散性的效果。
另外,为了防止虚拟接地点在DC方式下成为浮置电位,与实施例2的情况同样,虚拟接地点通过数MΩ的大电阻30与FET的漏极侧供电布线连接,连接在FET的供电电源上。
此外,在本实施例中,采用了内置平衡-不平衡变换器的IPD的电路结构,但是本发明并不限于这种情况,BTL电路和混合电路等、只要是将从1个输入产生的两电路的相位偏离180度的电路,是能够在IPD基板上形成为单片的电路,就能够使用任何一种这样的电路。
实施例4
以下,参照图12及图13说明本发明的实施例4。图12是表示本发明实施例4的半导体装置的俯视图,图13是表示其相邻的IPD部分的放大俯视图。本实施例4的特征在于:将多个平衡型电路的IPD20、21并联连接合成。
如图12所示,参考符号17、18表示用各个平衡-不平衡变换器所分配的信号的相位为0度的信号及180度的信号供电的信号分量,19、19′是分别设置在输入侧及输出侧的电功率分配电路及电功率合成电路。用该输入侧功率分配电路19分配输入功率,供电给各自的输入侧内置平衡-不平衡变换器的IPD20,并被FET4放大。放大了的供电信号(17、18)通过各自的输出侧内置平衡-不平衡变换器的IPD21,供电给输出侧功率合成电路19′,使其合成。
通过将多个这些平衡型电路的IPD20、21并联连接进行合成,由于能够减小各FET的大小、功率,从而能够提高FET的阻抗、降低输入输出侧的阻抗匹配电路的阻抗变换比,能够降低匹配电路的损耗。另外,各IPD的RF功率也减小,能够用微细的L、C、R构成匹配电路,能够减小IPD。
在图13中,被MIM电容器夹持的虚拟接地点,用大电阻30与漏极侧供电布线连接,使之在DC方式下不成为浮置状态,防止静电击穿。另外,漏极侧的供电全部用漏极偏置用导线32连接,从半导体装置的两侧供电。
对邻接的IPD之间,从各信号线路通过电阻31和导线11与邻接的IPD的同相信号线路连接,本来,由于两信号线路是同相信号,两信号电路的电位相同,在电阻31上没有电流流动。但是,由于在所谓的奇模式发生的情况下,成为反相,在电阻31上流过电流,具有使反相信号衰减的效果。由于这种效应,能够抑制成为寄生振荡的奇模式,得到难于振荡、稳定的半导体装置。
另外,在本实施例的半导体装置中,由于各FET组的每一组均为推挽结构,与仅仅并联合成的情况相比,也具有抑制在FET中产生的畸变分量的效果。进而,由于将IPD用于FET4的输入输出部,在能够使半导体装置小型-轻量化,降低成本的同时,能够降低因部件的对位精度引起的RF特性离散度。
发明的效果
如上所述,根据本发明,通过在各IPD上设置一对平衡型电路结构的匹配电路,将能够连接两匹配电路的虚拟接地点用作对RF特性敏感的接地点,由于消除了接地电感的离散性,能够不受接地用导线离散性的影响,在IPD内构成匹配电路,从而在能够使半导体装置实现小型-轻量化、低成本化的同时,能够降低因部件的对位精度引起的RF特性的离散度。
Claims (10)
1、一种半导体装置,在输入匹配电路与输出匹配电路之间连接放大器用半导体芯片(4),以上述输入匹配电路接收相位相差180度的2个信号分量,并且由上述放大器用半导体芯片(4)放大,其特征在于:
上述输入匹配电路与上述输出匹配电路分别具有在高频无源元件上设置的一对平衡型电路,
上述各匹配电路,在包含串联连接的电容器时,在上述一对平衡型电路之间设置单一的接地电容器或一对互相连接的接地电容器,而且将上述单一的接地电容器的中心部或上述一对连接的接地电容器之间的连线部分作为虚拟接地点,
上述各匹配电路,在包含串联连接的电感器时,在上述一对平衡型电路之间设置单一的接地电感器或一对互相连接的接地电感器,而且将上述单一的接地电感器的中心部或上述一对互相连接的接地电感器之间的连线部分作为虚拟接地点。
2、如权利要求1所述的半导体装置,其特征在于:
上述输入匹配电路及输出匹配电路分别包含在上述一对平衡型电路之间串联连接的一对接地电容器和包含于各平衡型电路之中并且串联连接的电感器,将串联连接在上述一对平衡型电路之间的一对接地电容器连接的连线被连接在虚拟接地点上。
3、如权利要求1所述的半导体装置,其特征在于:
上述输入匹配电路及输出匹配电路分别包含在上述一对平衡型电路之间串联连接的一对接地电感器和包含于各平衡型电路之中并且串联连接的电容器,将串联连接在上述一对平衡型电路之间的一对接地电感器连接的连线被连接在虚拟接地点上。
4、如权利要求1所述的半导体装置,其特征在于:
还具有从平衡型电路向不平衡型电路变换用的输入侧平衡-不平衡变换器和进行其相反变换用的输出侧平衡-不平衡变换器,输入信号被上述输入侧平衡-不平衡变换器分割成相位相差180度的2个信号分量并以上述输入匹配电路接收,用上述半导体芯片放大后,被上述输出侧平衡-不平衡变换器合成。
5、如权利要求1所述的半导体装置,其特征在于:
在上述各匹配电路中内置混合电路,构成从1个输入通过该混合电路分割的平衡型匹配电路。
6、如权利要求1所述的半导体装置,其特征在于:
将上述各匹配电路和上述半导体芯片容纳在1个封装内。
7、如权利要求1所述的半导体装置,其特征在于:
将多个上述平衡型电路并联合成。
8、如权利要求7所述的半导体装置,其特征在于:
排列上述多个平衡型电路,使其各邻接的平衡型电路的信号相位相同,通过电阻器连接在该邻接的平衡型电路的信号线之间。
9、如权利要求2所述的半导体装置,其特征在于:
将连接上述一对平衡型电路之间的串联连接的上述一对接地电容器连接的连线,作为虚拟接地点,通过电阻器连接该虚拟接地点和接地电极或供电电源。
10.如权利要求3所述的半导体装置,其特征在于:
将连接上述一对平衡型电路之间的串联连接的上述一对接地电感器连接的连线,作为虚拟接地点,通过电阻器连接该虚拟接地点和接地电极或供电电源。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003069600A JP4012840B2 (ja) | 2003-03-14 | 2003-03-14 | 半導体装置 |
JP69600/2003 | 2003-03-14 | ||
JP69600/03 | 2003-03-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1531194A CN1531194A (zh) | 2004-09-22 |
CN1287514C true CN1287514C (zh) | 2006-11-29 |
Family
ID=32959390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100287351A Expired - Lifetime CN1287514C (zh) | 2003-03-14 | 2004-03-12 | 半导体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7061329B2 (zh) |
JP (1) | JP4012840B2 (zh) |
CN (1) | CN1287514C (zh) |
DE (1) | DE102004011719B4 (zh) |
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US7576607B2 (en) * | 2008-01-03 | 2009-08-18 | Samsung Electro-Mechanics | Multi-segment primary and multi-turn secondary transformer for power amplifier systems |
US7812701B2 (en) | 2008-01-08 | 2010-10-12 | Samsung Electro-Mechanics | Compact multiple transformers |
US8044759B2 (en) * | 2008-01-08 | 2011-10-25 | Samsung Electro-Mechanics | Overlapping compact multiple transformers |
US7675366B2 (en) * | 2008-03-18 | 2010-03-09 | Infineon Technologies Ag | Integrated amplifier circuit |
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US8030763B2 (en) * | 2008-06-26 | 2011-10-04 | Freescale Semiconductor, Inc. | Semiconductor package with reduced inductive coupling between adjacent bondwire arrays |
JP5578797B2 (ja) * | 2009-03-13 | 2014-08-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
GB2471498A (en) * | 2009-07-01 | 2011-01-05 | Thales Holdings Uk Plc | A microwave push-pull amplifier using broadband hybrid stripline couplers |
JP5631607B2 (ja) * | 2009-08-21 | 2014-11-26 | 株式会社東芝 | マルチチップモジュール構造を有する高周波回路 |
JP2011171697A (ja) * | 2010-01-22 | 2011-09-01 | Toshiba Corp | 高周波半導体装置 |
US8125276B2 (en) * | 2010-03-12 | 2012-02-28 | Samsung Electro-Mechanics | Sharing of inductor interstage matching in parallel amplification system for wireless communication systems |
CN102055414A (zh) * | 2010-04-14 | 2011-05-11 | 锐迪科创微电子(北京)有限公司 | 射频功率放大器模块及移动通信终端 |
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JP6171427B2 (ja) * | 2013-03-13 | 2017-08-02 | 三菱電機株式会社 | 高周波電力増幅器 |
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-
2003
- 2003-03-14 JP JP2003069600A patent/JP4012840B2/ja not_active Expired - Lifetime
-
2004
- 2004-03-05 US US10/792,856 patent/US7061329B2/en not_active Expired - Lifetime
- 2004-03-10 DE DE200410011719 patent/DE102004011719B4/de not_active Expired - Fee Related
- 2004-03-12 CN CNB2004100287351A patent/CN1287514C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2004281625A (ja) | 2004-10-07 |
DE102004011719A1 (de) | 2004-12-09 |
US20040178854A1 (en) | 2004-09-16 |
JP4012840B2 (ja) | 2007-11-21 |
DE102004011719B4 (de) | 2008-12-24 |
CN1531194A (zh) | 2004-09-22 |
US7061329B2 (en) | 2006-06-13 |
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