CN109286406B - high-speed data transmission receiving device - Google Patents
high-speed data transmission receiving device Download PDFInfo
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- CN109286406B CN109286406B CN201811205121.4A CN201811205121A CN109286406B CN 109286406 B CN109286406 B CN 109286406B CN 201811205121 A CN201811205121 A CN 201811205121A CN 109286406 B CN109286406 B CN 109286406B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
- H04B1/0017—Digital filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0032—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage with analogue quadrature frequency conversion to and from the baseband
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/12—Neutralising, balancing, or compensation arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention provides a high-speed data transmission receiving device, comprising: the input end of the down-conversion plate is electrically connected with an external receiving antenna through an SMA interface and is used for receiving and processing an X-waveband radio-frequency signal of the external receiving antenna to generate an intermediate-frequency signal with fixed frequency; the input end of the baseband board is electrically connected with the output end of the down-conversion board, and the output end of the baseband board is electrically connected with the PC end; wherein the base band plate includes: the analog radio frequency front end is electrically connected with the down-conversion board and is used for receiving the intermediate frequency signal and converting the intermediate frequency signal into a baseband signal; and the baseband receiving module is electrically connected with the analog radio frequency front end. The high-speed data transmission receiving device supports the demodulation of various systems, can realize the reliable butt joint of input signals with various amplitudes, can effectively improve the sampling frequency locking efficiency of the system, and can better meet the requirements of high-speed data conversion and acquisition of the high-speed data transmission system.
Description
Technical Field
the invention relates to the technical field of high-speed data transmission among satellites, in particular to a high-speed data transmission receiving device
background
at present, important national economic departments such as meteorological, oceanic and national soil resource surveying and mapping survey and the like bring spatial data sources into a main business application system, continuous business requirements are provided for the spatial high-speed data transmission technology, high-speed data transmission effective loads are increasingly widely and deeply applied, and various effective loads have increasingly higher requirements on data transmission rate, transmission quality and the like. In recent years, technologies such as a high-speed modulation and demodulation technology, a high-efficiency coding and decoding technology, a very long baseline measurement technology and the like are developed rapidly, and the new technologies have no requirements and limitations on transmitted data contents, so that the method can be widely applied to various fields such as weather, oceans, resources, environments, communication, reconnaissance and the like, provides a transmission link for high-speed data generated by various satellite-borne payloads, and realizes the acquisition of high-speed information. At present, the foreign satellite-ground high-speed data transmission bandwidth reaches Gbps magnitude, the domestic high-speed data transmission bandwidth also reaches hundreds of Mbps magnitude, the foreseeable demand for high-code-rate data transmission in the coming years can continuously and rapidly increase, the application field is continuously expanded, the code rate is more than 600Mbps, and the demand of a high-speed data transmission receiver which can adapt to various modulation modes is particularly urgent.
Disclosure of Invention
the invention provides a high-speed data transmission receiving device, which aims to solve the problems that the signal receiving dynamic range of a high-speed data transmission receiver is narrow, the receiving end is difficult to identify the signal receiving, and the code rate is low, so that the requirement of a communication system for rapidly increasing the high-code-rate data transmission rate cannot be met.
In order to achieve the above object, an embodiment of the present invention provides a high-speed data transmission receiving apparatus, including:
The input end of the down-conversion plate is electrically connected with an external receiving antenna through an SMA interface and is used for receiving and processing an X-waveband radio-frequency signal of the external receiving antenna to generate an intermediate-frequency signal with fixed frequency;
the input end of the baseband board is electrically connected with the output end of the down-conversion board, and the output end of the baseband board is electrically connected with the PC end; wherein the base band plate includes:
the analog radio frequency front end is electrically connected with the down-conversion board and is used for receiving the intermediate frequency signal and converting the intermediate frequency signal into a baseband signal;
the analog radio frequency front end comprises:
the input end of the first digital-to-analog converter is electrically connected with the output end of the first digital frequency synthesizer and is used for receiving a high-dynamic orthogonal single carrier signal sent by the first digital frequency synthesizer and converting the high-dynamic orthogonal single carrier signal into an analog signal;
a first input end of the second quadrature modulator is electrically connected with an output end of the first digital-to-analog converter, a second input end of the second quadrature modulator is electrically connected with an output end of a second phase-locked loop, an output end of the second quadrature modulator is electrically connected with a high-speed dual-channel analog-to-digital converter, and the second quadrature modulator is used for receiving an analog signal sent by the first digital-to-analog converter and a high-frequency high-precision carrier signal sent by the second phase-locked loop, performing quadrature modulation on the analog signal and the carrier signal, generating a frequency meeting precision and speed requirements, and sending the frequency to the high-speed dual-channel analog-to-digital converter;
The input end of the second digital-to-analog converter is electrically connected with the output end of the second digital frequency synthesizer and is used for receiving a high-dynamic orthogonal single carrier signal sent by the second digital frequency synthesizer and converting the high-dynamic orthogonal single carrier signal into an analog signal;
A first input end of the third quadrature modulator is connected with an output end of the second digital-to-analog converter, a second input end of the third quadrature modulator is electrically connected with an output end of the first phase-locked loop, and an output end of the third quadrature modulator is electrically connected with a clock input end of the first quadrature modulator, and the third quadrature modulator is used for receiving an analog signal sent by the second digital-to-analog converter and a high-frequency high-precision carrier signal sent by the first phase-locked loop, performing quadrature modulation on the analog signal and the carrier signal, generating a frequency meeting precision and speed requirements, and sending the frequency to the first quadrature modulator;
The baseband receiving module is electrically connected with the analog radio frequency front end and used for receiving the baseband signal and demodulating and decoding the baseband signal;
And the first communication module is electrically connected with the baseband receiving module and used for receiving the demodulated and decoded baseband signal and sending the demodulated and decoded baseband signal to the PC terminal.
wherein the down conversion plate includes:
the input end of the amplitude limiter is electrically connected with an external receiving antenna through an SMA interface and is used for receiving the radio-frequency signal sent by the external receiving antenna and carrying out amplitude limiting processing on the radio-frequency signal;
The input end of the radio frequency band-pass filter is electrically connected with the output end of the amplitude limiter;
The input end of the low-noise amplifier is electrically connected with the output end of the radio frequency band-pass filter and is used for performing power amplification processing on the radio frequency signal;
the input end of the mixer is electrically connected with the output end of the low-noise amplifier;
the input end of the first intermediate frequency band-pass filter is electrically connected with the output end of the mixer;
The input end of the automatic gain control amplifier is electrically connected with the output end of the first intermediate frequency band-pass filter;
And the input end of the second intermediate frequency band-pass filter is electrically connected with the output end of the automatic gain control amplifier.
wherein the down conversion plate further comprises:
the input end of the second communication module is electrically connected with the first communication module, and the output end of the second communication module is electrically connected with the automatic gain control amplifier;
and the local oscillator is electrically connected with the second communication module, generates a required clock signal under the control of the second communication module, and has a clock input end electrically connected with the first temperature compensation crystal oscillator and an output end electrically connected with the second input end of the frequency mixer.
Wherein the analog radio frequency front end comprises:
a first input end of the numerical control attenuator is electrically connected with an output end of the second intermediate frequency band-pass filter;
the input end of the amplifier is electrically connected with the output end of the numerical control attenuator;
a first band pass filter, an input of the first band pass filter being electrically connected to an output of the amplifier;
The input end of the first quadrature demodulator is electrically connected with the output end of the first band-pass filter, and the output end of the first quadrature demodulator is respectively electrically connected with the second band-pass filter and the third band-pass filter, and is used for converting the analog signal filtered by the first band-pass filter into two paths of orthogonal I, Q signals;
and the first input end of the high-speed dual-channel analog-to-digital converter is respectively electrically connected with the second band-pass filter and the third band-pass filter and is used for receiving analog signals filtered by the second band-pass filter and the third band-pass filter.
Wherein, the analog radio frequency front end further comprises:
and a first output end of the second temperature compensation crystal oscillator is respectively and electrically connected with a clock input end of the first phase-locked loop and a clock input end of the second phase-locked loop and is used for providing a clock source for the first phase-locked loop and the second phase-locked loop.
wherein the baseband receiving module comprises:
The input end of the sampling data sorting unit is electrically connected with the output end of the high-speed double-channel analog-to-digital converter and is used for receiving a digital signal sent by the high-speed double-channel analog-to-digital converter;
The input end of the carrier synchronization unit is electrically connected with the output end of the sampling data sorting unit;
the input end of the bit synchronization unit is electrically connected with the output end of the carrier synchronization unit, and the first output end of the bit synchronization unit is electrically connected with the first digital frequency synthesizer and the second digital frequency synthesizer respectively;
the input end of the demodulation unit is electrically connected with the second output end of the bit synchronization unit;
and the input end of the decoding unit is electrically connected with the output end of the demodulation unit, and the output end of the decoding unit is electrically connected with the first communication module.
Wherein the baseband receiving module further comprises:
and the output end of the SPI control unit is respectively electrically connected with the SPI input end of the first phase-locked loop and the SPI input end of the second phase-locked loop and used for enabling the first phase-locked loop and the second phase-locked loop to generate carrier signals with fixed frequency and high precision.
wherein, the analog radio frequency front end further comprises:
the input end of the first digital-to-analog converter is electrically connected with the output end of the first digital frequency synthesizer and is used for receiving a high-dynamic orthogonal single carrier signal sent by the first digital frequency synthesizer and converting the high-dynamic orthogonal single carrier signal into an analog signal;
A first input end of the second quadrature modulator is electrically connected with an output end of the first digital-to-analog converter, a second input end of the second quadrature modulator is electrically connected with an output end of the second phase-locked loop, an output end of the second quadrature modulator is electrically connected with the high-speed dual-channel analog-to-digital converter, and the second quadrature modulator is used for receiving an analog signal sent by the first digital-to-analog converter and a high-frequency high-precision carrier signal sent by the second phase-locked loop, performing quadrature modulation on the analog signal and the carrier signal, generating a frequency meeting precision and speed requirements, and sending the frequency to the high-speed dual-channel analog-to-digital converter;
the input end of the second digital-to-analog converter is electrically connected with the output end of the second digital frequency synthesizer and is used for receiving a high-dynamic orthogonal single carrier signal sent by the second digital frequency synthesizer and converting the high-dynamic orthogonal single carrier signal into an analog signal;
and a third quadrature modulator, a first input end of the third quadrature modulator being connected to an output end of the second digital-to-analog converter, a second input end of the third quadrature modulator being electrically connected to an output end of the first phase-locked loop, an output end of the third quadrature modulator being electrically connected to a clock input end of the first quadrature modulator, and configured to receive an analog signal sent by the second digital-to-analog converter and a high-frequency and high-precision carrier signal sent by the first phase-locked loop, perform quadrature modulation on the analog signal and the carrier signal, generate a frequency meeting precision and speed requirements, and send the frequency to the first quadrature modulator.
And the second input end of the numerical control attenuator is electrically connected with the baseband receiving module.
the scheme of the invention has the following beneficial effects:
the high-speed data transmission receiving device of the embodiment of the invention realizes the modulation modes of BPSK/SQPSK/QPSK/UQPSK/8PSK/16QAM and the like based on the FPGA software radio technology, adopts the software radio technology to realize on a digital domain, can conveniently realize the carrier synchronization, the bit synchronization and the frame synchronization of various systems, calculates the carrier error and the bit synchronization error according to different systems in the FPGA, and can realize closed-loop self-calibration by controlling the clock frequency of the PLL to realize the carrier and bit synchronization; the FPGA is adopted to automatically adjust the gain according to the amplitude of the signal acquired by the ADC, so that the dynamic range of-50 dBm to 0dBm can be realized, and the reliable butt joint of input signals with various amplitudes can be realized; by adopting the DDS, DAC and PLL closed-loop control method, the DSS has shorter frequency locking time and is combined with the PLL with longer frequency locking time, so that the sampling frequency locking efficiency of the system can be effectively improved, and the requirements of high-speed data conversion and acquisition of the high-speed data transmission system can be better met.
drawings
FIG. 1 is a schematic structural diagram of the present invention.
[ description of reference ]
1-a limiter; 2-a radio frequency band pass filter; 3-a low noise amplifier; a 4-mixer; 5-a first intermediate frequency band-pass filter; 6-automatic gain control amplifier; 7-a second intermediate frequency band-pass filter; 8-a first temperature compensated crystal oscillator; 9-local oscillation; 10-a second communication module; 11-analog radio frequency front end; 12-a digitally controlled attenuator; 13-an amplifier; 14-a first band pass filter; 15-a first quadrature modulator; 16-a second band-pass filter; 17-a third band-pass filter; 18-high speed dual channel analog to digital converter; 19-a sample data sorting unit; 20-a carrier synchronization unit; a 21-bit synchronization unit; 22-a demodulation unit; 23-a decoding unit; 24-a first communication module; 25-a first digital frequency synthesizer; 26-SPI control unit; 27-a first digital-to-analog converter; 28-a second quadrature modulator; 29-a second phase locked loop; 30-a first phase-locked loop; 31-a first temperature compensated crystal oscillator; 32-a second digital frequency synthesizer; 33-a second digital-to-analog converter; 34-third quadrature modulator.
Detailed Description
in order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
the invention provides a high-speed data transmission receiving device aiming at the problems that the signal receiving dynamic range of the existing high-speed data transmission receiver is narrow, the signal receiving identification of a receiving end is difficult, the code rate is low, and the rapid increase requirement of a communication system on the high-code-rate data transmission rate cannot be met.
As shown in fig. 1, an embodiment of the present invention provides a high-speed data transmission receiving apparatus, including: the input end of the down-conversion plate is electrically connected with an external receiving antenna through an SMA interface and is used for receiving and processing an X-waveband radio-frequency signal of the external receiving antenna to generate an intermediate-frequency signal with fixed frequency; the input end of the baseband board is electrically connected with the output end of the down-conversion board, and the output end of the baseband board is electrically connected with the PC end; wherein the base band plate includes: the analog radio frequency front end 11 is electrically connected with the down-conversion board and is used for receiving the intermediate frequency signal and converting the intermediate frequency signal into a baseband signal; the baseband receiving module is electrically connected with the analog radio frequency front end 11 and is used for receiving the baseband signal and demodulating and decoding the baseband signal; and the first communication module 24 is electrically connected with the baseband receiving module, and is configured to receive the demodulated and decoded baseband signal and send the demodulated and decoded baseband signal to the PC terminal.
the high-speed data transmission receiving device of the embodiment of the invention realizes the modulation modes of BPSK/SQPSK/QPSK/UQPSK/8PSK/16QAM and the like based on the FPGA software radio technology, adopts the software radio technology to realize on a digital domain, can conveniently realize the carrier synchronization, the bit synchronization and the frame synchronization of various systems, calculates the carrier error and the bit synchronization error according to different systems in the FPGA, and can realize closed-loop self-calibration by controlling the clock frequency of the PLL to realize the carrier and bit synchronization; the 2-stage automatic gain control amplifier 6 is adopted, the FPGA carries out automatic gain adjustment according to the amplitude of the signal acquired by the ADC, the dynamic range of-50 dBm to 0dBm can be realized, and the reliable butt joint of input signals with various amplitudes can be realized; by adopting the DDS, DAC and PLL closed-loop control method, the DSS has shorter frequency locking time and is combined with the PLL with longer frequency locking time, so that the sampling frequency locking efficiency of the system can be effectively improved, and the requirements of high-speed data conversion and acquisition of the high-speed data transmission system can be better met.
wherein the down conversion plate includes: the amplitude limiter 1 is characterized in that the input end of the amplitude limiter 1 is electrically connected with an external receiving antenna through an SMA interface and is used for receiving a radio frequency signal sent by the external receiving antenna and carrying out amplitude limiting processing on the radio frequency signal; the input end of the radio frequency band-pass filter 2 is electrically connected with the output end of the amplitude limiter 1; the input end of the low-noise amplifier 3 is electrically connected with the output end of the radio frequency band-pass filter 2 and is used for performing power amplification processing on the radio frequency signal; a mixer 4, wherein the input end of the mixer 4 is electrically connected with the output end of the low noise amplifier 3; a first intermediate frequency band-pass filter 5, wherein the input end of the first intermediate frequency band-pass filter 5 is electrically connected with the output end of the mixer 4; an input end of the automatic gain control amplifier 6 is electrically connected with an output end of the first intermediate frequency band-pass filter 5; and the input end of the second intermediate frequency band-pass filter 7 is electrically connected with the output end of the automatic gain control amplifier 6.
Wherein the down conversion plate further comprises: a second communication module 10, an input end of the second communication module 10 is electrically connected with the first communication module 24, and an output end of the second communication module 10 is electrically connected with the automatic gain control amplifier 6; the local oscillator 9 is electrically connected with the second communication module 10, generates a required clock signal under the control of the second communication module 10, a clock input end of the local oscillator 9 is electrically connected with the first temperature compensation crystal oscillator 8, and an output end of the local oscillator 9 is electrically connected with a second input end of the frequency mixer 4.
After receiving an X-band radio frequency signal from an external receiving antenna, the down conversion board according to the embodiment of the present invention performs radio frequency filtering on the radio frequency signal through a radio frequency filter, amplifies the radio frequency signal by the low noise amplifier 3, and then sends the amplified radio frequency signal to the input end of the mixer 4, and after mixing the amplified radio frequency signal with an output signal of the local oscillator 9 configured by the FPGA, outputs an intermediate frequency signal with a certain fixed frequency, taking the radio frequency signal frequency as 8GHz and the intermediate frequency as 720MHz as examples, in order to obtain the 720MHz output frequency, the output frequency of the local oscillator 9 should be configured as 7.28GHz through the second communication module 10 interface, so that the input radio frequency signal can be converted into the 720MHz intermediate frequency signal, and in order to achieve a wide dynamic range of the signal; the high-speed data transmission receiving device adopts a 2-level automatic gain control technology, an automatic gain control amplifier 6 is adopted on a down-conversion board to carry out first-level gain adjustment, gain control of 720MHz intermediate-frequency signals after down-conversion is realized under the control of internal logic of an FPGA, signals entering a second-level numerical control attenuator 12 are ensured to be within a reasonable range, and the two-level automatic gain control technology is adopted, so that each level of automatic gain control can be ensured to be in an optimal linear amplification working state, and a receiving system can be ensured to have a wide dynamic range.
Wherein, the analog rf front end 11 includes: a first input end of the numerical control attenuator 12 is electrically connected with an output end of the second intermediate frequency band-pass filter 7; the input end of the amplifier 13 is electrically connected with the output end of the numerical control attenuator 12; a first band-pass filter 14, an input of the first band-pass filter 14 being electrically connected to an output of the amplifier 13; a first quadrature demodulator, an input end of which is electrically connected to an output end of the first band-pass filter 14, and output ends of which are electrically connected to the second band-pass filter 16 and the third band-pass filter 17, respectively, for converting the analog signal filtered by the first band-pass filter 14 into two paths of orthogonal I, Q signals; and a first input end of the high-speed dual-channel analog-to-digital converter 18 is electrically connected with the second band-pass filter 16 and the third band-pass filter 17 respectively, and is used for receiving the analog signals filtered by the second band-pass filter 16 and the third band-pass filter 17.
The analog radio frequency front end 11 according to the above embodiment of the present invention receives an intermediate frequency signal that is filtered by the automatic gain control amplifier 6 and an intermediate frequency, inputs the intermediate frequency signal to the second-stage digital control attenuator 12, amplifies the intermediate frequency signal according to an initial amplification factor configured by the FPGA, and then sends the intermediate frequency signal to the first quadrature demodulator after being filtered by the low noise amplifier 13 and the first band pass filter 14, and the intermediate frequency signal is stripped by the quadrature demodulator, the second band pass filter 16 and the third band pass filter 17 to obtain a baseband signal waveform; wherein the second band-pass filter 16 and the third band-pass filter 17 are low-pass filters.
Wherein, the analog rf front end 11 further includes: a second temperature compensated crystal oscillator 31, a first output end of the second temperature compensated crystal oscillator 31 is electrically connected to a clock input end of the first phase-locked loop 30 and a clock input end of the second phase-locked loop 29, respectively, and is configured to provide a clock source for the first phase-locked loop 30 and the second phase-locked loop 29.
the analog radio frequency front end 11 according to the above embodiment of the present invention converts the intermediate frequency signal into a baseband signal under the control of the local oscillator 9 signal output by the phase-locked loop, and sends the baseband signal to the high-speed dual-channel analog-to-digital converter 18, and the baseband receiving module sorts the sampling data and automatically adjusts the gain setting value of the digital control attenuator 12 according to the condition that the signal is received by the high-speed dual-channel analog-to-digital converter 18, so as to ensure the validity of the acquired signal.
wherein the baseband receiving module comprises: the input end of the sampling data sorting unit 19 is electrically connected with the output end of the high-speed double-channel analog-to-digital converter 18 and is used for receiving the digital signal sent by the high-speed double-channel analog-to-digital converter 18; the input end of the carrier synchronization unit 20 is electrically connected with the output end of the sampling data sorting unit 19; a bit synchronization unit 21, an input terminal of the bit synchronization unit 21 being electrically connected to an output terminal of the carrier synchronization unit 20, and a first output terminal of the bit synchronization unit 21 being electrically connected to the first digital frequency synthesizer 25 and the second digital frequency synthesizer 32, respectively; a demodulation unit 22, an input end of the demodulation unit 22 is electrically connected with a second output end of the bit synchronization unit 21; an input end of the decoding unit 23 is electrically connected to an output end of the demodulating unit 22, and an output end of the decoding unit 23 is electrically connected to the first communication module 24.
wherein the baseband receiving module further comprises: an SPI control unit 26, an output end of the SPI control unit 26 is electrically connected to an SPI input end of the first phase-locked loop 30 and an SPI input end of the second phase-locked loop 29, respectively, for enabling the first phase-locked loop 30 and the second phase-locked loop 29 to generate high-frequency and high-precision carrier signals with fixed frequency.
Wherein, the analog rf front end 11 further includes: a first digital-to-analog converter 27, an input end of the first digital-to-analog converter 27 is electrically connected to an output end of the first digital frequency synthesizer 25, and is configured to receive a high dynamic orthogonal single carrier signal sent by the first digital frequency synthesizer 25 and convert the high dynamic orthogonal single carrier signal into an analog signal; a second quadrature modulator 28, a first input end of the second quadrature modulator 28 is electrically connected to the output end of the first digital-to-analog converter 27, a second input end of the second quadrature modulator 28 is electrically connected to the output end of the second phase-locked loop 29, and an output end of the second quadrature modulator 28 is electrically connected to the high-speed dual-channel analog-to-digital converter 18, and is configured to receive the analog signal sent by the first digital-to-analog converter 27 and the carrier signal sent by the second phase-locked loop 29 with high frequency and high precision, perform quadrature modulation on the analog signal and the carrier signal, generate a frequency meeting precision and speed requirements, and send the frequency to the high-speed dual-channel analog-to-digital converter 18; a second digital-to-analog converter 33, an input end of the second digital-to-analog converter 33 is electrically connected to an output end of the second digital frequency synthesizer, and is configured to receive a high dynamic orthogonal single carrier signal sent by the second digital frequency synthesizer 32 and convert the high dynamic orthogonal single carrier signal into an analog signal; a third quadrature modulator 34, a first input end of the third quadrature modulator 34 is connected to an output end of the second digital-to-analog converter 33, a second input end of the third quadrature modulator 34 is electrically connected to an output end of the first phase-locked loop 30, an output end of the third quadrature modulator 34 is electrically connected to a clock input end of the first quadrature modulator 15, and the third quadrature modulator is configured to receive an analog signal sent by the second digital-to-analog converter 33 and a high-frequency and high-precision carrier signal sent by the first phase-locked loop 30, perform quadrature modulation on the analog signal and the carrier signal, generate a frequency meeting precision and speed requirements, and send the frequency to the first quadrature modulator 15.
And a second input end of the digital control attenuator 12 is electrically connected with the baseband receiving module.
The baseband receiving module according to the above embodiment of the present invention outputs a local oscillator 9 signal of a certain frequency under the control of the SPI control unit 26, the first digital-to-analog converter 27 generates an adjustable clock signal according to the output signal of the bit synchronization module, the digital signal is converted into a digital signal by the second quadrature modulator 28, and then quadrature-modulated with the clock signal output by the first phase-locked loop 30 to generate a high-speed ADC sampling clock signal, and according to the Nyquist sampling theorem, when the signal sampling frequency output by the quadrature modulator satisfies Fs ≥ 2Fb (Fb-ADC input signal bandwidth), the high-speed dual-channel analog-to-digital converter 18 can be effectively performed.
In the above embodiment of the present invention, the high-speed dual-channel analog-to-digital converter 18 has two channels, the highest supports 3.0GSPS (dual channel) sampling, the quantization Bit width is 8 bits, supports the SPI serial control interface, and can select the DDR clock mode and adopt the way of expanding the data Bit width to achieve that 4 sampling points are output at the same time by each clock under the condition of maximally reducing the LVDS line pair rate, the supported code rate of the present invention is 5Mbps to 600Mbps, the maximum code rate of I, Q two signals passing through the broadband high-speed quadrature demodulator is 600Mbps, the highest sampling rate of the ADC is 1.2GSPS, and the precision of the high-speed ADC is 8 Bit. I, Q the total bandwidth of the data after high-speed sampling for the two-channel data is: 1.2G × 8 × 2 ═ 19.2 Gbps. When the data volume with high bandwidth is accessed to the FPGA, the LVDS interface is adopted for inputting: the output of ADC sampling data is divided into I, Q two channels to be output simultaneously in parallel, each channel adopts a mode of expanding an LVDS line pair, the output bit width of each channel is expanded into 16 pairs of LVDS, namely each clock edge can output 2 sampling points (because one sampling point is 8 bits), in order to further reduce the frequency of a channel associated clock and improve the feasibility of accessing an FPGA, the ADC can be set to adopt a double edge clock DDR mode, the ADC data is effective on the double edges of the channel associated clock (equivalent to outputting 4 sampling points in one clock period), and at the moment, the frequency of the channel associated clock can be reduced to 1/4 of the sampling clock. Thus, for samples up to 1.2GSPS, the associated clock for the ADC data output is 300 MHz.
the high-speed data transmission receiving device according to the above-mentioned embodiment of the present invention implements BPSK/SQPSK/QPSK/UQPSK/8PSK/16QAM modulation schemes based on the FPGA software radio technology, and implements the BPSK/SQPSK/QPSK/UQPSK/8PSK/16QAM modulation schemes in the digital domain by using the software radio technology, so that it is more convenient to implement carrier synchronization, bit synchronization, and frame synchronization of multiple systems, and calculate carrier error and bit synchronization error according to different systems inside the FPGA, and implement closed-loop self-calibration by controlling the clock frequency of the PLL, thereby implementing carrier and bit synchronization; the 2-stage automatic gain control amplifier 6 is adopted, the FPGA carries out automatic gain adjustment according to the amplitude of the signal acquired by the ADC, the dynamic range of-50 dBm to 0dBm can be realized, and the reliable butt joint of input signals with various amplitudes can be realized; by adopting the DDS, DAC and PLL closed-loop control method, the DSS has shorter frequency locking time and is combined with the PLL with longer frequency locking time, so that the sampling frequency locking efficiency of the system can be effectively improved, and the requirements of high-speed data conversion and acquisition of the high-speed data transmission system can be better met.
while the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. a high-speed data transmission/reception apparatus, comprising:
The input end of the down-conversion plate is electrically connected with an external receiving antenna through an SMA interface and is used for receiving and processing an X-waveband radio-frequency signal of the external receiving antenna to generate an intermediate-frequency signal with fixed frequency;
the input end of the baseband board is electrically connected with the output end of the down-conversion board, and the output end of the baseband board is electrically connected with the PC end; wherein the base band plate includes:
The analog radio frequency front end is electrically connected with the down-conversion board and is used for receiving the intermediate frequency signal and converting the intermediate frequency signal into a baseband signal;
the analog radio frequency front end comprises:
the input end of the first digital-to-analog converter is electrically connected with the output end of the first digital frequency synthesizer and is used for receiving a high-dynamic orthogonal single carrier signal sent by the first digital frequency synthesizer and converting the high-dynamic orthogonal single carrier signal into an analog signal;
A first input end of the second quadrature modulator is electrically connected with an output end of the first digital-to-analog converter, a second input end of the second quadrature modulator is electrically connected with an output end of a second phase-locked loop, an output end of the second quadrature modulator is electrically connected with a high-speed dual-channel analog-to-digital converter, and the second quadrature modulator is used for receiving an analog signal sent by the first digital-to-analog converter and a high-frequency high-precision carrier signal sent by the second phase-locked loop, performing quadrature modulation on the analog signal and the carrier signal, generating a frequency meeting precision and speed requirements, and sending the frequency to the high-speed dual-channel analog-to-digital converter;
The input end of the second digital-to-analog converter is electrically connected with the output end of the second digital frequency synthesizer and is used for receiving a high-dynamic orthogonal single carrier signal sent by the second digital frequency synthesizer and converting the high-dynamic orthogonal single carrier signal into an analog signal;
A first input end of the third quadrature modulator is connected with an output end of the second digital-to-analog converter, a second input end of the third quadrature modulator is electrically connected with an output end of the first phase-locked loop, and an output end of the third quadrature modulator is electrically connected with a clock input end of the first quadrature modulator, and the third quadrature modulator is used for receiving an analog signal sent by the second digital-to-analog converter and a high-frequency high-precision carrier signal sent by the first phase-locked loop, performing quadrature modulation on the analog signal and the carrier signal, generating a frequency meeting precision and speed requirements, and sending the frequency to the first quadrature modulator;
The baseband receiving module is electrically connected with the analog radio frequency front end and used for receiving the baseband signal and demodulating and decoding the baseband signal;
and the first communication module is electrically connected with the baseband receiving module and used for receiving the demodulated and decoded baseband signal and sending the demodulated and decoded baseband signal to the PC terminal.
2. The apparatus according to claim 1, wherein the down-conversion board comprises:
the input end of the amplitude limiter is electrically connected with an external receiving antenna through an SMA interface and is used for receiving the radio-frequency signal sent by the external receiving antenna and carrying out amplitude limiting processing on the radio-frequency signal;
the input end of the radio frequency band-pass filter is electrically connected with the output end of the amplitude limiter;
The input end of the low-noise amplifier is electrically connected with the output end of the radio frequency band-pass filter and is used for performing power amplification processing on the radio frequency signal;
the input end of the mixer is electrically connected with the output end of the low-noise amplifier;
the input end of the first intermediate frequency band-pass filter is electrically connected with the output end of the mixer;
the input end of the automatic gain control amplifier is electrically connected with the output end of the first intermediate frequency band-pass filter;
And the input end of the second intermediate frequency band-pass filter is electrically connected with the output end of the automatic gain control amplifier.
3. The apparatus according to claim 2, wherein the down-conversion board further comprises:
the input end of the second communication module is electrically connected with the first communication module, and the output end of the second communication module is electrically connected with the automatic gain control amplifier;
And the local oscillator is electrically connected with the second communication module, generates a required clock signal under the control of the second communication module, and has a clock input end electrically connected with the first temperature compensation crystal oscillator and an output end electrically connected with the second input end of the frequency mixer.
4. The apparatus according to claim 2, wherein the analog rf front end comprises:
a first input end of the numerical control attenuator is electrically connected with an output end of the second intermediate frequency band-pass filter;
the input end of the amplifier is electrically connected with the output end of the numerical control attenuator;
A first band pass filter, an input of the first band pass filter being electrically connected to an output of the amplifier;
the input end of the first quadrature demodulator is electrically connected with the output end of the first band-pass filter, and the output end of the first quadrature demodulator is respectively electrically connected with the second band-pass filter and the third band-pass filter, and is used for converting the analog signal filtered by the first band-pass filter into two paths of orthogonal I, Q signals;
And the first input end of the high-speed dual-channel analog-to-digital converter is respectively electrically connected with the second band-pass filter and the third band-pass filter and is used for receiving analog signals filtered by the second band-pass filter and the third band-pass filter.
5. The apparatus according to claim 4, wherein the analog RF front end further comprises:
and a first output end of the second temperature compensation crystal oscillator is respectively and electrically connected with a clock input end of the first phase-locked loop and a clock input end of the second phase-locked loop and is used for providing a clock source for the first phase-locked loop and the second phase-locked loop.
6. the apparatus according to claim 5, wherein the baseband receiving module comprises:
the input end of the sampling data sorting unit is electrically connected with the output end of the high-speed double-channel analog-to-digital converter and is used for receiving a digital signal sent by the high-speed double-channel analog-to-digital converter;
The input end of the carrier synchronization unit is electrically connected with the output end of the sampling data sorting unit;
the input end of the bit synchronization unit is electrically connected with the output end of the carrier synchronization unit, and the first output end of the bit synchronization unit is electrically connected with the first digital frequency synthesizer and the second digital frequency synthesizer respectively;
the input end of the demodulation unit is electrically connected with the second output end of the bit synchronization unit;
and the input end of the decoding unit is electrically connected with the output end of the demodulation unit, and the output end of the decoding unit is electrically connected with the first communication module.
7. the apparatus according to claim 6, wherein the baseband receiving module further comprises:
And the output end of the SPI control unit is respectively electrically connected with the SPI input end of the first phase-locked loop and the SPI input end of the second phase-locked loop and used for enabling the first phase-locked loop and the second phase-locked loop to generate carrier signals with fixed frequency and high precision.
8. the high-speed data transmission receiving device according to claim 4, wherein the second input terminal of the digitally controlled attenuator is electrically connected to the baseband receiving module.
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| CN115996111B (en) * | 2023-03-24 | 2023-06-27 | 湖南迈克森伟电子科技有限公司 | Sampling clock signal generation method, symbol synchronization method and related device |
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| CN202160172U (en) * | 2011-08-17 | 2012-03-07 | 赵熠明 | X wave band broadband high resolution digital channelizing receiver |
| CN104393885B (en) * | 2014-11-26 | 2016-08-31 | 成都中远信电子科技有限公司 | A kind of reception terminal for unmanned plane ground-to-air wideband communication system and method thereof |
| US9847802B1 (en) * | 2016-08-16 | 2017-12-19 | Xilinx, Inc. | Reconfiguration of single-band transmit and receive paths to multi-band transmit and receive paths in an integrated circuit |
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