CN1255937C - Automatic track feedback circuit and high-speed A/D converter therewith - Google Patents
Automatic track feedback circuit and high-speed A/D converter therewith Download PDFInfo
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- CN1255937C CN1255937C CN 02105513 CN02105513A CN1255937C CN 1255937 C CN1255937 C CN 1255937C CN 02105513 CN02105513 CN 02105513 CN 02105513 A CN02105513 A CN 02105513A CN 1255937 C CN1255937 C CN 1255937C
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Abstract
The present invention relates to a bias circuit for generating common mode bias voltage by means of responding to the active and automatic tracing feedback of the reference voltage of analog ground and generating common mode voltage used by differential amplifiers by means of responding to the common mode bias voltage. The bias circuit supports high-speed operation and is stable during temperature change, process change and power supply voltage drift. In the implementation examples, the bias circuit comprises an operational amplifier and a feedback amplifier and is provided with a common mode bias endpoint coupled with the output end of the operational amplifier, and the bias circuit and the operational amplifier are arranged in a feedback loop; the out of the operational amplifier serves as the common mode voltage of a differential amplifier, the design of the feedback amplifier is matched with that of the differential amplifier using the common mode bias voltage, and therefore, common mode bias voltage is generated so as to automatically generate the common mode voltage which can cause the differential amplifier to be quite harmonious, and the differential amplifier and a high speed analog-digital converter use the automatic tracing active mode bias circuit.
Description
Technical field
The invention relates to the common mode feedback circuit (common mode feedback circuit) that a kind of high-gain differential amplifier is used, operational amplifier (operationalamplifier) for example, and the high speed adc of this amplifier of use, common-mode feedback wherein is very important to precise results.
Background technology
Pipelineization (pipelined) adc often is used in the high-speed applications, and known this transducer can be seen in United States Patent (USP) number 4894657,4903026,5635937,5929796,6028546 and other many patents.This analogy need provide a plurality of levels (stages) to the basic operation of digital quantizer, and each all has a sampling and keeps amplifier (sample and hold amplifier) (often being a differential operational amplifier), a summation node (summing node), an and inter-stage amplifier (interstage amplifier) (often being a differential operational amplifier).It is operated with pipelined fashion, and sampling mode and amplification mode are arranged.The first order is when sampling mode, sampling and keep input voltage, and the single bit pad when it is offered amplification mode, input voltage is converted to single position, the output of taking a sample then and keeping amplifier deducts the aanalogvoltage of single position conversion, interstage amplifier then amplifies difference results, and when amplification mode, is urged to next stage.Each level is operation in an identical manner all, to produce several positions of the numerical data of representing input voltage.
Along with the pipeline adc will produce a problem, because need the bias voltage differential operational amplifier, thus in time range in a small amount, get back to reference voltage with reference to the analogue ground voltage level, or " stabilizing ".For operating in for example is the high speed adc of 160MHz, setting time may have only several nanoseconds (ns), so when sampling mode, amplifier is operated in skew payment (offset cancelling) mode, so that during amplification mode, input is followed in output exactly.Common mode feedback circuit has developed the skew payment function of improving amplifier, and this common mode feedback circuit also uses other circuit at various use differential amplifiers and operational amplifier, please referring to the patent of United States Patent (USP) number 5955922 and 5847601.
Therefore,, design an operational amplifier and be used as sampling and keep amplifier, and be necessary as the about high frequency range interstage amplifier of GHz scope for the analogy of 160MHz clock pulse frequency high speed circuit for digital quantizer.The frequency range that picture is so high typically can consume very big bias current (bias current) in operational amplifier.Similarly, the common-mode feedback kenel also will have stable fast characteristic, and in the of short duration setting time scope of for example 3 nanoseconds, the output of operational amplifier must be stabilized the precise voltage level in analogue ground.The residual of any output voltage all can be transmitted to next stage, becomes wrong voltage, and amplifies in pipeline stages thereafter.In addition, to different speed applications, also must adjust or follow the trail of common mode bias voltage to reach stable function.
Common mode feedback circuit produces the common-mode voltage of the differential amplifier operating point that is used for the use of bias voltage feedback.The common mode feedback circuit tendency produces common-mode voltage, and (for example being the analogue ground voltage level) is applied to bias point when two inputs of differential amplifier are positioned at same voltage level, can cause the output of differential amplifier to be stabilized in analogue ground voltage.Common mode feedback circuit relies on the common mode bias voltage that produces stationary value, still, is containing a temperature range, manufacture deviation, is reaching in the voltage deviation scope of supply circuit, and it is difficult that the stable common mode bias voltage that is suitable for high speed operation is provided.
Be desirable to provide a bias circuit, be used for producing stable common mode bias voltage, and its accuracy and temperature, process deviation and supply voltage deviation are irrelevant, wish that more this bias voltage can support to use the high speed operation of the differential amplifier of this voltage, wish that also this bias voltage circuit is suitable for the high speed adc and uses, and the application of other high-gain differential operational amplifier.
Summary of the invention
The invention provides a kind of bias circuit (bias circuit), in order to rely in response to the reference voltage that for example is analogue ground, initiatively, follow the trail of feedback automatically, to produce common mode bias voltage (common mode bias voltage), and in response to common mode bias voltage, to keep common-mode voltage (common mode voltage), so that set up the output of analogue ground in differential amplifier.This bias circuit is supported high speed operation, and can be stable at variations in temperature, technique change when drifting about with supply voltage.In an embodiment, bias circuit comprises an operational amplifier, and it has the common mode bias end points that couples common-mode voltage; And feedback amplifier, it has the common mode bias end points that couples operational amplifier output, and with operational amplifier arrangement in feedback loop.The output of operational amplifier is used for being used as the common mode bias voltage of the common mode feedback circuit of differential amplifier, feedback amplifier is designed to and uses the differential amplifier of common mode bias voltage to be complementary (match), and then produce a common mode bias voltage, automatically to produce the common-mode voltage that can cause differential amplifier quite to be coordinated.
In one embodiment, feedback amplifier comprises " partly " operational amplifier.In this way, the differential operational amplifier that feedback amplifier can be designed to will give with a common mode bias voltage almost is complementary.
In another embodiment, operational amplifier in the feedback circuit is planned to virtual short, and be its input with the output and the reference voltage of feedback amplifier, therefore, feedback amplifier will be subjected to bias voltage, and producing this reference voltage at its output, and the common mode bias voltage that produces of this operational amplifier and feedback circuit can be driven to and causes differential amplifier suitably to be stabilized in the level of reference voltage (analogue ground just) for a moment.
In another embodiment, the invention provides a common mode feedback circuit, use for differential operational amplifier with a positive input terminal, a negative input end, a positive output end, a negative output terminal and a common-mode voltage input.This common mode feedback circuit comprises a switch capacitor circuit, and it operates in sampling mode, to take a sample and to keep the common mode bias voltage relevant with reference voltage; And operate in amplification mode, put between the common mode input and positive-negative output end of this differential operational amplifier with the common mode bias voltage that institute is taken a sample and keeps.This feedback circuit comprises that also a bias circuit is used for producing common mode bias voltage, it comprises one second operational amplifier, it has the common mode bias end points that is coupled to this common-mode voltage input, an and feedback amplifier, it has the common mode bias end points of the output that connects second operational amplifier, and as above-mentioned, with itself and second operational amplifier arrangement in feedback loop.
In another embodiment of the present invention, provide a kind of high-speed figure to analog converter, comprise a plurality of levels, each level comprises sampling respectively and keeps amplifier, summation node and interstage amplifier.In this embodiment, have a sampling at least and keep amplifier and interstage amplifier, make high-gain differential amplifier with above-mentioned common mode feedback circuit.
Therefore, the invention provides a common mode feedback circuit, can stablize the common-mode voltage of full differential operational amplifier, it is suitable for for example is the high speed circuit use of adc.In addition, common mode feedback circuit comprises a bias circuit, and it can follow the trail of the differential operational amplifier relevant with common-mode feedback automatically.In this way, can reach a stable and circuit at a high speed.
Description of drawings
Fig. 1 is that it has the common-mode feedback of active common-mode feedback bias circuit according to a kind of basic pipeline adc of the present invention;
Sampling that Fig. 2 uses for the system of Fig. 1 and the basic design of keeping amplifier, its common-mode voltage is produced according to the present invention;
Fig. 3 is the basic design of the interstage amplifier that uses of the system of Fig. 1, and its common-mode voltage produces according to the present invention;
Fig. 4 is corresponding to common mode bias voltage, produces the basic common mode feedback circuit of common-mode voltage;
Fig. 5 is the time sequential routine of the high speed adc of Fig. 1, and it is according to stable operation of the present invention;
Fig. 6 is known in order to produce the bias circuit of common mode bias voltage;
Fig. 7 is according to bias circuit reduced graph of the present invention, and it uses the active automatic tracking feedback that produces common mode bias voltage;
Fig. 8 is that to be suitable for the sampling differential operational amplifier that uses with the present invention graphic; And
Fig. 9 is the half operational amplifier example that the feedback amplifier of bias circuit of the present invention uses.
Description of reference numerals:
10,13,21: the loop line indication
11: take a sample and keep amplifier
12: adc
14: single bit digital is to analog converter
15: the summation node
16: interstage amplifier
20: the error correction logic
22,24: common mode feedback circuit
23,25: active common-mode feedback bias circuit
50,70: operational amplifier
51,71: positive input terminal
52,72: negative input end
53,73: positive output end
54,74: negative output terminal
55,75: common mode bias voltage end points
56-62,76-81,107-110: first group of switch
63-65,82-84,111-114: second group of switch
66,86: the first input capacitances
67,87: the second input capacitances
68,88: the first feedback capacities
69,89: the second feedback capacities
90,91: the summation node
100-106,115-118,178,200,202,204,205: node
250,251,254,256,260,261: node
151-154: sequential point
170: reference current source
171-177,179,180,251-253,255,257: transistor
258,263,264,266,267: transistor
201: amplifier
203: feedback amplifier
Embodiment
Fig. 1 to Fig. 9 is the detailed description of one embodiment of the invention, and Fig. 1 is according to the simplified block diagram that comprises the pipeline adc of common mode feedback circuit and active common-mode feedback bias circuit of the present invention.
This pipeline adc receives analog input voltage by sampling and the input of keeping amplifier 11 on No. 10 line, this sampling and keep amplifier 11 and provide and export adc 12 to, be positioned on No. 13 lines to produce output, carry-out bit on No. 13 lines provide to single bit digital to analog converter 14, its output then provides to the negative terminal of summation node 15, and the anode of summation node 15 receives sampling and keeps the output of amplifier 11.Therefore, sampling and keep input voltage that amplifier 11 provides and No. 13 lines on the analogue value of digital signal between difference become the input of interstage amplifier 16, the output of interstage amplifier 16 provide to comprise the 2nd grade (not illustrating) to the analogy of M level to the next stage in the digital quantizer.The 1st grade of digital value that provides to the M level inputs to error correction logic 20, and it provides the output of pipeline simulation to digitial controller on No. 21 lines.
According to the present invention, this sampling and keep amplifier 11 and comprise the common mode bias end points that receives common-mode voltage VCM, common mode feedback circuit 22 couples sampling and keeps the output of amplifier 11, and provides common-mode voltage VCM to amplifier 11.In addition, active common-mode feedback bias circuit 23 produces common-mode feedback bias voltage VCMB, causes common-mode voltage to be followed the trail of automatically along with the deviation of temperature, technology, service speed and other factors.Similarly, interstage amplifier 16 comprises the common mode feedback circuit 24 and active common-mode feedback bias circuit 25 of automatic tracking.Use common-mode feedback of the present invention and active common-mode feedback bias circuit, can reach high speed and accurate analogy to digital quantizer, the analogy that operates in 160MHz clock pulse speed that for example provides in the example is to digital quantizer.
If the amplifier that uses in the pipeline adc fully mates, so just can allow more than one or the shared single active common-mode feedback bias circuit of all adapter amplifiers, produce common-mode feedback bias voltage VCMB.
Fig. 2 to Fig. 5 for the analogy of Fig. 1 to being described in more detail of digital quantizer, the example of the common-mode feedback bias circuit of prior art is shown among Fig. 6, common-mode feedback bias circuit according to the present invention then is shown among Fig. 7, Fig. 8 and Fig. 9.
Fig. 2 is the sampling of using in the system of Fig. 1 and keeps amplifier architecture that this structure comprises the high-gain differential amplifier that is formed by operational amplifier 50.Operational amplifier 50 comprises a positive input terminal 51, a negative input end 52, a positive output end 53 and a negative output terminal 54.Common mode bias voltage end points 55 receives common-mode voltage VCM, first group of switch (56-62) closure when sampling mode, second group of switch (63-65) be closure when amplifying (be also referred to as and keep) pattern, first input capacitance 66 is coupled between the negative input end 52 and switch 56 of operational amplifier 50, second input capacitance 67 is coupled between the positive input terminal 51 and switch 57 of operational amplifier 50, first feedback capacity 68 is coupled between the negative input end 52 and switch 64 of operational amplifier 50, second feedback capacity 69 is coupled between the positive input terminal 51 and switch 65 of operational amplifier 50, input voltage IP is connected in switch 56 and switch 62, input voltage IN is connected in switch 57 and switch 61, and 60 on switch 58 and switch are connected to system simulation ground connection.
When sampling mode, first group of switch 56-62 closure, and second group of switch 63-65 opens, and causes system simulation ground connection to deliver to the positive input terminal 51 and the negative input end 52 of operational amplifier 50, and the right hand end of first input capacitance 66 and second input capacitance 67.Input voltage IP delivers to the left hand end of first input capacitance 66, and input voltage IN then delivers to the left hand end of second input capacitance 67.In addition, input voltage IP also delivers to the right hand end of first feedback capacity 68, and input voltage IN then delivers to the right hand end of second feedback capacity 69.First and second feedback capacities 68 and 69 left hand end are connected to system simulation ground connection.Common-mode voltage VCM is set in a value, so that when sampling mode, positive output end 53 and negative output terminal 54 can be got back to system simulation ground connection.
When amplification mode, first group of switch 56-62 opens, and second group of switch 63-65 closure causes the left hand end of input capacitance 66 and 67 to connect, so that drives the positive input terminal 51 of operational amplifier 50 and negative input end 52 value to input voltage IP and input voltage IN.Similarly, set up the feedback via first feedback capacity 68 and second feedback capacity 69, the positive output end 53 of operational amplifier 50 and negative output terminal 54 gain or are suitable for specially designed gain with one and follow the trail of input exactly.
Summation node and interstage amplifier structure that Fig. 3 uses for the structure that cooperates Fig. 2.In this example, interstage amplifier comprises a high-gain differential amplifier that is formed by operational amplifier 70, and this operational amplifier 70 comprises a positive input terminal 71, negative input end 72, positive output end 73 and negative output terminal 74.Common mode bias end points 75 receives common-mode voltage VCM, first group of switch (76-81) closure when sampling mode, second group of switch (82-84) is in keeping or closure during amplification mode, first input capacitance 86 is coupled between the negative input end 72 and switch 76 of operational amplifier 70, second input capacitance 87 is coupled between the positive input terminal 71 and switch 77 of operational amplifier 70, first feedback capacity 88 is coupled between the negative input end 72 and switch 83 of operational amplifier 70, second feedback capacity 89 is coupled between the positive input terminal 71 and switch 84 of operational amplifier 70, summation node 90 and summation node 91 lay respectively at the both sides of switch 82, summation node 90 is that planning receives the analogy that depends upon Fig. 1 negative reference point or the positive reference point to the value of digital quantizer 12, and summation node 91 then is that planning receives the analogy that depends upon Fig. 1 other negative reference point and the positive reference point to the value of digital quantizer 12.
When sampling mode, first group of switch 76-81 closure, and second group of switch 82-84 opens, and causes left hand end output and that deliver to input capacitance 86 of input voltage IP and dac 14 on the node 90, and system simulation ground connection then connects its right hand end.In addition, the left hand end output of input voltage IN and dac 14 and that deliver to input capacitance 87 on the node 91, system simulation ground connection then connects the right hand end of input capacitance 87.Similarly, input voltage IN delivers to the right hand end of second feedback capacity 89, and input voltage IP then delivers to the right hand end of first feedback capacity 88 simultaneously.Common-mode voltage VCM on the end points 75 is set in a value, so that when sampling mode, the positive output end 73 and the negative output terminal 74 of operational amplifier 70 can be got back to system simulation ground connection.
When amplification mode, first group of switch 76-81 opens, and second group of switch 82-84 closure causes the left hand end of input capacitance 86 and 87 to connect, so that drives the positive input terminal 71 of operational amplifier 70 and negative input end 72 value to summation node 90 and 91 voltages.Similarly, also set up the feedback via first feedback capacity 88 and second feedback capacity 89, the positive output end 73 of operational amplifier 70 and negative output terminal 74 are with a gain or be suitable for the voltage that summation node 90 and 91 are followed the trail of in specially designed gain exactly.
Fig. 4 is the common mode feedback circuit basic structure corresponding to the generation voltage VCM of the node 101 of operational amplifier and output voltage OP on the node 102 and ON.System simulation ground connection AG is connected to node 103 and 104, and common mode bias voltage is connected to node 105 and 106, the first groups of switches (107-110) closure when amplification mode, and second group of switch (111-114) closure when sampling mode.Switch 107 is coupled to the upper end 115 of node 104 and capacitor C1, and switch 108 is coupled to the lower end 116 of node 106 and capacitor C1, and switch 111 is coupled between node 115 and the node 101, and switch 112 is coupled between node 116 and the node 100.Capacitor C2 is coupled between node 101 and the node 100, and capacitor C3 is coupled between node 102 and the node 100.Switch 113 is coupled between the upper end of node 102 and capacitor C4, and switch 114 is coupled between the lower end 118 of node 100 and capacitor C4, and switch 109 is coupled between node 117 and the node 103, and switch 110 is coupled between node 118 and the node 105.
When amplification mode, first group of switch 107-110 closure, and second group of switch 111-114 opens, so then common mode bias voltage VCMB and analogue ground AG build on across capacitor C1 and capacitor C4.When sampling mode, first group of switch 107-110 opens, and second group of switch 111-114 closes, like this then across the voltage supply of capacitor C1 across capacitor C2, and across the voltage supply of capacitor C4 across capacitor C3.As mentioned above, when sampling mode, common-mode voltage VCM is set to and allows output OP and ON stabilize level in analogue ground; When amplification mode, it is a constant level haply that common-mode voltage VCM is maintained at by capacitor C2 and C3, and output OP and ON separate even with common mode feedback circuit when amplification mode.
As can be seen, the level of common mode bias voltage VCMB must be maintained at allow operational amplifier be output in sampling mode the time, stabilize in analogue ground level AG, the displacement of common mode bias voltage VCMB will cause the output bias error of accumulating in the pipelined road as the pipeline adc.
Please refer to the sequential chart of Fig. 5, will more understand the operating principle of circuit.Among Fig. 5, uppermost waveform representative control clock pulse Φ
S, when high level, can close the switch that sampling mode is used; Second waveform representative control clock pulse Φ
H, when high level, can close the switch that amplification mode is used; The 3rd waveform is represented common-mode voltage VCM; The 4th waveform is represented the positive output OP of operational amplifier; The 5th waveform is represented the negative output ON of operational amplifier.As can be seen, when the sampling mode switch when 150 close, common-mode voltage will be fixed in common mode bias voltage VCMB, and positive output OP and negative output ON stabilize in the analogue ground level.At 151 o'clock, the sampling mode switch opens soon thereafter 152 o'clock, keep pattern or the amplification mode switch cuts out, and positive output OP changeed high according to input voltage, and negative output then changes low according to input voltage.At 153 o'clock, keep mode switch and open, thereafter 154 o'clock, the sampling mode switch cut out soon.When the sampling mode switch cut out, output OP and ON stabilized again in analogue ground, like this repetitive cycling.Common-mode voltage VCM is set in common mode bias voltage VCMB when sampling switch is closed, and in keeping or the amplification mode switch keeps its final value when cutting out.Therefore, change common mode bias voltage VCMB, phase time in the time of will causing taking a sample, output is stabilized in drift level.This drift causes the operating mistake of the circuit of dependent operations amplifier accuracy.
Fig. 6 is known circuit example in order to generation common mode bias voltage VCMB, and this circuit is the reference current source that connects into the P channel transistor 171 of diode (diode connected) based on driving, and its source electrode couples power vd D.Second loop of circuit comprises that one links the P channel transistor 172 of forming current mirrors with P channel transistor 171, and one links for the N channel transistor 173 of diode structure and is serially connected with between transistor 172 and the earth point.The tertiary circuit of circuit comprises P channel transistor 174, it is current-mirror structure that itself and transistor 171 and 172 link, and be serially connected with N channel transistor 175 and 176 between P channel transistor 174 and earth point, the drain electrode of transistor 175 connects the drain electrode of P channel transistor 174, the grid of N channel transistor 175 connects the grid of N channel transistor 173, and the grid of N channel transistor 176 couples the drain electrode of N channel transistor 175.The 4th loop of circuit comprises that binding is the P channel transistor 177 of diode structure, its source electrode couples power vd D, and drain electrode couples output node 178 with grid, to produce common mode bias voltage VCMB, N channel transistor 179 and 180 is serially connected with between node 178 and the earth point, the grid of transistor 179 is connected in the grid of transistor 173 and 175, and the grid of transistor 180 is connected in the grid of transistor 176.This mode can produce common mode bias voltage VCMB on node 178, its value is set up by reference current source 170 basically.Yet this circuit also there is no variation of temperature, the variation of technology and the demand of high speed circuit of following the trail of.In addition, for the service speed of modifier, reference current source also will and then be adjusted, with the drift that prevents that VCMB is unnecessary.
Fig. 7 is according to common mode bias potential circuit sketch of the present invention, and it produces common mode bias voltage VCMB on node 200.Node 200 is the positive output ends that are called the high-gain amplifier 201 of first operational amplifier, and first input of amplifier 201 connects analogue ground AG, and second input of amplifier 201 couples the output of second amplifier 203, to form feedback loop.Amplifier 201 can be the amplifier of operational amplifier or other pattern, and feedback amplifier 203 is its input with analogue ground AG, and produces output 205.Amplifier 201 produces output in node 200, and feedback amplifier 203 is in response to the common-mode voltage that output provided of amplifier 201, so that common mode bias voltage VCMB is used for common-mode voltage as feedback amplifier 203.Feedback amplifier 203 is made with the characteristic (for example amplifier configuration, device appearance ratio) of coupling differential amplifier, and this differential amplifier is in order to receive the common-mode feedback that produces common mode bias voltage.Amplifier 201 links with the structure of virtual short, like this then circuit tendency is urged to the identical value of analogue ground that provides with node 202 with the signal of node 205, and the variable voltage of circuit is the common mode bias voltage VCMB on the node 200, it provides feedback amplifier 203, with as common-mode voltage.
In an embodiment, feedback amplifier 203 is made with " partly " operational amplifier of the positive output part of matched operational amplifier, this operational amplifier is in order to receive to produce the common-mode feedback of common mode bias voltage, for example the sampling in Fig. 1 circuit and keep amplifier 11 and interstage amplifier 16.If design changes, the different bias voltage follow currents that cause the operation of amplifier high speed, amplifier 203 in the common mode voltage bias circuit feedback loop also changes just change, the change of technology and the change of main operational amplifier service speed of traceable temperature of common mode bias voltage like this with identical fabrication schedule so.In addition, feedback is automatically to follow the trail of this variation on one's own initiative, fast and constantly, the operation exactly with the high speed of circuit that image tube linearize adc is provided.
Fig. 8 and Fig. 9 are respectively basic operation amplifier and " partly " operational amplifier of the circuit use that is suitable for Fig. 7.The operational amplifier of Fig. 8 is included in the negative input stage that receives negative input voltage IN on the node 250, the positive input level that reaches reception positive input voltage IP on node 251.Negative input stage comprises P channel transistor 252, it is connected in series with N channel current source transistor 253, common-mode voltage VCM is provided in the grid of transistor 253 in node 254, P channel loading current source transistor 255 is connected between the source electrode and voltage source V DD of P channel transistor 252, and bias voltage VB1 is linked on the loop line 256 of grid of transistor 255.The positive input level comprises that source electrode couples the P channel transistor 257 of the drain electrode of transistor 255, its drain electrode couples the drain electrode of N channel current source transistor 258, the grid of transistor 258 receives common-mode voltage on loop line 254, the negative output level produces output signal ON on node 260, and the positive output level produces output voltage OP on node 261.The negative output level comprises N channel transistor 263, and it is connected in series with P channel transistor 264.The source electrode of P channel transistor 264 couples voltage source V DD, and drain electrode couples node 260.The drain electrode of N channel transistor 263 couples node 260, and source electrode is earth point then, and the grid of transistor 263 couples the node of transistor 253 drain electrodes, and the grid of transistor 264 couples the bias voltage of node 256.The positive output level comprises that grid couples the P channel transistor 266 of the bias voltage VB1 on the node 256, and its source electrode couples voltage source V DD, and drain electrode couples node 261.The positive output level comprises that also drain electrode couples the N channel transistor 267 of node 261, and its grid couples the drain electrode of transistor 258, and source electrode is earth point then.
The operational amplifier of Fig. 8 is that the difference between input IN on the node 250 and the input IP on the node 251 is amplified, to produce the differential basic circuit that is output on node 260 and 261.When IN and IP are set in same reference voltage, common-mode voltage VCM causes exporting OP and ON to be stabilized in the reference voltage level as the analogue ground of high-velocity tube linearize adc, the common-mode feedback bias circuit promptly is in order to set up that value, the operation that the active common-mode feedback bias circuit that this paper mentions is automatically followed the trail of operational amplifier changes, to keep common-mode voltage in the common-mode voltage of keeping a stable analogue ground level.
Fig. 9 is suitable for " partly " operational amplifier that the feedback amplifier 203 of the common mode voltage bias circuit of Fig. 7 uses.Fig. 9 element that is matched with Fig. 8 element has identical reference symbol, and no longer describes.This amplifier circuit is complementary with the operational amplifier that receives common-mode feedback, so that produce the variation that the active feedback circuit of common mode bias voltage VCMB is followed the trail of technology, temperature and service speed automatically.
Other operational amplifier structure also can be used in the various embodiments of the invention with " partly " operational amplifier structure, and embodiment provided herein is the embodiment in order to illustrate just, and the guiding of implementing other same circuits is provided.
The invention provides and similarly be the sampling in the pipeline adc and keep amplifier and common-mode feedback bias voltage that operational amplifier such as interstage amplifier uses that it can will be exported and stabilize in the analogue ground level fast when sampling mode.This structure can be in common mode voltage bias circuit or calculation amplifier for the national games, uses " partly " operational amplifier, and the attainable quick setting time of the present invention is very important for the differential amplifier with common mode bias end points of the quick setting time of needs.
Though the present invention with the embodiment explanation as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is when being as the criterion with claims.
Claims (23)
1. the amplifying stage of a high speed circuit is characterized by: comprising:
One differential amplifier has a common-mode voltage, first and second input, and level at least one output of influenced by this common-mode voltage;
One common mode feedback circuit, couple the output of this differential amplifier, and couple a reference voltage and produce a common mode bias voltage of this common-mode voltage so that the output of this differential amplifier this first and second input be matched with this reference voltage during, be matched with this reference voltage; And
One bias circuit in order to producing this common mode bias voltage, and is delivered to this common mode feedback circuit with it, and this bias circuit has an active feedback in response to this reference voltage and this common mode bias voltage.
2. amplifying stage as claimed in claim 1 is characterized by: this active feedback comprises:
One first amplifier; And
One feedback amplifier has the common mode bias end points of the output that connects this first amplifier, and is arranged in the feedback loop with this first amplifier.
3. amplifying stage as claimed in claim 1 is characterized by: this reference voltage is analogue ground.
4. amplifying stage as claimed in claim 2 is characterized by: this feedback amplifier comprises half operational amplifier, and this half operational amplifier has the element that is matched with this differential amplifier.
5. amplifying stage as claimed in claim 2 is characterized by: this first amplifier is formulated for virtual short.
6. amplifying stage as claimed in claim 2, it is characterized by: this first amplifier has first and second inputs, this first input end couples this reference voltage, and this second input couples the output of this feedback amplifier, this first amplifier also has an output, this output is subjected to a common-mode voltage, the output of this reference voltage and this feedback amplifier influences, this first amplifier is output as this common mode bias voltage, and this feedback amplifier has first input that couples this reference voltage, an and output level that influenced by this common mode bias voltage and this reference voltage.
7. amplifying stage as claimed in claim 2 is characterized by: this differential amplifier comprises that one is matched with the operational amplifier of this feedback amplifier in this bias circuit.
8. amplifying stage as claimed in claim 1 is characterized by: this differential amplifier is as the one-level in the pipeline adc.
9. amplifying stage as claimed in claim 1 is characterized by: this differential amplifier has a sampling mode and an amplification mode, and wherein this common mode feedback circuit can drive this reference voltage that exports to of this differential amplifier when this sampling mode.
10. common mode feedback circuit, be applicable to have a positive input terminal, a differential operational amplifier of a negative input end, a positive output end, a negative output terminal and a common-mode voltage input, when this differential operational amplifier couples a reference voltage at this positive input terminal and this negative input end, operate in a sampling mode, and when this positive input terminal and this negative input end couple the node of keeping sampling voltage respectively, operate in an amplification mode, it is characterized by: comprising:
One switch capacitor circuit, when this amplification mode, take a sample and keep a common mode bias voltage corresponding to this reference voltage, when this sampling mode, with take a sample and the common mode bias voltage kept puts on this common-mode voltage input and this differential amplifier this just and negative output terminal between; And
One bias circuit in order to producing this common mode bias voltage, and is delivered to this switch capacitor circuit with it, and this bias circuit comprises: one has second operational amplifier of common mode bias end points; And the common mode bias end points with the output that connects this second operational amplifier, and be arranged in feedback amplifier in the feedback loop with this second operational amplifier.
11. common mode feedback circuit as claimed in claim 10 is characterized by: this reference voltage is analogue ground.
12. common mode feedback circuit as claimed in claim 10 is characterized by: this feedback amplifier comprises having half operational amplifier that is matched with this differential operational amplifier.
13. common mode feedback circuit as claimed in claim 10 is characterized by: this second operational amplifier is planned to virtual short.
14. common mode feedback circuit as claimed in claim 10, it is characterized by: this second operational amplifier has first and second inputs, this first input end couples this reference voltage, this second input couples the output of this feedback amplifier, and this second operational amplifier has an output, its level is influenced by this output of this reference voltage and this feedback amplifier, this of this second operational amplifier is output as this common mode bias voltage, and this feedback amplifier has first input that couples this reference voltage, and the level output that influenced by this common mode bias voltage and this reference voltage.
15. common mode feedback circuit as claimed in claim 10 is characterized by: this common mode feedback circuit is when this sampling mode, and this positive and negative output that drives this differential operational amplifier is to this reference voltage.
16. a pipeline adc is characterized by: comprising:
A most switching stage, those switching stages comprise sampling respectively and keep amplifier, summation node and interstage amplifier; Wherein those samplings and keep amplifier one of them comprises with those interstage amplifiers at least:
One differential amplifier has a common-mode voltage, first, second input and at least one output, and its level is influenced by this common-mode voltage;
One common mode feedback circuit, couple the output of this differential amplifier, and couple the common mode bias voltage that a reference voltage and produces this common-mode voltage so that this at least one output this first and second input be matched with this reference voltage during, be matched with this reference voltage; And
One bias circuit in order to producing this common mode bias voltage, and is delivered to this common mode feedback circuit with it, and this bias circuit has an active feedback in response to this reference voltage and this common mode bias voltage.
17. pipeline adc as claimed in claim 16 is characterized by: this active feedback comprises:
One operational amplifier; And
One feedback amplifier has a common mode bias terminal point, connects the output of this operational amplifier, and with this operational amplifier arrangement in a feedback loop.
18. pipeline adc as claimed in claim 16 is characterized by: this reference voltage is analogue ground.
19. pipeline adc as claimed in claim 17 is characterized by: this feedback amplifier comprises having half operational amplifier that is matched with this differential amplifier.
20. pipeline adc as claimed in claim 17 is characterized by: this operational amplifier is formulated for virtual short.
21. pipeline adc as claimed in claim 17, it is characterized by: this operational amplifier has first and second inputs, this first input end couples this reference voltage, and this second input couples the output of this feedback amplifier, this operational amplifier also has an output, the level of this output is influenced by the output of this reference voltage and this feedback amplifier, this operational amplifier is output as this common mode bias voltage, and this feedback amplifier has a first input end that couples this reference voltage, and an output level that influenced by this common mode bias voltage and this reference voltage.
22. pipeline adc as claimed in claim 17 is characterized by: this differential amplifier comprises that one is matched with the operational amplifier of this feedback amplifier in this bias circuit.
23. pipeline adc as claimed in claim 16, it is characterized by: this differential amplifier has a sampling mode and an amplification mode, and wherein this common mode feedback circuit can drive this reference voltage that exports to of this differential amplifier when this sampling mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105513 CN1255937C (en) | 2002-04-12 | 2002-04-12 | Automatic track feedback circuit and high-speed A/D converter therewith |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105513 CN1255937C (en) | 2002-04-12 | 2002-04-12 | Automatic track feedback circuit and high-speed A/D converter therewith |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1452314A CN1452314A (en) | 2003-10-29 |
| CN1255937C true CN1255937C (en) | 2006-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02105513 Expired - Lifetime CN1255937C (en) | 2002-04-12 | 2002-04-12 | Automatic track feedback circuit and high-speed A/D converter therewith |
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| Country | Link |
|---|---|
| CN (1) | CN1255937C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100533954C (en) * | 2007-01-29 | 2009-08-26 | 中国科学院上海微***与信息技术研究所 | Float restraint amplification circuit in sensor network |
| CN110086437A (en) * | 2018-01-26 | 2019-08-02 | 华为技术有限公司 | Operational amplifier and chip |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4324202B2 (en) * | 2007-01-25 | 2009-09-02 | シャープ株式会社 | A / D converter |
| CN102413303B (en) * | 2010-09-21 | 2014-01-08 | 瑞昱半导体股份有限公司 | Signal generation apparatus and method thereof |
| TWI756531B (en) * | 2019-04-09 | 2022-03-01 | 瑞昱半導體股份有限公司 | Transmitter, receiver, and hybrid transceiver |
| CN113746437A (en) * | 2020-05-27 | 2021-12-03 | 瑞昱半导体股份有限公司 | Operational amplifier and DC voltage level control method |
-
2002
- 2002-04-12 CN CN 02105513 patent/CN1255937C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100533954C (en) * | 2007-01-29 | 2009-08-26 | 中国科学院上海微***与信息技术研究所 | Float restraint amplification circuit in sensor network |
| CN110086437A (en) * | 2018-01-26 | 2019-08-02 | 华为技术有限公司 | Operational amplifier and chip |
| US11290075B2 (en) | 2018-01-26 | 2022-03-29 | Huawei Technologies Co., Ltd. | Operational amplifier and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1452314A (en) | 2003-10-29 |
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