CN1215291A - Time division multiplexting switch with single and double buffer ability - Google Patents
Time division multiplexting switch with single and double buffer ability Download PDFInfo
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- CN1215291A CN1215291A CN98120132A CN98120132A CN1215291A CN 1215291 A CN1215291 A CN 1215291A CN 98120132 A CN98120132 A CN 98120132A CN 98120132 A CN98120132 A CN 98120132A CN 1215291 A CN1215291 A CN 1215291A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/08—Time only switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13167—Redundant apparatus
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- Computer Networks & Wireless Communication (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
A time multiplex switch comprises a first and a second speech path register; a write address counter for producing continuously a write address and transmitting the write address to the first and the second speech path register; a control register for producing randomly a read address and transmitting the read address to the first and the second speech path register; an operation control circuit for operating both the first and the second speech path register on the first state, operating only the first speech path register on the second state.
Description
The present invention relates to a kind of time division multiplexing switch, its compatible Integrated Service Digital Network terminal and public telephone terminal that needs a large amount of time slots with large scale digital switching equipment.
In a digital local exchange installation, on a time basis, change about the time division multiplexing digital signal (pulse code modulated signal) of a voice path.
The time division multiplexing switch also is provided on the data high-speed path of digital local exchange installation.This time division multiplexing switch is divided into two kinds of single buffer types and double buffering types.
Single buffer types time division multiplexing switch of prior art is made of a single voice path register, write address counter, a control register of finishing read operation at random at the voice path register of finishing continuous write operation at the voice path register.The back can be done to explain in detail to this.
In single buffer types time division multiplexing switch of prior art, although the time of delay of voice data is very little, but since to the read operation of voice path register be by control register read the execution at random of address institute, therefore, may keep time slot sequence integrity in interframe hardly.Especially when the data that require a sequence frame were transmitted, the data of mistake might be transmitted.
The double buffering type time division multiplexing switch of prior art also comprises an additional voice path register and a multiplexer except the element that single buffer types time division multiplexing switch is comprised.That is to say that write operation is that one of two voice path registers are carried out, and read operation is by the selection of multiplexer another voice path register to be carried out.
, very big by the data delay time of voice path register in the double buffering type time division multiplexing switch of prior art, for example, be 125 μ s to a frame, be 250 μ s to two frames.That is to say that be the twice in single buffer types time division multiplexing switch the time of delay in double buffering type time division multiplexing switch.
The present invention seeks to provide a kind of time division multiplexing switch, make it to have the data such as speech are reduced time of delay and the time slot sequence integrity of keeping interframe data.
According to the present invention, in the time division multiplexing switch, comprise the first and second voice path registers, be used for producing continuously write address and with it send to the first and second voice path registers writing address register, be used for producing at random and read the address and to the control circuit that the control register of the first and second voice path registers and one operate, only the first voice path register operated at second state the first and second voice path registers at first state of sending.
By following argumentation, with the comparison of prior art with reference to accompanying drawing, the present invention will more clearly be understood.Wherein:
Figure 1A is single buffer types time division multiplexing switch of a prior art;
Figure 1B is a calcspar of explaining single buffer types time division multiplexing switching manipulation shown in Figure 1A;
Fig. 2 A is the double buffering type time division multiplexing switch of a prior art;
The calcspar of double buffering type time division multiplexing switching manipulation shown in Fig. 2 B and the 2C key-drawing 2A;
Fig. 3 is the main circuit block figure according to first embodiment of time division multiplexing switch of the present invention;
Fig. 4 is the main circuit block figure according to second embodiment of time division multiplexing switch of the present invention;
Fig. 5 is the main circuit block figure according to the 3rd embodiment of time division multiplexing switch of the present invention; And
Fig. 6 is the main circuit block figure according to the 4th embodiment of time division multiplexing switch of the present invention.
Before preferred embodiment is described, at first the time division multiplexing switch of prior art is made an explanation with reference to Figure 1A, 1B, 2A and 2B.
In Figure 1A of the single buffer types time division multiplexing of demonstration prior art switch, reference number 1 expression one voice path register (SPM) is used for importing data high-speed path input digital data IN and output digital data OUT in a dateout high speed channel one.
Offer the input W of voice path register 1 when write address counter 2
OddDuring a write address WA, each channel of numerical data IN all is written in the corresponding positions of voice path register 1.Therefore, in the voice path register, produce a continuous write operation.For example, numerical data IN is on input data high-speed path, and wherein each channel is multiplexed with the frame with 125 microseconds by 8 data and " n " channel of a check digit formation.Therefore, each channel data of numerical data IN is sequentially written in the voice path register assigned address and is " 0 ", and " 1 " ... the position of " n-1 ".
On the other hand, read address counter 3 produces a continuous address RA1 that reads, and to the control register 4 of sending, and control register 4 according to content with this continuous read address RA1 convert at random read address RA2.Therefore, in voice path register 1, produce a read operation at random.
In more detail, in control register 4, write the amount of relation of an input time slot and output time solt in advance by CPU (CPU).That is to say, when CPU when control register 4 provides a write address WA0, correspondingly have one to read address RA0 and be written in the control register 4 by the specified position of write address WA0.Therefore, when read address counter 3 provides one to read address RA1 to control register 4, and control register 4 is to input terminal R
AddWhen providing one to read address RA2, the data of relevant position are just read on the dateout high speed channel from voice path register 1.
Therefore, " n " input channel of a sequence can be converted into " n " delivery channel of a sequence.
The operation of single buffer types time division multiplexing switch shown in Figure 1A is explained with reference to Figure 1B.At this, suppose " 3 ", " 2 ", " 0 " and " 1 " have been write respectively in the control register 4 in advance by address " 0 ", " 1 ", " 2 " and " 3 " specified position.
At first, corresponding to time slot " 0 ", " 1 ", and the voice data A0 of " 2 " and " 3 ", B0, C0 and D0 are write in the voice path register 1 by input data high-speed path in proper order by the content according to write address counter 2.
On the other hand, corresponding to output time solt " 0 ", " 1 ", and " 2 " and " 3 " voice data D0, C0, A1 and B1 are read into the dateout high speed channel by voice path register 1.At this moment, the write timing of voice path register 2 just depends on maximum time slot with the difference of reading timing.And, because being the address RA2 that reads by control register 4, read operation carries out, just be equal to the maximum delay of a frame, i.e. 125 μ s time of delay by the voice data of voice path register 1.
In the single buffer types time division multiplexing switch shown in Figure 1A, although the time of delay of voice data is very little, but, therefore, may keep the interframe time slot sequence integrity hardly owing to be that the address RA2 that reads by control register 4 carries out at random to the read operation of voice path register 1.For example, shown in Figure 1B, if a frame is by voice data A0, B0, C0 and D0 form, and another frame is by voice data A1, B1, C1 and D1 form, and then when the time slot " 3 " (or address " 3 ") of voice path register 1, might carry out a read operation to voice data D0 before voice data D1 is written into.Therefore, can not read voice data according to the order of frame.Especially when data were strict with according to interframe order rather than voice data transmission, misdata just may be transmitted.
Fig. 2 A has demonstrated the double buffering type time division multiplexing switch of prior art.Wherein, do not resemble and have only a voice path register 1 among Figure 1A, but two voice path register 1a and 1b are arranged, and on the basis of Figure 1A, increased a multiplexer 5.The frame signal that voice path register 1a and 1b and multiplexer 5 are 8KHz by a frequency is switched.For example,, then voice path register 1a is carried out write operation, and voice path register 1b is carried out read operation, and multiplexer 5 is selected speech road register 1b if frame signal is at first state.On the other hand,, then voice path register 1b is carried out write operation, and voice path register 1a is carried out read operation, and multiplexer 5 is selected speech road register 1a if frame signal is at second state.
The operation of the time division multiplexing of double buffering type shown in Fig. 2 A switch is explained with reference to Fig. 2 B and 2C.At this, suppose " 3 ", " 2 ", " 0 " and " 1 " have been write respectively in the control register 4 in advance by address " 0 ", " 1 ", " 2 " and " 3 " specified position.
Fig. 2 B has demonstrated an example when frame signal is in first state.That is to say, corresponding to output time solt " 0 ", " 1 ", the voice data D0 of " 2 " and " 3 ", C0, A0 and B0 are read into output data path from voice path register 1b, and corresponding to input time slot " 0 ", " 1 ", the voice data A1 of " 2 " and " 3 ", B1, C1 and D1 are written to voice path register 1a from the input data path.
Fig. 2 C has demonstrated an example when frame signal is in second state.That is to say, corresponding to output time solt " 0 ", " 1 ", the voice data D1 of " 2 " and " 3 ", C1, A1 and B1 are read into output data path by voice path register 1a, and corresponding to input time slot " 0 ", " 1 ", the voice data A2 of " 2 " and " 3 ", B2, C2 and D2 are written to voice path register 1b by the input data path.
State shown in Fig. 2 B and the 2C alternately repeats, so all frame voice datas can both be read output data path from voice path register 1a and 1b.Therefore, the time slot sequence integrity of interframe can be guaranteed.
, very big by the time of delay of voice path register 1a and 1b in the time division multiplexing of double buffering type shown in Fig. 2 A switch, for example, be 125 μ s to a frame, be 250 μ s to two frames.That is to say that be the twice in single buffer types time division multiplexing switch shown in Figure 1A the time of delay in the time division multiplexing of double buffering type shown in Fig. 2 A switch.
Fig. 3 has demonstrated first embodiment according to time division multiplexing switch of the present invention, the switch of double buffering type time division multiplexing shown in single buffer types time division multiplexing switch and Fig. 2 A shown in Figure 1A, by with from the selection control bit SCB of CPU consistent time slot control.And the control register 4 among Fig. 2 A is modified and is control register 4 ', and it can be stored according to write address WA0 and select control bit SCB.Further, provide a selection control register 6, be used for storing selection control bit SCB according to reading address RA0.
When the write address WA according to write address counter 2 read in a selection control bit SCB1 from selecting control register 6, this selection control bit SCB1 can control a multiplexer 7a, and then the write operation of control voice path register 1a.On the other hand, when reading in one when selecting control bit SCB2 according to reading address RA1 from control register 4 ', this selections control bit SCB2 can control a multiplexer 7b, and then controls the read operation of multiplexers 5 and voice path register 1a by OR circuit 8.
Below the operation of time division multiplexing switch shown in Figure 3 is given to explain.
When all being " 0 " by selection control bit SCB1 that selects control register 6 to be read and selection control bit SCB2, multiplexer 7a and 7b select frame signal.Therefore, the read-write operation of voice path register 1a and voice path register 1b all can alternately be carried out.And because frame signal is passed through OR circuit 8, multiplexer 5 selects one of voice path register 1a and 1b to carry out read operation.Therefore, double buffering type time division multiplexing switch is achieved.
On the other hand, when all being " 1 " by selection control bit SCB1 that selects control register 6 to be read and selection control bit SCB2, multiplexer 7a and 7b select " 0 ".Therefore, voice path register 1a is compelled to be in the Writing/Reading state.And owing to select control signal SCB2 by OR circuit 8, multiplexer 5 total voice paths of selecting are deposited 1a.
Therefore, single buffer types time division multiplexing switch is achieved.
Fig. 4 has demonstrated second embodiment according to time division multiplexing switch of the present invention, and the control register 4 ' among Fig. 3 is modified and is control register 4 ", wherein introduced the selection control register 6 among Fig. 3.So, write address WA0 and read the address, select control bit SCB all to be provided for control register 4 " port one; And read address RA1 by reception, read address RA2 and select control bit SCB2 by from control register 4 " port 2 read.On the other hand, read address RA0 and select control bit SCB to be provided for control register 4 " port 3, simultaneously,, select control bit SBC1 by from control register 4 by receiving write address WA " port 4 read.
Because the selection control register 6 among Fig. 3 is omitted in Fig. 4, therefore, with respect to Fig. 3, the hardware of the time division multiplexing switch among Fig. 4 is simplified.
Fig. 5 has demonstrated the 3rd embodiment according to time division multiplexing switch of the present invention, the control register 4 among Fig. 4 " be modified and be control register 4 , it has only a single Writing/Reading terminal.In the multiplexer 9a and the 9b that have provided by CPU control.When multiplexer 9b selects write address WA0, multiplexer 9a will read address RA0 and select control bit SCB (=SCB2) carry out compoundly, and write control register 4 .When multiplexer 9b selects to read address RA0, multiplexer 9a selection control bit SCB (=SCB1), and write control register 4 .When multiplexer 9b selects write address WA, then from control register 4 , read in and select control bit SCB1.When multiplexer 9b selects to read address RA1, then from control register 4 , read in address RA2 and select control bit SCB2.Therefore, with respect to Fig. 4, the hardware of the time division multiplexing switch among Fig. 5 is simplified.
Fig. 6 has demonstrated the 4th embodiment according to time division multiplexing switch of the present invention, control register 4 ' among Fig. 3 is replaced by the control register among Fig. 2 A 4, and write address WA and read address RA2 by multiplexer 13 be provided for select control register 6 read End of Address R
AddMultiplexer 13 is by write address counter 2 controls.
In Fig. 6, be provided for multiplexer 7a and 7b together by the selection control bit SCB1 that selects control register 6 to read, and offer multiplexer 5 by OR circuit 8.Therefore, the write and read time of data can be simplified.And since the control register among Fig. 64 does not require the selection control bit SCB from CPU, with respect to the control register 4 ' of Fig. 3, control register 4 is simplified.Therefore, with respect to Fig. 3, the hardware of the time division multiplexing switch among Fig. 6 is simplified.
In sum, according to certain alternative condition, time division multiplexing switch according to the present invention can be used as a single buffer types or a pair of buffer types time division multiplexing switch is operated.If transmit the voice data that does not need the interframe time slot sequence integrity, then select single buffer types, so be reduced the time of delay of voice data.On the other hand, if transmit the data that require the interframe time slot sequence integrity, then select the double buffering type, even now can increase the time of delay of data.
Claims (7)
1. a time division multiplexing switch comprises
The first and second voice path registers (1a, 1b);
One write address counter (2) is connected with the described first and second voice path registers, is used for producing continuously a write address (WA) and transmits described write address to the described first and second voice path registers;
One control register (4,4 ', 4 ", 4 ), be connected with the described first and second voice path registers, be used for producing at random one and read address (RA2) and transmit the described address of reading to the described first and second voice path registers; With
Operation control circuit (5,7a, 7b, 8), be connected with the described first and second voice path registers,, only the described first voice path register operated at second state so that the described first and second voice path registers are operated at first state.
2. switch as claimed in claim 1, the described first and second voice path registers are alternately carried out a write operation and a read operation in each frame.
3. switch as claimed in claim 1, one of described first and second states be for each time slot of data specified.
4. switch as claimed in claim 1 further comprises:
One first control selects the position to produce circuit (6; 4 " 4 ), be connected with described write address counter and described operation control circuit, be used for producing one first and select control bit signal (SCB1) according to described write address, and to the described operation control circuit of sending, thus, the described first voice path register is forced to be in the write operation state; With
One second control selects the position to produce circuit (6; 4 " 4 ), be connected with described operation control circuit, be used for producing one second selection control bit signal (SCB2), and to the described operation control circuit of send according to the described address (RA1) of reading, thus, the described first voice path register is forced to be in the read operation state, and it is effective having only the data of reading from the described first voice path register.
5. switch as claimed in claim 4, described first control select position generation circuit to comprise that one selects control register 6, and described control register has merged described second and selected control bit to produce circuit.
6. switch as claimed in claim 4, described control register have merged described first and second controls and have selected the position to produce circuit.
7. switch as claimed in claim 4 further comprises:
One selects control register, has merged described first and second and has selected control bit to produce circuit; With
One multiplexer (13), be connected with described write address counter, described control register and described selection control register, be used to select described write address and described one of the address of reading, and transmit described write address and described one of the address of reading to described selection control register.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9275822A JPH11113078A (en) | 1997-10-08 | 1997-10-08 | Time multiplex switch |
| JP275822/97 | 1997-10-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1215291A true CN1215291A (en) | 1999-04-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98120132A Pending CN1215291A (en) | 1997-10-08 | 1998-10-07 | Time division multiplexting switch with single and double buffer ability |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH11113078A (en) |
| KR (1) | KR19990036939A (en) |
| CN (1) | CN1215291A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5348263B2 (en) * | 2012-02-29 | 2013-11-20 | 富士通株式会社 | Data transmission apparatus, data transmission system, and data transmission method |
-
1997
- 1997-10-08 JP JP9275822A patent/JPH11113078A/en active Pending
-
1998
- 1998-10-07 CN CN98120132A patent/CN1215291A/en active Pending
- 1998-10-08 KR KR1019980041996A patent/KR19990036939A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990036939A (en) | 1999-05-25 |
| JPH11113078A (en) | 1999-04-23 |
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