CN1210365A - 能改善平面化的半导体器件的制造方法 - Google Patents

能改善平面化的半导体器件的制造方法 Download PDF

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CN1210365A
CN1210365A CN98117446A CN98117446A CN1210365A CN 1210365 A CN1210365 A CN 1210365A CN 98117446 A CN98117446 A CN 98117446A CN 98117446 A CN98117446 A CN 98117446A CN 1210365 A CN1210365 A CN 1210365A
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金昶圭
洪锡智
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Samsung Electronics Co Ltd
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Abstract

公开了一种制造半导体器件的方法,通过在DRAM单元区内形成电容并在平面化之前淀积第一绝缘层之后在逻辑区内形成高度与电容类似的金属互连能使DRAM和逻辑区之间的台阶最小化。虽然第二绝缘层淀积在衬底上,但由于在逻辑区内形成金属互连可以使DRAM单元区和逻辑区之间的台阶最小化。由此,虽然仅使用CMP或深腐蚀工艺,可以进行第二绝缘层的平面化。

Description

能改善平面化的半导体器件的制造方法
本发明涉及在同一晶片上形成有存储器件和逻辑器件的半导体器件的制造方法，特别涉及在形成存储器件的存储单元区域和形成逻辑器件的逻辑区之间能改善平面化的半导体器件的制造方法。
随着半导体器件集成度的增加，进一步要求形成在半导体晶片或衬底上绝缘层的平面化技术确保光刻裕度并将金属互连的长度最小化。要平面化绝缘层，特别是层间绝缘层，现已使用有几种方法，例如回流如BPSG(硼磷硅玻璃)的方法、SOG(旋涂玻璃)工艺、在绝缘层上淀积光刻胶后进行深腐蚀工艺、用于平面化淀积的绝缘层的CMP(化学机械抛光)工艺等。在这些方法中，CMP工艺能允许回流工艺或深腐蚀工艺不能达到的低温平面化，因此该CMP工艺已广泛用于衬底平面化中。
下面参考图1介绍具有DRAM(动态随机存储器)单元区和逻辑区的半导体器件的常规制造方法。
参考图1，首先，包括栅12的晶体管形成在具有由场氧化物限定的器件隔离的半导体衬底10上。电容14直接与衬底10接触地形成，并由侧壁间隔层13a和形成在栅12上的帽盖绝缘层13b绝缘。接下来，进行绝缘体淀积和CMP工艺形成具有平面化表面的绝缘层15。穿通平面化的绝缘层15形成接触孔后，钨塞16a填充接触孔，然后形成互连17a与钨塞16a电连接。
随后，再次进行绝缘体淀积和CMP工艺以及栓和互连形成工艺形成穿通绝缘层18的钨塞16b并在钨塞16b上形成互连17b。
如上面刚介绍的，由于在形成电容之前场氧化物11和栅12同时形成在DRAM单元区和逻辑区，所以在器件之间没有产生高台阶。然而，形成电容后，由于电容14仅形成在DRAM单元区，因此DRAM单元区和逻辑区之间的台阶很高。由此，当形成电容15后淀积绝缘层15时，应进行以上提到的CMP工艺以得到平坦表面的绝缘层15。这样会导致一个严重的问题即由于与抛光垫直接接触的部分衬底和衬底的其它表面之间的压力差发生与抛光垫不均匀的抛光引起的凹陷现象。
要抑制凹陷，需要使用两个抛光步骤：使用光刻胶的深腐蚀和CMP。首先，进行使用光刻胶的深腐蚀工艺除去在高台阶区内一定量的绝缘层，然后进行CMP工艺平面化衬底的整个表面。
然而，这种方法有两个缺点：一个是衬底平面化中的多个步骤减少了生产率，另一个是由于在抛光过程中使用了光刻胶的深腐蚀产生了大量的颗粒。
本发明意在解决以上问题，本发明的一个目的是提供一种半导体器件的制造方法，通过在DRAM单元区内形成电容并在逻辑区内形成其高度与电容类似的金属互连能使DRAM和逻辑区之间的台阶最小化。
要得到以上目的，具有由DRAM单元区和逻辑区限定的衬底的半导体器件的制造方法包括步骤：在半导体衬底的存储单元区内形成电容；在半导体衬底上形成第一绝缘层，在半导体衬底的存储单元和逻辑区内局部地平面化所述第一绝缘层；在逻辑区内形成金属图形层，所述金属图形层与半导体衬底直接接触并且其高度与电容类似；在包括第一绝缘层和金属图形层的半导体衬底上形成第二绝缘层；以及平面化第二绝缘层。
通过参考下面的附图，对本领域的技术人员来说本发明将易理解并且本发明的目的将很显然。
图1为衬底由DRAM单元区和逻辑区限定的常规半导体器件的局部剖面图；以及
图2A到2D示出了根据本发明的一个实施例制造半导体器件的一个新颖方法的工艺步骤剖面图。
下面参考示出一个实施例的附图详细地介绍本发明。
参考图2A，器件隔离由场氧化物21限定的半导体器件的衬底20由DRAM和逻辑区限定。包括栅22的晶体管形成在DRAM和逻辑区内的半导体衬底20上。电容24直接与衬底20接触地形成，并由侧壁间隔层23a和形成在栅22上的帽盖绝缘层23b绝缘。这里应该注意电容24形成在DRAM单元区内而不是逻辑区内的事实导致了区之间的高台阶。
接下来，如图2B所示，通过淀积O3-TEOS USG(未掺杂的硅酸盐玻璃)层后使用深腐蚀、SOG深腐蚀、BPSG回流工艺等在衬底上形成第一绝缘层25。局部平面化每个区后，金属互连26即高度与电容类似的金属图形穿过形成在逻辑区的第一绝缘层25内的接触孔与衬底接触地形成。这里，我们可以看出DRAM和逻辑区之间的平面化不能通过第一绝缘层25进行，但可以在各区域内进行局部平面化。
通过下面的步骤形成金属图形26。
首先，进行选择性的腐蚀工艺形成接触孔。接下来，如Ti/TiN(未显示)层的阻挡金属层淀积在接触孔的底部，然后进行铝回流工艺。构图回流的铝层形成金属图形26。另外，在本领域形成钨塞的公知工艺也适用于形成金属图形26。
随后，在图2C中，如SOG层的第二绝缘层27形成在包括金属图形26和第一绝缘层25的衬底上，然后进行平面化工艺。仅通过CMP或深腐蚀可以获得第二绝缘层27的平面化。当SOG层用做第二绝缘层时，在本实施例优选使用深腐蚀。
接下来，如图2D所示，在DRAM单元区内和金属图形26上形成接触孔，然后用钨材料填满接触孔形成钨塞28。最后，金属互连形成在钨塞28上。所得的钨塞28同时形成在DRAM和逻辑区内。
如上所述，虽然在DRAM单元区内形成电容后在DRAM和逻辑区之间存在高台阶，但通过在逻辑区内形成金属图形可以使两者之间的台阶最小化，其中逻辑区内金属图形的高度类似于电容的高度，并直接与衬底接触。因此，接下来形成在电容和金属图形上的绝缘层的平面化工艺得到简化。

Claims (6)

1．一种制造半导体器件的方法，其中衬底由存储单元区和逻辑区限定，包括步骤：
在半导体衬底的存储单元区内形成电容；
在半导体衬底上形成第一绝缘层，在半导体衬底的存储单元区和逻辑区内局部地平面化所述第一绝缘层；
在逻辑区内形成金属图形层，所述金属图形层与半导体衬底直接接触并且其高度与电容类似；
在包括第一绝缘层和金属图形层的半导体衬底上形成第二绝缘层；以及
平面化第二绝缘层。
2．根据权利要求1的方法，其中形成第一绝缘层的步骤包括在含有电容的半导体衬底上形成O3-TEOS USG未掺杂的硅酸盐玻璃层，和深腐蚀O3-TEOS USG未掺杂的硅酸盐玻璃层。
3．根据权利要求1的方法，其中形成第一绝缘层的步骤包括在含有电容的半导体衬底上形成包括SOG层的绝缘层，和深腐蚀包括SOG层的绝缘层。
4．根据权利要求1的方法，其中第一绝缘层步骤形成回流的BPSG层。
5．根据权利要求1或4的方法，其中通过CMP工艺进行平面化第二绝缘层的步骤。
6．根据权利要求1或4的方法，其中第二绝缘层由SOG层制成，并且其中通过深腐蚀工艺进行平面化第二绝缘层的步骤。
CN98117446A 1997-08-28 1998-08-28 能改善平面化的半导体器件的制造方法 Expired - Fee Related CN1107346C (zh)

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US7317208B2 (en) * 2002-03-07 2008-01-08 Samsung Electronics Co., Ltd. Semiconductor device with contact structure and manufacturing method thereof
JP2004045576A (ja) * 2002-07-09 2004-02-12 Sharp Corp 液晶表示装置及びその製造方法
JP2005026313A (ja) * 2003-06-30 2005-01-27 Shinko Electric Ind Co Ltd 配線基板の製造方法
US6906908B1 (en) * 2004-05-20 2005-06-14 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
KR100624566B1 (ko) * 2004-05-31 2006-09-19 주식회사 하이닉스반도체 커패시터 상부에 유동성 절연막을 갖는 반도체소자 및 그제조 방법
US20150206794A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Removing Micro Scratches In Chemical Mechanical Polishing Processes

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