CN1181618A - 网格焊球阵列封装的外部管脚制造方法 - Google Patents
网格焊球阵列封装的外部管脚制造方法 Download PDFInfo
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Abstract
一种用于网格球形阵列(BGA)半导体封装的外部管脚制造方法,它能够直接地在衬底上形成一凸起状金属,包含步骤:在衬底的上表面形成了数目众多的相互之间以一定的间隔而分布的导电支柱;在该衬底上形成一光致抗蚀剂薄膜;穿过该光致抗蚀剂薄膜暴露各相应的支柱;在每一个该暴露出的支柱的上面形成一导电凸起部分;以及清除残留在该衬底上面的光致抗蚀剂薄膜。
Description
本发明涉及一种半导体器件封装制造方法,尤其是涉及一种用网格焊球阵列(BGA)封装的外部管脚制造方法,当形成作为BGA封装的用作焊球的外部引线时,通过直接在衬底上镀敷凸起状金属,能够省去需要安装球形管脚的步骤。
如图1所示,在常规的BGA封装中,已经提供了许多用金属铜构成的内部引线2,并且它们穿过衬底1以连接该衬底1的上表面和下表面,数目众多的焊接指2a形成于内部引线2的相应的上面部分,管芯焊盘3安装在衬底1的表面。使用粘结剂将半导体芯片4连接在管芯焊盘3的上面,通过金属线6内部引线2的焊接指2a分别连接至芯片4的焊盘上,在芯片4和金属线6的周围已经形成一个模制单元7,它通过使用环氧树脂覆盖着衬底1上的某一区域。为数众多的焊球8连接至相应的铜支柱10,铜支柱10形成于位于衬底1的下表面处的相应内部引线2的下端,并且通过相应的穿过衬底1的内部引线2电连接至芯片4。
象这样构成的常规BGA封装可通过下列步骤制造出。
首先,通过图型化一薄印刷电路板(PCB)并通过对该图型化部分进行冲孔,数目众多的通孔即形成于衬底中以便制造出一封装基片。许多带有在此形成的通孔的PCB板被叠加在一起,于是通过填塞铜金属至相应的通孔中以连接衬底1的上表面和下表面,具有在此穿过的内部引线2的衬底1即被形成。
其次,其上胶粘有粘结盘5的管芯焊盘3安装在衬底1上,衬底1具有穿过其中的内部引线2,并且进行模片键合用来将芯片4连接至粘结剂5上。
使用金属线6进行线焊接以便将形成于芯片4上的相应焊盘(未示出)与相应的形成于内部引线2的相应上端的焊接指2a相连接。
为保护芯片4和金属线6免受外部损坏,使用环氧树脂模制化合物在此形成了模制单元7。
为了使铜支柱10与位于衬底1下表面处的焊球8能够更好地粘合,已经实行一个焊剂处理步骤以便将焊膏分布在衬底1的上面。
衬底1与焊球安装器件(未示出)之间的位置已经调节好,焊球8因而易被安装好。在装配完焊球8之后,清除焊料残余物,进行回流处理步骤以整平这些焊球,并且使用乙醇,丙酮或者类似的溶剂,该衬底的表面即被清洗干净,因此便完成了BGA的封装制造过程。
尽管如此,在常规的BGA封装制造方法中,在将焊球8安装在衬底1的下表面的焊球安装步骤期间,调整好衬底与焊球安装器件(未未出)之间适当的位置是很困难的,所以对于位于内部引线2的相应下端的铜支柱10来讲,焊球并没有精确地安装在理想的位置上,并且在内部引线2和焊球(外部引线)8之间会因此而发生连接错误,或者是在焊球装配完之后,在焊球8与内部引线2之间会出现粘合不良,因而导致焊球与外部引线的脱离。另外,还需要一个价格昂贵的焊球安装器件,它增加了生产成本。
另外,焊球的标准直径是0.76mm,因而在焊球的最小化尺寸方面存在一个限度,而且如果在高密度多管脚结构的半导体封装的情况下,它的应用已经变得更加困难。
因此,本发明的第一目的在于提供一种用于网格球形阵列(BGA)封装的外部管脚制造方法,通过直接在衬底上镀敷凸起状金属而不是将焊球安装在衬底上的方法,以在BGA封装中消除容易引起故障的因素。
本发明的第二目的在于提供一种用于BGA封装的外部管脚制造方法,因为不需要价格昂贵的焊球安装设备,所以它能够降低生产成本。
本发明的第三目的在于提供一种用于BGA封装的外部管脚制造方法,由于能够使得凸起状金属的平均直径小于0.76mm,所以该方法能适用于多管脚结构的BGA封装。
为了达到上述目的,已经提供了一种用于BGA封装的外部管脚制造方法,它包含步骤:在衬底的上表面形成多个相互之间以一定的间隔而分布的导电支柱(凸台);在该衬底的上表面形成一光致抗蚀剂薄膜;穿透该光致抗蚀剂薄膜暴露各相应的导电凸台(支柱);在每个暴露的凸台上面形成一导电的凸起部分;以及清除衬底上面剩余的光致抗蚀剂薄膜。
图1是常规BGA封装的示意剖面图;
图2A至2F是反映依据本发明的第一实施方案的用于BGA封装的衬底形成方法的工艺过程示意图;以及
图3A至3F是反映依据本发明的第二实施方案的用于BGA封装的衬底形成方法的工艺过程示意图。
参照附图,现在将要描述用于BGA封装的外部管脚制造方法。
图2A-F中所显示的主要是反映依据本发明的第一实施方案的用于BGA封装的制造方法的工艺过程示意图。首先提供一种已制备好的并且具有许多在其中穿过的内部引线2的PCB衬底1,如图2A所示,在衬底1的上表面形成了许多具有大约10~50μm的厚度的铜支柱122,其中通过应用一种众所周知的PCB电路图型化制作工艺,暴露内部引线2。
接着,如图2B所示,在具有铜支柱122的衬底1的顶部分布一层其厚度是50~100μm的光致抗蚀剂薄膜123。
然后,如图2C所示,通过实行一种公知的光刻工艺,清除覆盖在铜支柱122上面的该光致抗蚀剂薄膜123,因而暴露出这些铜支柱122。
如图2D所示,使用一种非电解电镀工艺,一层铜金属层被镀敷在所暴露的铜支柱122的上面以便形成为数众多的凸起部分124,此时,当外部管脚之间的间距大约为1.27mm时,凸起部分124的直径被形成为250~700μm,以防止相邻的凸起部分124相互跨接,同样,当安装已经成型的BGA封装器件时,在某一装配温度下,在凸起部分熔化之后,应该考虑一较低的安装高度,凸起部分124的理想高度是100~700μm。依据基于电镀反应速度的反应时间,凸起部分124的高度是可以控制的。
如图2F所示,光致抗蚀剂薄膜123的剩余部分从衬底1上清除掉,并且Ni层125a被镀敷在金属铜凸起部分124的表面,其厚度达5~30μm,此后,在电镀Ni层125a的顶部,已经镀敷一层Au,其厚度小于5μm,以便在PCB(未示出)板安装时提高其粘合力。
也就是说,作为BGA封装器件的外部管脚的凸起部分124已经被形成,并且在衬底1相反的那一边已经安装好模板3,其上分布有粘结剂5,然后进行模片键合以便将芯片4粘接在那里,实行线焊接步骤以便用金属线6将芯片4的焊盘与位于内部引线2的相应末端部分的焊接指2a相连接,因此芯片4即与外部管脚8相电连接,并且一环氧树脂化合物已经被模制成围绕着金属线6和芯片4,这样即完成了BGA封装的制造过程。
如图3A-3F中所示,它反映依据本发明的第二实施方案的用于BGA封装的外部管脚制造方法,通过使用一种共知的PCB构图制作工艺,在具有许多穿过其中的内部引线2的衬底1的上面形成了多个的铜支柱222,在衬底1上形成了一层光致抗蚀剂薄膜223,然后使用一种光刻工艺,清除掉光致抗蚀剂薄膜223形成并覆盖在铜支柱222上面的那一部分,从而暴露出支柱222。一种焊料(so1der)被镀敷在所暴露的铜支柱222的上面以形成凸起部分224,衬底1上面剩余的光致抗蚀剂薄膜被全部清除掉,并且该焊接物凸起部分224被实行回流以形成锥球形状的管脚。理想的衬底1由PCB或者是由一种陶瓷材料来制作成,它具有超过300℃的熔点。当进行装配时,在某一安装温度下,焊接物凸起部分124的凸起高度变得很低,所以值得推荐的是采用一种Sn与Pb之比率为90∶10到80∶20且具有较高熔点的焊料而不采用Sn与Pb之比为63至37的焊膏,因此而防止相邻管脚之间的搭接。
如上所述,在依据本发明的用于BGA封装的外部管脚制造方法中,采用了一种球形管脚制作工艺,所以常规的球形管脚安装过程可以省略,从而消除了故障部分,如在焊球的装配过程中,由于不精确的配合,在内部端子与外部管脚之间会出现故障连接;或者是在衬底与焊球之间,由于粘合不良,会出现外部引线的局部脱离,因此而提高了半导体封装制造的生产率。
另外,由于消除了对高价格焊球安装器件的需要,依据本发明的半导体封装能够以较低的成本制造出。
Claims (11)
1.一种用于网格球形阵列(BGA)半导体封装的外部管脚制造方法,其特征在于,包含步骤:
在一衬底的上表面形成多个相互之间以一定间隔分布的导电支柱;
在所述衬底上面形成一层光致抗蚀剂薄膜;
穿过所述光致抗蚀剂薄膜,暴露所述相应的支柱;
在所述的每个被暴露的支柱上面形成一导电凸起物;以及
清除所述衬底上面剩余的所述光致抗蚀剂薄膜。
2.如权利要求1所述的方法,其特征在于,所述凸起物由非电解工艺过程形成。
3.如权利要求1所述的方法,其特征在于,所述支柱由金属铜制成。
4.如权利要求1所述的方法,其特征在于,所述凸起物其高度为100~700μm,并且其直径为250~700μm。
5.如权利要求1所述的方法,其特征在于,所述凸起物由金属铜制成。
6.如权利要求5所述的方法,其特征在于,在所述凸起物的被暴露表面依次形成了一层镍和一层金。
7.如权利要求6所述的方法,其特征在于,所述镍层和所述金层由一电镀工艺过程来形成。
8.如权利要求1所述的方法,其特征在于,所述凸起物由一焊料制成。
9.如权利要求8所述的方法,其特征在于,在形成所述凸起物之后,执行一回流过程。
10.如权利要求8所述的方法,其特征在于,所述衬底由一印刷电路板和一陶瓷材料组成,并具有一超过300℃的熔点。
11.如权利要求8所述的方法,其特征在于,在所述凸起物中,比率Sn∶Pb的比值范围是从90∶10到80∶20。
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KR1019960049456A KR100234694B1 (ko) | 1996-10-29 | 1996-10-29 | 비지에이 패키지의 제조방법 |
KR49456/96 | 1996-10-29 |
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CN1181618A true CN1181618A (zh) | 1998-05-13 |
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CN97103772A Pending CN1181618A (zh) | 1996-10-29 | 1997-04-14 | 网格焊球阵列封装的外部管脚制造方法 |
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US (1) | US5895231A (zh) |
JP (1) | JPH10135366A (zh) |
KR (1) | KR100234694B1 (zh) |
CN (1) | CN1181618A (zh) |
DE (1) | DE19715926B4 (zh) |
Cited By (1)
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CN100340962C (zh) * | 2004-06-15 | 2007-10-03 | 日月光半导体制造股份有限公司 | 触摸传感封装构造 |
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JP4428832B2 (ja) * | 1999-08-27 | 2010-03-10 | 富士通株式会社 | 金属配線構造、半導体装置及び半導体装置の製造方法 |
SG99877A1 (en) * | 2001-01-04 | 2003-11-27 | Inst Materials Research & Eng | Forming an electrical contact on an electronic component |
JP2003264260A (ja) * | 2002-03-08 | 2003-09-19 | Toshiba Corp | 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板 |
CN100474539C (zh) * | 2002-03-12 | 2009-04-01 | 费查尔德半导体有限公司 | 晶片级涂覆的铜柱状凸起 |
US20040007779A1 (en) * | 2002-07-15 | 2004-01-15 | Diane Arbuthnot | Wafer-level method for fine-pitch, high aspect ratio chip interconnect |
JP3721175B2 (ja) * | 2003-06-03 | 2005-11-30 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US7417220B2 (en) * | 2004-09-09 | 2008-08-26 | Toyoda Gosei Co., Ltd. | Solid state device and light-emitting element |
DE102008042107A1 (de) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Elektronisches Bauteil sowie Verfahren zu seiner Herstellung |
JP5642473B2 (ja) * | 2010-09-22 | 2014-12-17 | セイコーインスツル株式会社 | Bga半導体パッケージおよびその製造方法 |
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JP2721580B2 (ja) * | 1990-05-17 | 1998-03-04 | シャープ株式会社 | 半導体装置の製造方法 |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
SG49779A1 (en) * | 1993-11-26 | 1998-06-15 | Delco Electronics Corp | Method of forming solder bumps on an integrated circuit flip chip |
US5508229A (en) * | 1994-05-24 | 1996-04-16 | National Semiconductor Corporation | Method for forming solder bumps in semiconductor devices |
US5466635A (en) * | 1994-06-02 | 1995-11-14 | Lsi Logic Corporation | Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
JP3199963B2 (ja) * | 1994-10-06 | 2001-08-20 | 株式会社東芝 | 半導体装置の製造方法 |
US5646068A (en) * | 1995-02-03 | 1997-07-08 | Texas Instruments Incorporated | Solder bump transfer for microelectronics packaging and assembly |
JPH08250827A (ja) * | 1995-03-08 | 1996-09-27 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその製造方法並びに半導体装置 |
US5639696A (en) * | 1996-01-31 | 1997-06-17 | Lsi Logic Corporation | Microelectronic integrated circuit mounted on circuit board with solder column grid array interconnection, and method of fabricating the solder column grid array |
-
1996
- 1996-10-29 KR KR1019960049456A patent/KR100234694B1/ko not_active IP Right Cessation
-
1997
- 1997-04-14 CN CN97103772A patent/CN1181618A/zh active Pending
- 1997-04-16 DE DE1997115926 patent/DE19715926B4/de not_active Expired - Fee Related
- 1997-10-23 JP JP29076597A patent/JPH10135366A/ja active Pending
- 1997-10-29 US US08/960,210 patent/US5895231A/en not_active Expired - Fee Related
Cited By (1)
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CN100340962C (zh) * | 2004-06-15 | 2007-10-03 | 日月光半导体制造股份有限公司 | 触摸传感封装构造 |
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Publication number | Publication date |
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KR100234694B1 (ko) | 1999-12-15 |
US5895231A (en) | 1999-04-20 |
DE19715926B4 (de) | 2004-09-23 |
DE19715926A1 (de) | 1998-05-07 |
KR19980030097A (ko) | 1998-07-25 |
JPH10135366A (ja) | 1998-05-22 |
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