CN101060087A - 电极及其制造方法,以及具有该电极的半导体器件 - Google Patents

电极及其制造方法,以及具有该电极的半导体器件 Download PDF

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Publication number
CN101060087A
CN101060087A CNA2007100961494A CN200710096149A CN101060087A CN 101060087 A CN101060087 A CN 101060087A CN A2007100961494 A CNA2007100961494 A CN A2007100961494A CN 200710096149 A CN200710096149 A CN 200710096149A CN 101060087 A CN101060087 A CN 101060087A
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China
Prior art keywords
electrode
pad
encapsulation
metallic plate
metal column
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CNA2007100961494A
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山口昌浩
中村博文
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Nec Toppan Electric Substrate Co Ltd
Micron Memory Japan Ltd
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Nec Toppan Electric Substrate Co Ltd
Elpida Memory Inc
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Application filed by Nec Toppan Electric Substrate Co Ltd, Elpida Memory Inc filed Critical Nec Toppan Electric Substrate Co Ltd
Publication of CN101060087A publication Critical patent/CN101060087A/zh
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Abstract

通过刻蚀金属板形成金属柱。因此，金属柱可以形成有精确的高度和精细间距。通过使用上封装中形成的金属柱将上和下封装连接在一起，能够获得具有精细电极间距的小型化半导体器件。

Description

电极及其制造方法，以及具有该电极的半导体器件
本申请要求在先的日本专利申请JP2006-113195的优先权，在此将其公开内容引入供参考。
背景技术
本发明涉及一种半导体器件的电极，具体地，涉及用于PoP结构(Package-on-Package)的电极，其中安装有半导体元件的封装被层叠在一起，还涉及这种电极的制造方法以及具有这种电极的半导体器件。
近年来，半导体器件的速度和容量增加，此外，为了电子***的微型化，半导体器件封装已被小型化。特别，在便携式器件中，封装的小型化是重要的，并且，每个具有安装在一个封装中的多个半导体芯片的那些半导体器件已经被采用至今。作为这些半导体器件，已经提出了具有在封装中层叠多个半导体芯片的MCP(多芯片封装)和其中多个CSP(芯片尺寸封装)被层叠在一起的PoP(Package-on-Package)器件。此外，倒装芯片键合方法等等被用作除常规引线键合方法以外的半导体芯片连接方法，其中倒装芯片键合方法使用形成为凸块的键合焊盘。这使之可以获得半导体器件的小型化。
图3是具有常规PoP结构的半导体器件的剖面图。在所示的半导体器件中，上封装具有树脂密封的半导体芯片9-1和9-2，并且在它们的焊盘3处通过焊球16-2连接到下封装。具体地，下封装安装有半导体芯片9-3，并且具有在其上部的连接焊盘3和在其底部设置的焊球16-1。半导体芯片9-1和9-2被安装在上封装的上部，并通过引线键合连接到上封装板的电极。在上封装的底侧形成用于连接下封装的焊盘3。
在该PoP结构中，为了将上和下封装连接在一起，必须保证下封装中安装的半导体芯片9-3的高度所需要的空间或间隙(间隔)。该间隔由焊球的高度保持。但是，由于焊球的球形由焊料本身的物理性能决定，因此不可能随意地形成垂直延伸的形状。因此，连接上和下封装的每个焊球16-2要求具有大于该间隔的直径。另一方面，依据连接端子(I/O端子)的数目增加，封装的小型化等等，必须减小连接焊球的尺寸和减窄连接电极间距。但是，就焊球而言，存在如果球直径被减小，那么间隔量也减小的问题。相反，如果用于连接上和下封装的焊球16-2的直径大于用于将板连接的焊球16-1的直径，那么由于端子数目，产生封装的尺寸增加的问题。
为了处理该问题，考虑使用除焊球以外的连接方法。例如，专利文件1(日本未审查专利申请公开号(JP-A)-14571)公开了一种半导体器件，具有在半导体元件上形成的金属柱。在专利文件1中，使用电镀方法形成金属柱。但是，通过电镀方法存在金属柱的高度变化的问题。另一方面，在专利文件2(日本未审查专利申请公开号(JP-A)2004-228403)中，半导体元件和相对板的连接图形通过导电柱连接在一起。但是，在专利文件2中，发生有关导电柱的定位问题。这些现有技术文件的技术被不足以应用于具有许多端子的半导体器件，在这种半导体器件中连接电极间距被减窄。
此外，随着增强的功能性，半导体器件的连接端子数目增加，以致需要减窄连接端子间距。
但是，没有建立用于PoP结构的电极连接技术，以便充分地减窄连接电极间距。
发明内容
因此本发明的目的是提供一种用于PoP(Package-on-Package)结构的电极，使之可以减窄端子间距，并提供这种电极的制造方法以及具有这种电极的半导体器件。
为了实现上述目的，本发明基本上采用下面将被描述的技术。可以容易地理解，本发明也包括这种技术的要点范围内能实现的各种应用技术。
本发明的电极制造方法包括以下步骤：从其背面刻蚀金属板，由此形成具有与金属板厚度相等的高度的金属柱。
本发明的电极制造方法的特征在于具有以下步骤：在形成金属柱的步骤之前，在金属板的表面上形成布线板和在该布线板上安装半导体芯片并树脂密封它。
本发明的电极制造方法的特征还可以在于，形成布线板的步骤包括以下步骤：通过在金属板的表面上涂敷抗电镀剂、构图该抗电镀剂、以及进行电镀来形成焊盘，形成用于保护该焊盘的绝缘树脂层，以及在该绝缘树脂层中形成穿通孔由此形成连接到该焊盘的电极。
本发明的电极制造方法的特征还在于通过依次电镀镍、金、镍和铜，形成该焊盘。
本发明的电极制造方法的特征还可以在于通过镀铜形成电极。
本发明的电极制造方法的特征可以在于，形成所述金属柱/多个金属柱的步骤包括：在金属板的背面上涂敷抗刻蚀剂，对该抗刻蚀剂进行构图以提供用于保留与焊盘相对应的金属板区域的图形，以及然后利用该图形刻蚀金属板。
本发明的电极制造方法的特征还可以在于由包含铜作为主要成分的金属板形成金属柱。
本发明的电极由上述电极制造方法的任意一项制造。
本发明的半导体器件包括通过上述电极制造方法的任意一项制造的电极。
本发明的半导体器件的特征在于具有金属柱的封装被用作上封装，以及该金属和下封装的焊盘通过焊接连接在一起。
由于通过刻蚀金属板形成本发明的金属柱，因此获得了可以形成具有精确高度的金属柱的效果。此外，通过使用上封装中形成的本发明的金属柱将上和下封装连接在一起，有可以获得具有精细电极间距和精确高度的小型化PoP结构半导体器件的效果。
附图说明
图1是根据本发明实施例的PoP-结构半导体器件的剖面图；
图2A至2P示出了根据制造流程的主要工艺的剖面图，用于说明根据本发明实施例的PoP-结构半导体器件的制造方法；以及
图3是常规PoP-结构半导体器件的剖面图。
具体实施方式
下面将参考图1和图2A至2P详细描述根据本发明实施例的电极结构及其制造方法。图1是根据本发明实施例的PoP-结构半导体器件的剖面图。图2A至2P示出了根据制造流程的主要工艺的剖面图，用于说明图1所示的PoP-结构半导体器件的制造方法。
首先，将参考图2A至2P，根据制造流程描述电极和PoP-结构半导体器件的制造方法。如图2A所示，首先制备铜板1作为用于形成金属柱的金属板。该金属不被特别限制，只要它是导电性和散热性优异的金属。例如，优选使用导电性和散热性优异的铜或含铜的金属作为主要成分。铜板1的厚度直接对应于铜柱的高度，并被设为例如，200μm。然后，在铜板1的上表面上形成PoP结构中的上封装的焊盘3。该焊盘3通过对抗电镀剂2构图(图2B)并进行电镀工艺(图2C)形成。在该电镀工艺中，依次电镀镍、金、镍和铜。完成该电镀之后，抗电镀剂2被除去。
然后，形成用于保护焊盘3的绝缘树脂层4(图2D)并使用例如，二氧化碳激光器，在将用作穿通孔5的部分执行穿孔(图2E)。然后，再次使用抗电镀剂2并进行电镀工艺，用电镀金属填充穿通孔5，此外，形成连接图形和电极6(图2F和2G)。在该电镀工艺中，进行镀铜。在除去抗电镀剂2之后(图2H)，形成阻焊剂7(图2I)。
在形成多个连接层的情况下，绝缘树脂层形成、激光器穿孔以及电镀的工艺可以被重复需要的次数。通过上述工艺，在铜板1上形成布线板8，布线板8具有用于在其上安装半导体芯片所必需的连接图形和电极6。然后，在布线板8上安装半导体芯片9。在本实施例中，在布线板8上层叠两个半导体芯片9-1和9-2并通过引线键合连接(图2J)。然后，用密封树脂10覆盖半导体芯片9和键合引线，以便与布线板8整体地密封(图2K)。
然后，对抗刻蚀剂11进行构图，以使得其在将形成铜柱的铜板1上的部分处保留(图2L)，并通过刻蚀铜板1，形成铜柱12(图2M)。由此，每个铜柱12的高度等于铜板1的厚度，由于铜板1的厚度精确度是优异的，所以每个铜柱12的高度也是高度精确的。在该刻蚀中，由于半导体芯片9和安装有半导体芯片9的布线板8被密封树脂10整体地密封，所以没有刻蚀的腐蚀影响。在刻蚀铜板1之后，抗蚀剂11被除去，然后在预定部分执行切割，由此获得形成有铜柱12的封装(图2N)。铜柱12被连接到焊盘3，因此用作封装13的电极。
如上所述，通过刻蚀铜板，形成铜柱12，并且每个铜柱12具有等于铜板厚度的高度。铜板的厚度几乎没有偏差，且因此精确度是优异的。因此，铜柱的高精确度也是优异的，而没有偏差。此外，由于利用抗蚀剂图形的刻蚀能够产生精细图形，铜柱的间距可以被精细地减窄。由此，根据本实施例的铜柱最适宜于作为精细-间距电极，且因此最适宜于具有许多端子的PoP结构半导体器件的上封装。
此外，把分别制备的下封装14和上封装13连接在一起。下封装14在其底部设有焊球16，以及在其上部具有半导体芯片9-3，此外，焊料膏15被涂敷到其上部形成的焊盘3(图2O)。上封装13的铜柱12和下封装14的焊盘3通过回流加热键合在一起。因此，上和下封装13和14被集成在一起，由此获得PoP-结构半导体器件20(图2P和图1)。在上和下封装13和14之间可以填充底层填料等等。
以此方式，通过使用铜柱12将上和下封装13和14连接在一起，制造图1的PoP-结构半导体器件20。在上封装13中，安装半导体芯片9-1和9-2，并且铜柱12被连接到焊盘3。下封装14在其中安装有半导体芯片9-3并形成有焊盘3。上封装的铜柱12和下封装的焊盘3上的焊料膏通过回流加热键合，由此形成PoP-结构半导体器件20。该PoP结构中的上和下封装之间的间隔由每个铜柱的高度决定。由于间隔由每个铜柱的高度决定，因此其是优异的而没有偏差。
根据本发明的实施例，通过使用上封装中形成的铜柱的焊接，PoP-结构半导体器件的上和下封装被连接在一起。在铜板上形成的布线板上安装半导体芯片并密封该封装之后，通过从其背面(即与形成布线板的侧面相对的侧面)刻蚀铜板，来形成铜柱。使用铜板的厚度作为每个铜柱的高度，可以在获得精细电极间距的同时，保证用于间隔的高度。由于铜板的厚度的精确度是优异的，PoP-结构半导体器件的间隔的精确度也是优异的，如前面所述。由于该刻蚀使得可以将铜柱处理至精细尺寸，因此能够获得高精确度和小尺寸连接电极。由此，通过利用铜柱作为连接电极，获得了高度精确的和小型化的具有多连接端子的PoP-结构半导体器件。
尽管已根据该实施例详细描述了本发明，但是本发明不限于此，而是在不脱离本发明的原理的条件下，可以以多种方式体现，其均自然地包括在本发明中。

Claims (10)

1.一种电极制造方法，包括以下步骤：从其背面刻蚀金属板，由此形成金属柱，该金属柱具有由所述金属板的厚度决定的高度。
2.根据权利要求1的电极制造方法，在形成所述金属柱的步骤之前，还包括以下步骤：在所述金属板的表面上形成布线板和在所述布线板上安装半导体芯片并对其进行树脂密封。
3.根据权利要求2的电极制造方法，其中形成所述布线板的步骤包括以下若干步骤：通过在所述金属板的表面上涂敷抗电镀剂、对所述抗电镀剂进行构图、然后电镀从而形成焊盘，形成用于保护所述焊盘的绝缘树脂层，以及在所述绝缘树脂层中形成穿通孔以由此形成连接到所述焊盘的电极。
4.根据权利要求3的电极制造方法，其中所述焊盘通过依次电镀镍、金、镍和铜来形成。
5.根据权利要求3的电极制造方法，其中通过镀铜形成所述电极。
6.根据权利要求1的电极制造方法，其中形成所述金属柱的步骤包括：在所述金属板的背面上涂敷抗蚀剂，对所述抗蚀剂进行构图以提供用于保留与焊盘相对应的所述金属板的区域的图形，以及利用所述图形刻蚀所述金属板。
7.一种通过根据权利要求1的电极制造方法制造的电极。
8.根据权利要求7的电极，其中所述金属柱由包含铜作为主要成分的金属板形成。
9.一种半导体器件，包括通过根据权利要求1的电极制造方法制造的电极。
10.一种根据权利要求9的半导体器件，其中具有所述金属柱的封装被用作上封装，并且所述金属柱和下封装的焊盘通过焊接连接在一起。
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CN105047617A (zh) * 2015-06-09 2015-11-11 华进半导体封装先导技术研发中心有限公司 一种整体堆叠封装结构及其制作方法
CN105047617B (zh) * 2015-06-09 2018-01-16 华进半导体封装先导技术研发中心有限公司 一种整体堆叠封装结构及其制作方法
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