CN118135913A - Pixel circuit, driving method and display device thereof - Google Patents

Abstract

The pixel circuit, the driving method and the display device thereof provided by the embodiment of the disclosure comprise the following steps: a light emitting device; a driving transistor configured to generate a driving current for driving the light emitting device to emit light according to the data voltage signal; a first control circuit configured to provide a signal of a reference voltage signal terminal to a first node in response to a signal of a first control signal terminal; a first coupling control circuit configured to stabilize a voltage of the first node and a voltage of a gate of the driving transistor; a second coupling control circuit configured to stabilize a voltage of the first node and a voltage of a second pole of the driving transistor; a second control circuit configured to turn on the gate of the driving transistor and the first pole of the driving transistor in response to a signal of the second control signal terminal; and a data write circuit configured to supply a data voltage signal of the data signal terminal to the gate of the driving transistor in response to the signal of the first scan signal terminal.

Description

Pixel circuit, driving method and display device thereof

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method, and a display device thereof.

Background

Light emitting devices such as Organic LIGHT EMITTING Diodes (OLED), quantum Dot LIGHT EMITTING Diodes (QLED), micro LIGHT EMITTING Diodes (Micro LED), and Mini LEDs (MINI LIGHT EMITTING Diode, mini LED) have advantages of self-luminescence and low energy consumption, and are one of hot spots in the application research field of current display devices. A pixel circuit is used in a general display device to drive a light emitting device to emit light.

The pixel circuit may include a driving transistor generating a driving current and a light emitting device to which the driving current is applied. When the driving transistor of the pixel circuit does not normally operate or the wiring is cut off or short-circuited, the light emitting device may not normally emit light since the driving current is not normally applied to the light emitting device. Therefore, it is necessary to confirm whether the driving transistor or other transistors in the pixel circuit are defective or not before the manufacturing process of the light emitting device, that is, to detect by the array test (ARRAY TEST, AT), so that the production efficiency can be improved and the cost can be reduced.

Disclosure of Invention

The pixel circuit provided by the embodiment of the disclosure comprises:

A light emitting device;

a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

A first control circuit coupled to the first node and configured to provide a signal of a reference voltage signal terminal to the first node in response to a signal of a first control signal terminal;

a first coupling control circuit coupled to the first node and the gate of the driving transistor, configured to stabilize a voltage of the first node and a voltage of the gate of the driving transistor;

A second coupling control circuit coupled to the first node and a second pole of the driving transistor, configured to stabilize a voltage of the first node and a voltage of the second pole of the driving transistor;

A second control circuit coupled to the gate of the drive transistor and the first pole of the drive transistor and configured to turn on the gate of the drive transistor and the first pole of the drive transistor in response to a signal from a second control signal terminal;

And a data write circuit coupled to the gate of the driving transistor and configured to supply the data voltage signal of the data signal terminal to the gate of the driving transistor in response to the signal of the first scan signal terminal.

In some possible embodiments, the first control circuit includes: a first transistor;

the gate of the first transistor is coupled to the first control signal terminal, the first pole of the first transistor is coupled to the first node, and the second pole of the first transistor is coupled to the reference voltage signal terminal.

In some possible embodiments, the first coupling control circuit includes: a first capacitor;

The first electrode of the first capacitor is coupled to the gate of the driving transistor, and the second electrode of the first capacitor is coupled to the first node.

In some possible embodiments, the second coupling control circuit includes: a second capacitor;

the first electrode of the second capacitor is coupled to the first node, and the second electrode of the second capacitor is coupled to the second electrode of the driving transistor.

In some possible embodiments, the second control circuit includes: a second transistor;

the gate of the second transistor is coupled to the second control signal terminal, the first pole of the second transistor is coupled to the gate of the driving transistor, and the second pole of the second transistor is coupled to the first pole of the driving transistor.

In some possible implementations, the data write circuit includes: a third transistor;

The gate of the third transistor is coupled to the first scan signal terminal, the first pole of the third transistor is coupled to the data signal terminal, and the second pole of the third transistor is coupled to the gate of the driving transistor.

In some possible embodiments, the method further comprises: an initialization circuit coupled to the light emitting device and configured to provide a signal of an initialization signal terminal to the light emitting device in response to a signal of a reset signal terminal.

In some possible implementations, the initialization circuit includes: a fourth transistor;

The gate of the fourth transistor is coupled to the reset signal terminal, the first pole of the fourth transistor is coupled to the second pole of the driving transistor, and the second pole of the fourth transistor is coupled to the initialization signal terminal.

In some possible embodiments, the method further comprises: a first light emission control circuit is coupled to the first pole of the drive transistor and configured to provide a signal of a first power supply terminal to the first pole of the drive transistor in response to a signal of a first light emission control signal terminal.

In some possible embodiments, the first light emitting control circuit includes: a fifth transistor;

the gate of the fifth transistor is coupled to the first light emitting control signal terminal, the first pole of the fifth transistor is coupled to the first power supply terminal, and the second pole of the fifth transistor is coupled to the first pole of the driving transistor.

In some possible embodiments, the method further comprises: and a second light emission control circuit, which is positioned between the second electrode of the driving transistor and the light emitting device, is coupled with the second electrode of the driving transistor and the light emitting device, and is configured to respond to the signal of the second light emission control signal terminal to conduct the second electrode of the driving transistor with the light emitting device.

In some possible embodiments, the second light emission control circuit includes: a sixth transistor;

the grid electrode of the sixth transistor is coupled with the second light-emitting control signal end, the first electrode of the sixth transistor is coupled with the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled with the light-emitting device.

In some possible embodiments, the gate of the driving transistor includes: a first gate and a second gate; the first gate of the driving transistor is coupled to the data writing circuit, and the second gate of the driving transistor is coupled to the second pole of the driving transistor.

The display device provided by the embodiment of the disclosure comprises the pixel circuit.

The embodiment of the disclosure provides a driving method for the pixel circuit, which comprises the following steps:

A reset stage, in which the first control circuit responds to the signal of the first control signal terminal and provides the signal of the reference voltage signal terminal to the first node; the second control circuit responds to a signal of a second control signal end to conduct the grid electrode of the driving transistor with the first pole of the driving transistor;

A threshold compensation stage, wherein the first control circuit responds to the signal of the first control signal terminal and provides the signal of the reference voltage signal terminal to the first node; a first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; a second coupling control circuit stabilizes the voltage of the first node and the voltage of the second pole of the driving transistor;

A data writing stage, in which the data writing circuit responds to the signal of the first scanning signal end and provides the data voltage signal of the data signal end to the grid electrode of the driving transistor; the first control circuit responds to the signal of the first control signal end and provides the signal of the reference voltage signal end to the first node; a first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; a second coupling control circuit stabilizes the voltage of the first node and the voltage of the second pole of the driving transistor;

and in the light-emitting stage, the driving transistor generates a driving current for driving the light-emitting device to emit light according to the data voltage signal.

Drawings

Fig. 1 is a schematic diagram of some structures of a pixel circuit according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of other structures of a pixel circuit according to an embodiment of the disclosure;

fig. 3 is a flowchart of a driving method of a pixel circuit according to an embodiment of the disclosure;

FIG. 4 is a timing diagram of some signals provided by embodiments of the present disclosure;

FIG. 5 is a timing diagram of other signals provided by embodiments of the present disclosure;

FIG. 6 is a schematic diagram of still other structures of a pixel circuit provided in an embodiment of the disclosure;

FIG. 7 is a schematic diagram of still other structures of a pixel circuit provided in an embodiment of the disclosure;

FIG. 8 is a timing diagram of yet other signals provided by embodiments of the present disclosure;

FIG. 9 is a schematic diagram of still other structures of a pixel circuit provided by embodiments of the present disclosure;

Fig. 10 is a schematic diagram of still other structures of a pixel circuit according to an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the figures in the drawings do not reflect true proportions, and are intended to illustrate the present invention only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The display device provided by the embodiment of the disclosure comprises: the display panel comprises a display area of the display panel, and a plurality of pixel units which are arranged in an array mode. Illustratively, each pixel cell includes a plurality of sub-pixels. For example, the pixel unit may include red, green, and blue sub-pixels, so that color mixing can be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed by red, green, blue, and white to realize color display. Of course, in practical application, the emission color of the sub-pixels in the pixel unit may be designed and determined according to the practical application environment, which is not limited herein.

In the embodiment of the disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light emitting device to drive the light emitting device to emit light, so that the display panel realizes a function of displaying a picture. Due to the reasons of process and device aging, the threshold voltage Vth of the driving transistor is uneven, so that the current flowing through different light emitting devices is changed to cause uneven display brightness, thereby affecting the display effect of the whole image.

And if the driving transistor is defective, display quality is also affected. Because the material cost of the light emitting device in the subsequent light emitting device manufacturing process is relatively high, if the array test (ARRAY TEST, AT) is not performed first to check whether the transistor manufacturing process is bad, the subsequent display backboard manufacturing cost is wasted, and the production efficiency is reduced.

Accordingly, embodiments of the present disclosure provide a pixel circuit, as shown in fig. 1, comprising: a light emitting device L;

a driving transistor M0 coupled to the light emitting device L and configured to generate a driving current for driving the light emitting device L to emit light according to the data voltage signal;

A first control circuit 10 coupled to the first node N1 and configured to provide a signal of the reference voltage signal terminal VREF to the first node N1 in response to a signal of the first control signal terminal CS 1;

A first coupling control circuit 20 coupled to the first node N1 and the gate of the driving transistor M0, configured to stabilize the voltage of the first node N1 and the voltage of the gate of the driving transistor M0;

A second coupling control circuit 30 coupled to the first node N1 and the second pole of the driving transistor M0, configured to stabilize the voltage of the first node N1 and the voltage of the second pole of the driving transistor M0;

A second control circuit 40 coupled to the gate of the driving transistor M0 and the first pole of the driving transistor M0, and configured to turn on the gate of the driving transistor M0 and the first pole of the driving transistor M0 in response to the signal of the second control signal terminal CS 2;

The data writing circuit 50, coupled to the gate of the driving transistor M0, is configured to provide the data voltage signal of the data signal terminal DA to the gate of the driving transistor M0 in response to the signal of the first scan signal terminal SS 1.

In the embodiment of the disclosure, through the mutual matching of the first control circuit, the first coupling control circuit, the second control circuit and the data writing circuit, the driving transistor can be tested when the array test (ARRAY TEST, AT) is performed before the preparation process of the light emitting device, so that whether the driving transistor is bad or not is judged, the waste of the manufacturing cost of the display backboard is reduced, the production efficiency can be improved, and the cost is reduced.

In addition, in the embodiment of the disclosure, by means of different paths for compensating the threshold voltage of the driving transistor and writing the data voltage, the threshold voltage compensation of the driving transistor and the data voltage writing are performed separately, so that high-frequency driving can be realized, and the influence of threshold voltage drift of the driving transistor on light emission of the light emitting device can be avoided.

In the embodiment of the present disclosure, as shown in fig. 1, the driving transistor M0 may be provided as an N-type transistor; the first pole of the driving transistor M0 may be a source thereof, and the second pole of the driving transistor M0 may be a drain thereof. Of course, the driving transistor M0 may be a P-type transistor, which is not limited herein.

In the embodiment of the disclosure, as shown in fig. 1, the second electrode of the driving transistor M0 is coupled to the anode of the light emitting device L, and the cathode of the light emitting device L is coupled to the second power terminal VSS. Illustratively, the light emitting device L may include: at least one of Micro LIGHT EMITTING Diode (Micro LED), organic LIGHT EMITTING Diode (OLED), and Quantum Dot LIGHT EMITTING Diode (QLED). The light emitting device L may include an anode, a light emitting layer, and a cathode, which are stacked. Further, the light emitting layer may further include a hole injection layer, a hole transport layer, an electron injection layer, and the like. In practical applications, the specific structure of the light emitting device may be designed and determined according to practical application environments, which is not limited herein.

In some embodiments of the present disclosure, as shown in fig. 2, the first control circuit 10 includes: a first transistor M1; the gate of the first transistor M0 is coupled to the first control signal terminal CS1, the first pole of the first transistor M1 is coupled to the first node N1, and the second pole of the first transistor M1 is coupled to the reference voltage signal terminal VREF.

Illustratively, the first transistor M1 may be turned on under control of an active level of the first control signal transmitted by the first control signal terminal CS1, and may be turned off under control of an inactive level of the first control signal. Illustratively, the first transistor M1 is set as a P-type transistor, and the active level of the first control signal is low, and the inactive level of the first control signal is high. Or the first transistor M1 is set as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

In some embodiments of the present disclosure, as shown in fig. 2, the first coupling control circuit 20 includes: a first capacitor C1; the first electrode of the first capacitor C1 is coupled to the gate of the driving transistor M0, and the second electrode of the first capacitor C1 is coupled to the first node N1.

In some embodiments of the present disclosure, as shown in fig. 2, the second coupling control circuit 30 includes: a second capacitor C2; the first electrode of the second capacitor C2 is coupled to the first node N1, and the second electrode of the second capacitor C2 is coupled to the second electrode of the driving transistor M0.

In some embodiments of the present disclosure, as shown in fig. 2, the second control circuit 40 includes: a second transistor M2; the gate of the second transistor M2 is coupled to the second control signal terminal CS2, the first pole of the second transistor M2 is coupled to the gate of the driving transistor M0, and the second pole of the second transistor M2 is coupled to the first pole of the driving transistor M0.

Illustratively, the second transistor M2 may be turned on under control of an active level of the second control signal transmitted by the second control signal terminal CS2, and may be turned off under control of an inactive level of the second control signal. Illustratively, the second transistor M2 is set as a P-type transistor, and the active level of the second control signal is low, and the inactive level of the second control signal is high. Or the second transistor M2 is set as an N-type transistor, the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

In some embodiments of the present disclosure, as shown in FIG. 2, data write circuit 50 includes: a third transistor M3; the gate of the third transistor M3 is coupled to the first scan signal terminal SS1, the first pole of the third transistor M3 is coupled to the data signal terminal DA, and the second pole of the third transistor M3 is coupled to the gate of the driving transistor M0.

Illustratively, the third transistor M3 may be turned on under control of an active level of the first scan signal transmitted by the first scan signal terminal SS1, and may be turned off under control of an inactive level of the first scan signal. Illustratively, the third transistor M3 is set as a P-type transistor, and the active level of the first scan signal is low, and the inactive level of the first scan signal is high. Or the third transistor M3 is set as an N-type transistor, the active level of the first scan signal is a high level, and the inactive level of the first scan signal is a low level.

In some embodiments of the present disclosure, as shown in fig. 2, further comprising: the initialization circuit 60 is coupled to the light emitting device L and configured to provide a signal of the initialization signal terminal VINIT to the light emitting device L in response to a signal of the reset signal terminal RE.

In some embodiments of the present disclosure, as shown in fig. 2, the initialization circuit 60 includes: a fourth transistor M4; the gate of the fourth transistor M4 is coupled to the reset signal terminal RE, the first pole of the fourth transistor M4 is coupled to the second pole of the driving transistor M0, and the second pole of the fourth transistor M4 is coupled to the initialization signal terminal VINIT.

Illustratively, the fourth transistor M4 may be turned on under control of an active level of the reset signal transmitted by the reset signal terminal RE, and may be turned off under control of an inactive level of the reset signal. Illustratively, the fourth transistor M4 is set as a P-type transistor, and the active level of the reset signal is low and the inactive level of the reset signal is high. Or the fourth transistor M4 is set to an N-type transistor, the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level.

For example, the reference voltage signal terminal VREF and the initialization signal terminal VINIT may be loaded with the same signal, so that the number of signal lines may be reduced, the space occupied by the wiring may be reduced, and the circuit design may be simplified.

In some embodiments of the present disclosure, as shown in fig. 2, further comprising: the first light emitting control circuit 70 is coupled to the first pole of the driving transistor M0 and configured to provide the signal of the first power supply terminal VDD to the first pole of the driving transistor M0 in response to the signal of the first light emitting control signal terminal EM 1.

In some embodiments of the present disclosure, as shown in fig. 2, the first light emitting control circuit 70 includes: a fifth transistor M5; the gate of the fifth transistor M5 is coupled to the first light emitting control signal terminal EM1, the first pole of the fifth transistor M5 is coupled to the first power source terminal VDD, and the second pole of the fifth transistor M5 is coupled to the first pole of the driving transistor M0.

Illustratively, the fifth transistor M5 may be turned on under control of an active level of the first light emitting control signal transmitted by the first light emitting control signal terminal EM1, and may be turned off under control of an inactive level of the first light emitting control signal. Illustratively, the fifth transistor M5 is set as a P-type transistor, and the active level of the first light emitting control signal is low, and the inactive level of the first light emitting control signal is high. Or the fifth transistor M5 is set as an N-type transistor, the active level of the first light emitting control signal is a high level, and the inactive level of the first light emitting control signal is a low level.

In some embodiments of the present disclosure, as shown in fig. 2, the driving transistor M0 is a dual gate transistor, and the gate of the driving transistor M0 includes: a first gate G1 and a second gate G2; the first gate G1 of the driving transistor M0 is coupled to the second pole of the third transistor M3 in the data writing circuit 50, and the second gate G2 of the driving transistor M0 is coupled to the second pole of the driving transistor M0.

Illustratively, the first pole of the transistor may be its source and the second pole may be its drain. Or the first pole is its drain and the second pole is its source. And are not limited thereto.

The transistor generally adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material as the active layer, has high mobility, can be made thinner and smaller, has lower power consumption, and the like, and can enable the material of the active layer of the at least one transistor to be set as the low temperature polysilicon material when in implementation. This makes it possible to set the above-described transistor as an LTPS-type transistor so that the pixel circuit can realize high mobility and can be made thinner and smaller, power consumption lower, and the like.

Since the leakage current of the transistor using the metal oxide semiconductor material as the active layer is generally small, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of the at least one transistor may also include a metal oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide ), or may be other metal oxide semiconductor materials, which is not limited herein. This allows the transistor to be an oxide transistor (Oxide Thin Film Transistor) so that the leakage current of the pixel circuit can be reduced.

By way of example, all transistors may be provided as LTPS type transistors.

Or all transistors may be provided as oxide type transistors. Because the metal oxide has lower cost, the crystallization process is not needed by using laser equipment.

Alternatively, part of the transistors may be oxide-type transistors, and the remaining transistors may be LTPS-type transistors.

In the disclosed embodiments, the first power supply terminal VDD may be configured to load a constant first power supply voltage VDD, and the first power supply voltage VDD is generally a positive value. And, the second power terminal VSS may load a constant second power voltage VSS, and the second power voltage VSS may be a ground voltage or a negative value. In practical applications, specific values of the first power supply voltage vdd and the second power supply voltage vss may be designed and determined according to practical application environments, which is not limited herein.

The driving method of the pixel circuit provided in the embodiment of the disclosure, as shown in fig. 3, includes the following steps:

S100, in a reset stage, a first control circuit responds to a signal of a first control signal end and provides a signal of a reference voltage signal end to a first node; the second control circuit responds to the signal of the second control signal end to conduct the grid electrode of the driving transistor with the first pole of the driving transistor;

S200, a threshold compensation stage, wherein a first control circuit responds to a signal of a first control signal end and provides a signal of a reference voltage signal end to a first node; the first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; the second coupling control circuit stabilizes the voltage of the first node and the voltage of the second pole of the driving transistor;

S300, a data writing stage, wherein a data writing circuit responds to a signal of a first scanning signal end and provides a data voltage signal of a data signal end to a grid electrode of a driving transistor; the first control circuit responds to the signal of the first control signal end and provides the signal of the reference voltage signal end to the first node; the first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; the second coupling control circuit stabilizes the voltage of the first node and the voltage of the second pole of the driving transistor;

S400, in the light-emitting stage, the driving transistor generates driving current for driving the light-emitting device to emit light according to the data voltage signal.

The following describes the operation of the pixel circuit according to the embodiment of the present disclosure, taking the pixel circuit shown in fig. 2 as an example, with reference to the signal timing diagram shown in fig. 4.

In the embodiment of the disclosure, as shown in fig. 4, EM1 represents the first light emitting control signal of the first light emitting control signal terminal EM1, CS1 represents the first control signal of the first control signal terminal CS1, CS2 represents the second control signal of the second control signal terminal CS2, RE represents the reset signal of the reset signal terminal RE, SS1 represents the first scan signal of the first scan signal terminal SS1, and DA represents the data voltage signal of the data signal terminal DA.

And, a reset phase F1, a threshold compensation phase F2, a data writing phase F3 and a light emitting phase F4 in one display frame are selected.

In the reset phase F1, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned on under the control of the high level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light emitting control signal em 1. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, and the voltage value VN 1=vref of the first node N1, where VREF represents the voltage value of the signal of the reference voltage signal terminal VREF; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first pole of the driving transistor M0, the turned-on second transistor M2 turns on the first pole of the driving transistor M0 and the first gate G1 of the driving transistor M0, and the voltage value Vg 1=vdd of the first gate G1 of the driving transistor M0, wherein VDD represents the first power supply voltage of the first power supply terminal VDD; the turned-on fourth transistor M4 supplies the signal of the initialization signal terminal VINIT to the anode of the light emitting device L, and the voltage value vl=vinit of the anode of the light emitting device L, wherein VINIT represents the voltage value of the signal of the initialization signal terminal VINIT.

In the threshold compensation stage F2, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light emitting control signal em 1. The turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0; the turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, and the voltage value VN 1=vref of the first node N1, and the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0; the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second pole of the driving transistor M0, and completes the compensation of the threshold voltage Vth of the driving transistor M0 by the source follower mode, the voltage value Vg 1=vdd of the first gate G1 of the driving transistor M0, and the voltage value vs=vdd-Vth of the second pole of the driving transistor M0.

In the data writing stage F3, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned on under the control of the high level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, and the fifth transistor M5 is turned off under the control of the low level of the first light emitting control signal em 1. The turned-on first transistor M1 supplies the signal of the reference voltage signal terminal VREF to the first node N1, the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0, the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second pole of the driving transistor M0, the turned-on third transistor M3 supplies the data voltage signal DA of the data signal terminal DA to the first gate G1 of the driving transistor M0, and then the voltage value Vg 1=vda of the first gate G1 of the driving transistor M0, wherein Vda represents the voltage value of the data voltage signal DA, and the voltage value vs=vdd-Vth of the second pole of the driving transistor M0.

In the light emitting stage F4, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light emitting control signal em 1. The turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0; the driving transistor M0 generates a driving current according to the data voltage signal da, which charges the anode of the light emitting device L until the light emitting device L stably emits light, at which time the voltage value vl=vs=vdd-Vth of the anode of the light emitting device L. And the voltage value Vg 1=vda of the first gate G1 of the driving transistor M0, and therefore, the voltage difference vgs=vda-vdd+vth between the first gate G1 and the source of the driving transistor M0; then, the driving transistor M0 operates in the saturation region, and the driving current I generated by the driving transistor M0 can be expressed as: i=k (Vgs-Vth) ²＝K*(Vda-vdd+Vth-Vth)²＝K*(Vda-vdd)²; wherein,Wherein μ represents mobility of the driving transistor M0, C _ox represents capacitance per unit area of the gate insulating layer of the driving transistor M0,/>Representing the channel width to length ratio of the drive transistor M0.

As can be seen from the above, the pixel circuit can solve the problem of uneven threshold voltage compensation of the driving transistor when the driving current I is not related to the threshold voltage Vth of the driving transistor M0, thereby improving the display effect. And the path for compensating the threshold voltage of the driving transistor is different from the path for writing the data voltage, so that the threshold voltage compensation of the driving transistor and the data voltage writing are performed separately, high-frequency driving can be realized, and the influence of the threshold voltage drift of the driving transistor on the light emission of the light emitting device is avoided.

The following describes an array detection process of the pixel circuit according to the embodiment of the present disclosure, taking the pixel circuit shown in fig. 2 as an example, with reference to the signal timing diagram shown in fig. 5.

In the embodiment of the disclosure, as shown in fig. 5, EM1 represents the first light emitting control signal of the first light emitting control signal terminal EM1, CS1 represents the first control signal of the first control signal terminal CS1, CS2 represents the second control signal of the second control signal terminal CS2, RE represents the reset signal of the reset signal terminal RE, SS1 represents the first scan signal of the first scan signal terminal SS1, and DA represents the data voltage signal of the data signal terminal DA.

In the initialization stage T1, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned on under the control of the high level of the reset signal re, and the fifth transistor M5 is turned on under the control of the high level of the first light emitting control signal em 1. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, and the voltage value VN 1=vref of the first node N1, where VREF represents the voltage value of the signal of the reference voltage signal terminal VREF; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first pole of the driving transistor M0, the turned-on second transistor M2 turns on the first pole of the driving transistor M0 and the first gate G1 of the driving transistor M0, and the voltage value Vg 1=vdd of the first gate G1 of the driving transistor M0, wherein VDD represents the first power supply voltage of the first power supply terminal VDD; the turned-on fourth transistor M4 supplies the signal of the initialization signal terminal VINIT to the anode of the light emitting device L, and the voltage value vl=vinit of the anode of the light emitting device L, wherein VINIT represents the voltage value of the signal of the initialization signal terminal VINIT.

In the detection phase, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned on under the control of the high level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, and the fifth transistor M5 is turned off under the control of the low level of the first light emission control signal em 1. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, the turned-on second transistor M2 turns on the first pole of the driving transistor M0 and the first gate G1 of the driving transistor M0, and the turned-on third transistor M3 provides the detection signal te to the first gate G1 of the driving transistor M0; the detection signal te passes through the third transistor M3, the second transistor M2, and the second poles of the driving transistors M0 to M0, and is used to detect whether the third transistor M3, the second transistor M2, and the driving transistor M0 generate a defect. After confirming that the third transistor M3, the second transistor M2, and the driving transistor M0 do not generate defects, it is confirmed that the display back panel enters the next manufacturing process.

Illustratively, the presence of the partial voltage of the parasitic capacitance Coled of the light emitting device L (i.e., the capacitance formed by the cathode and anode of the light emitting device L) also affects the display effect, resulting in degradation of the display quality.

The embodiments of the present disclosure provide other schematic structures of the pixel circuit, as shown in fig. 6, which are modified from the implementation of the embodiments described above. Only the differences between the present embodiment and the above-described embodiments are described below, and their substantial points are not described herein.

In other embodiments of the present disclosure, as shown in fig. 6, further comprising: the second light emission control circuit 80, which is located between the second electrode of the driving transistor M0 and the light emitting device L, and is coupled to the second electrode of the driving transistor M0 and the light emitting device L, is configured to turn on the second electrode of the driving transistor M0 and the light emitting device L in response to the signal of the second light emission control signal terminal EM 2.

According to the embodiment of the disclosure, the second light-emitting control circuit is arranged, so that partial voltage of parasitic capacitance Coled of the light-emitting device L (namely, capacitance formed by the cathode and the anode of the light-emitting device L) can be effectively avoided, the display effect is improved, and display quality is prevented from being reduced.

In other embodiments of the present disclosure, as shown in fig. 7, the second light emission control circuit 80 includes: a sixth transistor M6; the gate of the sixth transistor M6 is coupled to the second light-emitting control signal terminal EM2, the first electrode of the sixth transistor M6 is coupled to the second electrode of the driving transistor M0, and the second electrode of the sixth transistor M6 is coupled to the light-emitting device L.

Illustratively, the sixth transistor M6 may be turned on under control of an active level of the second light emission control signal transmitted by the second light emission control signal terminal EM2, and may be turned off under control of an inactive level of the second light emission control signal. Illustratively, the sixth transistor M6 is set as a P-type transistor, and the active level of the second light emission control signal is low, and the inactive level of the second light emission control signal is high. Or the sixth transistor M6 is set as an N-type transistor, the active level of the second light emission control signal is a high level, and the inactive level of the second light emission control signal is a low level.

The first light emission control signal terminal EM1 and the second light emission control signal terminal EM2 may load the same signal, so that the number of signal lines may be reduced, the space occupied by the wiring may be reduced, and the circuit design may be simplified.

The following describes the operation of the pixel circuit according to the embodiment of the present disclosure, taking the pixel circuit shown in fig. 2 as an example, with reference to the signal timing diagram shown in fig. 8.

In the embodiment of the disclosure, as shown in fig. 8, EM1 represents the first light emitting control signal of the first light emitting control signal terminal EM1, EM2 represents the second light emitting control signal of the second light emitting control signal terminal EM2, CS1 represents the first control signal of the first control signal terminal CS1, CS2 represents the second control signal of the second control signal terminal CS2, RE represents the reset signal of the reset signal terminal RE, SS1 represents the first scan signal of the first scan signal terminal SS1, and DA represents the data voltage signal of the data signal terminal DA.

And, a reset phase F1, a threshold compensation phase F2, a data writing phase F3 and a light emitting phase F4 in one display frame are selected.

In the reset phase F1, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned on under the control of the high level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned on under the control of the high level of the reset signal re, the fifth transistor M5 is turned on under the control of the high level of the first light emission control signal em1, and the sixth transistor M6 is turned on under the control of the high level of the second light emission control signal em 2. The turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, and the voltage value VN 1=vref of the first node N1, where VREF represents the voltage value of the signal of the reference voltage signal terminal VREF; the turned-on fifth transistor M5 provides the signal of the first power supply terminal VDD to the first pole of the driving transistor M0, the turned-on second transistor M2 turns on the first pole of the driving transistor M0 and the first gate G1 of the driving transistor M0, and the voltage value Vg 1=vdd of the first gate G1 of the driving transistor M0, wherein VDD represents the first power supply voltage of the first power supply terminal VDD; the fourth transistor M4 is turned on to provide the signal of the initialization signal terminal VINIT to the second diode of the driving transistor M0, the sixth transistor M6 is turned on to turn on the second diode of the driving transistor M0 and the anode of the light emitting device L, and the voltage value vl=vinit of the anode of the light emitting device L, where VINIT represents the voltage value of the signal of the initialization signal terminal VINIT.

In the threshold compensation stage F2, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, the fifth transistor M5 is turned on under the control of the high level of the first light emission control signal em1, and the sixth transistor M6 is turned on under the control of the high level of the second light emission control signal em 2. The turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0; the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the anode of the light emitting device L; the turned-on first transistor M1 provides the signal of the reference voltage signal terminal VREF to the first node N1, and the voltage value VN 1=vref of the first node N1, and the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0; the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second pole of the driving transistor M0, and completes the compensation of the threshold voltage Vth of the driving transistor M0 by the source follower mode, and then the voltage value Vg 1=vdd of the first gate G1 of the driving transistor M0 and the voltage value vs=vdd-Vth of the second pole of the driving transistor M0.

In the data writing stage F3, the first transistor M1 is turned on under the control of the high level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned on under the control of the high level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, the fifth transistor M5 is turned off under the control of the low level of the first light emission control signal em1, and the sixth transistor M6 is turned off under the control of the low level of the second light emission control signal em 2. The turned-on first transistor M1 supplies the signal of the reference voltage signal terminal VREF to the first node N1, the first capacitor C1 stabilizes the voltage of the first node N1 and the voltage of the first gate G1 of the driving transistor M0, the second capacitor C2 stabilizes the voltage of the first node N1 and the voltage of the second pole of the driving transistor M0, the turned-on third transistor M3 supplies the data voltage signal DA of the data signal terminal DA to the first gate G1 of the driving transistor M0, and then the voltage value Vg 1=vda of the first gate G1 of the driving transistor M0, wherein Vda represents the voltage value of the data voltage signal DA, and the voltage value vs=vdd-Vth of the second pole of the driving transistor M0.

In the light emitting stage F4, the first transistor M1 is turned off under the control of the low level of the first control signal cs1, the second transistor M2 is turned off under the control of the low level of the second control signal cs2, the third transistor M3 is turned off under the control of the low level of the first scan signal ss1, the fourth transistor M4 is turned off under the control of the low level of the reset signal re, the fifth transistor M5 is turned on under the control of the high level of the first light emitting control signal em1, and the sixth transistor M6 is turned on under the control of the high level of the second light emitting control signal em 2. The turned-on fifth transistor M5 supplies the signal of the first power supply terminal VDD to the first electrode of the driving transistor M0, and the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the anode of the light emitting device L; the driving transistor M0 generates a driving current according to the data voltage signal da, which charges the anode of the light emitting device L until the light emitting device L stably emits light, at which time the voltage value vl=vs=vdd-Vth of the anode of the light emitting device L. And the voltage value Vg 1=vda of the first gate G1 of the driving transistor M0, and therefore, the voltage difference vgs=vda-vdd+vth between the first gate G1 and the source of the driving transistor M0; the driving transistor M0 operates in the saturation region and the driving current I generated by it can be expressed as: i=k (Vgs-Vth) ²＝K*(Vda-vdd+Vth-Vth)²＝K*(Vda-vdd)²; wherein,Wherein μ represents mobility of the driving transistor M0, C _ox represents capacitance per unit area of the gate insulating layer of the driving transistor M0,/>Representing the channel width to length ratio of the drive transistor M0.

As can be seen from the above, the pixel circuit can solve the problem of uneven threshold voltage compensation of the driving transistor when the driving current I is not related to the threshold voltage Vth of the driving transistor M0, thereby improving the display effect. And the path for compensating the threshold voltage of the driving transistor is different from the path for writing the data voltage, so that the threshold voltage compensation of the driving transistor and the data voltage writing are performed separately, high-frequency driving can be realized, and the influence of the threshold voltage drift of the driving transistor on the light emission of the light emitting device is avoided.

Illustratively, since the first power supply terminal VDD is easily dropped (IR Drop), the first power supply voltage VDD of the first power supply terminal VDD is not uniform, thereby affecting the display effect, resulting in degradation of display quality.

The embodiments of the present disclosure provide further structural schematic diagrams of pixel circuits, as shown in fig. 9, which are modified for implementation in the above embodiments. Only the differences between the present embodiment and the above-described embodiments are described below, and their substantial points are not described herein.

In the embodiment of the present disclosure, as shown in fig. 9, further includes: a reset circuit 90 configured to supply a signal of an initialization signal terminal VINIT to the cathode of the light emitting device L in response to a signal of a reset signal terminal RE; wherein the reset circuit 90 includes: a seventh transistor M7; the gate of the seventh transistor M7 is coupled to the reset signal terminal RE, the first electrode of the seventh transistor M7 is coupled to the cathode of the light emitting device L, and the second electrode of the seventh transistor M7 is coupled to the initialization signal terminal VINIT. And, an anode of the light emitting device L is coupled to the first power supply terminal VDD, and a cathode of the light emitting device L is coupled to the first pole of the fifth transistor M5. By the arrangement, the situation that the display quality is reduced and the display effect is poor due to the fact that the first power supply voltage VDD is uneven due to the fact that the voltage Drop (IR Drop) occurs at the first power supply terminal VDD can be avoided.

Alternatively, as shown in fig. 10, the anode of the light emitting device L is coupled to the first power supply terminal VDD, and the cathode of the light emitting device L is coupled to the first pole of the fifth transistor M5. A first pole of the fourth transistor M4 in the initialization circuit 60 is coupled to the cathode of the light emitting device L. By the arrangement, the situation that the display quality is reduced and the display effect is poor due to the fact that the first power supply voltage VDD is uneven due to the fact that the voltage Drop (IR Drop) occurs at the first power supply terminal VDD can be avoided.

By way of example, the voltage drop problem in the pixel circuit can be improved by inverting the light emitting device L, or patterning the second power supply terminal VSS, or arranging the anodes of the light emitting device L in a grid shape, so as to further improve the display effect.

Based on the same disclosure concept, the embodiment of the disclosure also provides a display device, which comprises the pixel circuit provided by the embodiment of the disclosure. The principle of the display device for solving the problems is similar to that of the pixel circuit, so the implementation of the display device can be referred to the implementation of the pixel circuit, and the repetition is omitted herein.

In specific implementation, in the embodiment of the disclosure, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, an electronic watch, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims and the equivalents thereof, the present invention is also intended to include such modifications and variations.

Claims (15)

1. A pixel circuit, comprising:

A light emitting device;

a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

A first control circuit coupled to the first node and configured to provide a signal of a reference voltage signal terminal to the first node in response to a signal of a first control signal terminal;

a first coupling control circuit coupled to the first node and the gate of the driving transistor, configured to stabilize a voltage of the first node and a voltage of the gate of the driving transistor;

A second coupling control circuit coupled to the first node and a second pole of the driving transistor, configured to stabilize a voltage of the first node and a voltage of the second pole of the driving transistor;

A second control circuit coupled to the gate of the drive transistor and the first pole of the drive transistor and configured to turn on the gate of the drive transistor and the first pole of the drive transistor in response to a signal from a second control signal terminal;

And a data write circuit coupled to the gate of the driving transistor and configured to supply the data voltage signal of the data signal terminal to the gate of the driving transistor in response to the signal of the first scan signal terminal.

2. The pixel circuit of claim 1, wherein the first control circuit comprises: a first transistor;

the gate of the first transistor is coupled to the first control signal terminal, the first pole of the first transistor is coupled to the first node, and the second pole of the first transistor is coupled to the reference voltage signal terminal.

3. The pixel circuit of claim 1, wherein the first coupling control circuit comprises: a first capacitor;

The first electrode of the first capacitor is coupled to the gate of the driving transistor, and the second electrode of the first capacitor is coupled to the first node.

4. The pixel circuit of claim 1, wherein the second coupling control circuit comprises: a second capacitor;

the first electrode of the second capacitor is coupled to the first node, and the second electrode of the second capacitor is coupled to the second electrode of the driving transistor.

5. The pixel circuit of claim 1, wherein the second control circuit comprises: a second transistor;

the gate of the second transistor is coupled to the second control signal terminal, the first pole of the second transistor is coupled to the gate of the driving transistor, and the second pole of the second transistor is coupled to the first pole of the driving transistor.

6. The pixel circuit of claim 1, wherein the data write circuit comprises: a third transistor;

The gate of the third transistor is coupled to the first scan signal terminal, the first pole of the third transistor is coupled to the data signal terminal, and the second pole of the third transistor is coupled to the gate of the driving transistor.

7. A pixel circuit as claimed in any one of claims 1 to 6, further comprising: an initialization circuit coupled to the light emitting device and configured to provide a signal of an initialization signal terminal to the light emitting device in response to a signal of a reset signal terminal.

8. The pixel circuit of claim 7, wherein the initialization circuit comprises: a fourth transistor;

The gate of the fourth transistor is coupled to the reset signal terminal, the first pole of the fourth transistor is coupled to the second pole of the driving transistor, and the second pole of the fourth transistor is coupled to the initialization signal terminal.

9. A pixel circuit according to any one of claims 1 to 8, further comprising: a first light emission control circuit is coupled to the first pole of the drive transistor and configured to provide a signal of a first power supply terminal to the first pole of the drive transistor in response to a signal of a first light emission control signal terminal.

10. The pixel circuit of claim 9, wherein the first light emission control circuit comprises: a fifth transistor;

the gate of the fifth transistor is coupled to the first light emitting control signal terminal, the first pole of the fifth transistor is coupled to the first power supply terminal, and the second pole of the fifth transistor is coupled to the first pole of the driving transistor.

11. A pixel circuit according to any one of claims 1 to 10, further comprising: and a second light emission control circuit, which is positioned between the second electrode of the driving transistor and the light emitting device, is coupled with the second electrode of the driving transistor and the light emitting device, and is configured to respond to the signal of the second light emission control signal terminal to conduct the second electrode of the driving transistor with the light emitting device.

12. The pixel circuit of claim 11, wherein the second light emission control circuit comprises: a sixth transistor;

the grid electrode of the sixth transistor is coupled with the second light-emitting control signal end, the first electrode of the sixth transistor is coupled with the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled with the light-emitting device.

13. A pixel circuit according to any one of claims 1 to 12, wherein the gate of the drive transistor comprises: a first gate and a second gate; the first gate of the driving transistor is coupled to the data writing circuit, and the second gate of the driving transistor is coupled to the second pole of the driving transistor.

14. A display device comprising the pixel circuit according to any one of claims 1 to 13.

15. A driving method of a pixel circuit according to any one of claims 1 to 13, comprising:

A reset stage, in which the first control circuit responds to the signal of the first control signal terminal and provides the signal of the reference voltage signal terminal to the first node; the second control circuit responds to a signal of a second control signal end to conduct the grid electrode of the driving transistor with the first pole of the driving transistor;

A threshold compensation stage, wherein the first control circuit responds to the signal of the first control signal terminal and provides the signal of the reference voltage signal terminal to the first node; a first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; a second coupling control circuit stabilizes the voltage of the first node and the voltage of the second pole of the driving transistor;

A data writing stage, in which the data writing circuit responds to the signal of the first scanning signal end and provides the data voltage signal of the data signal end to the grid electrode of the driving transistor; the first control circuit responds to the signal of the first control signal end and provides the signal of the reference voltage signal end to the first node; a first coupling control circuit stabilizes the voltage of the first node and the voltage of the gate of the driving transistor; a second coupling control circuit stabilizes the voltage of the first node and the voltage of the second pole of the driving transistor;

and in the light-emitting stage, the driving transistor generates a driving current for driving the light-emitting device to emit light according to the data voltage signal.