CN113674695A - Pixel circuit, display panel and display device - Google Patents
Pixel circuit, display panel and display device Download PDFInfo
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- CN113674695A CN113674695A CN202110987990.2A CN202110987990A CN113674695A CN 113674695 A CN113674695 A CN 113674695A CN 202110987990 A CN202110987990 A CN 202110987990A CN 113674695 A CN113674695 A CN 113674695A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The pixel circuit of the present disclosure includes: one end of the first storage capacitor is connected with the first node, and the other end of the first storage capacitor is connected with the second node; one end of the second storage capacitor is connected with the second node, and the other end of the second storage capacitor is connected with the third node; the data writing sub-circuit is configured to write a data signal into the first node in response to the second scan signal and charge the first storage capacitor and the second storage capacitor with the data signal; the compensation sub-circuit is configured to write a threshold compensation voltage to the first node in response to a first compensation control signal; the first reset sub-circuit is configured to reset a voltage of the first node with a first power supply voltage signal in response to a first scan signal; the light emission control sub-circuit is configured to output the driving current output from the driving transistor to the light emitting device in response to a light emission control signal; the voltage stabilizing sub-circuit is configured to stabilize a voltage of the second node with the first power supply voltage signal in response to the first scan signal or the second compensation control signal.
Description
Technical Field
The disclosure belongs to the technical field of display, and particularly relates to a pixel circuit, a display panel and a display device.
Background
An Organic Light-Emitting Device (OLED) is a Light-Emitting Device using an Organic solid semiconductor as a Light-Emitting material, and has the advantages of simple preparation process, low cost, low power consumption, high Light-Emitting brightness, wide working temperature application range and the like, so that the OLED has a wide application prospect.
The OLED light emitting device is generally driven by a pixel circuit to emit light to realize a display function, and the pixel circuit includes a driving transistor, a storage capacitor, and other devices, and since a threshold voltage Vth of the driving transistor changes with time, the threshold voltage Vth of the driving transistor in the pixel circuit needs to be compensated. In the high frequency display, since the charging time of the pixels per row is short and the voltages of some nodes in the pixel circuits are unstable, the quality of the threshold voltage Vth compensation is degraded, and display unevenness and other defects are likely to occur.
Disclosure of Invention
The present disclosure is directed to at least one of the problems of the prior art, and provides a pixel circuit, a display panel and a display device.
In a first aspect, an embodiment of the present disclosure provides a pixel circuit, including: the circuit comprises a first storage capacitor, a second storage capacitor, a data writing sub-circuit, a compensation sub-circuit, a driving transistor, a first reset sub-circuit, a light-emitting control sub-circuit, a voltage stabilizing sub-circuit and a light-emitting device;
one end of the first storage capacitor is connected with a first node, and the other end of the first storage capacitor is connected with a second node; one end of the second storage capacitor is connected with the second node, and the other end of the second storage capacitor is connected with the third node;
the data writing sub-circuit is configured to write a data signal into the first node in response to a second scan signal, and to charge the first storage capacitor and the second storage capacitor by the data signal;
the compensation sub-circuit is configured to write a threshold compensation voltage to the first node in response to a first compensation control signal;
the first reset sub-circuit is configured to reset a voltage of the first node with a first power supply voltage signal in response to a first scan signal;
the light emitting control sub-circuit is configured to respond to a light emitting control signal and supply the driving current output by the driving transistor to the light emitting device so as to enable the light emitting device to work;
the voltage regulation sub-circuit is configured to regulate a voltage of the second node with a first power supply voltage signal in response to a first scan signal or a second compensation control signal.
Optionally, the pixel circuit further comprises: a second reset sub-circuit, a third reset sub-circuit and a fourth reset sub-circuit;
the second reset sub-circuit is configured to reset the voltage of the second node with a first power supply voltage signal in response to a first compensation control signal or a second compensation control signal;
the third reset sub-circuit is configured to reset a voltage of the first electrode of the light emitting device with a first power supply voltage signal in response to a first compensation control signal;
the fourth reset sub-circuit is configured to reset a voltage of the third node with a first power supply voltage signal or a reset signal in response to a light emission control signal.
Optionally, the second reset sub-circuit is multiplexed as the voltage regulation sub-circuit, and configured to regulate the voltage of the second node with the first power supply voltage signal in response to a second compensation control signal.
Optionally, the data writing sub-circuit comprises: a first transistor;
the grid electrode of the first transistor is connected with a second scanning signal end, the first pole of the first transistor is connected with a data signal end, and the second pole of the first transistor is connected with the third node.
Optionally, the compensation sub-circuit comprises: a second transistor;
the grid electrode of the second transistor is connected with a first compensation control signal end, the first pole of the second transistor is connected with the second pole of the driving transistor, and the second pole of the second transistor is connected with the first node.
Optionally, the first reset sub-circuit comprises: a fourth transistor;
and the grid electrode of the fourth transistor is connected with a first scanning signal end, the first pole of the fourth transistor is connected with an initialization signal end, and the second pole of the fourth transistor is connected with the first node.
Optionally, the light emission control sub-circuit comprises: an eighth transistor;
and the grid electrode of the eighth transistor is connected with a light-emitting control signal end, the first electrode of the eighth transistor is connected with the second electrode of the driving transistor, and the second electrode of the eighth transistor is connected with the first electrode of the light-emitting device.
Optionally, the voltage regulation sub-circuit comprises: a ninth transistor;
and the grid electrode of the ninth transistor is connected with a first scanning signal end, the first pole of the ninth transistor is connected with a first power supply voltage end, and the second pole of the ninth transistor is connected with the second node.
Optionally, the second reset sub-circuit comprises: a fifth transistor;
and the grid electrode of the fifth transistor is connected with a first compensation signal end, the first pole of the fifth transistor is connected with a first power supply voltage end, and the second pole of the fifth transistor is connected with the second node.
Optionally, the third reset sub-circuit comprises: a sixth transistor;
and the grid electrode of the sixth transistor is connected with a first compensation signal end, the first pole of the sixth transistor is connected with an initialization signal end, and the second pole of the sixth transistor is connected with the first electrode of the light-emitting device.
Optionally, the fourth reset sub-circuit comprises: a seventh transistor;
and the grid electrode of the seventh transistor is connected with a light-emitting control signal end, the first pole of the seventh transistor is connected with a first power supply voltage end or a reset signal end, and the second pole of the seventh transistor is connected with the third node.
In a second aspect, embodiments of the present disclosure provide a display panel including the pixel circuit provided as above.
Optionally, the display panel includes: the data line is connected with the data signal end, the first power supply voltage line is connected with the first power supply voltage end, and the reset signal line is connected with the reset signal end;
the data line, the first power supply voltage line and the reset signal line extend in the same direction, and the first power supply voltage line is located between the data signal line and the reset signal line.
Optionally, the display panel further comprises: a plurality of conductive layers stacked and insulated from each other;
the first power voltage line is made of two layers of the multiple conductive layers;
the reset signal line is made of two layers of the multiple conductive layers.
In a third aspect, embodiments of the present disclosure provide a display device including the display panel provided as described above.
Drawings
FIG. 1 is a schematic diagram of an exemplary pixel circuit;
FIG. 2 is a timing diagram of the pixel circuit shown in FIG. 1;
fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure;
FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 3;
fig. 6 is a timing diagram of the pixel circuit shown in fig. 4.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain. In the embodiments of the present disclosure, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, and the other pole is referred to as a second pole. In addition, the transistors can be divided into an N type and a P type according to the characteristics of the transistors, and in the following embodiment, a P type transistor is used for description, when the P type transistor is adopted, a first electrode is a source electrode of the P type transistor, a second electrode is a drain electrode of the P type transistor, and when a low level is input to a grid electrode, the source electrode and the drain electrode are conducted; when an N-type transistor is adopted, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the grid electrode inputs a high level, the source electrode and the drain electrode are conducted. It is contemplated that an implementation using N-type transistors will be readily apparent to one skilled in the art without inventive effort and, thus, is within the scope of the disclosed embodiments.
It should be noted that, in the embodiment of the present disclosure, for example, all the transistors are P-type transistors, the working level refers to an effective level for turning on the P-type transistors, that is, a low level, and the non-working level refers to a high level. The initial control signal in the embodiment of the present disclosure is a fixed working level, that is, a fixed low level signal. The light emitting device in the embodiments of the present disclosure includes, but is not limited to, an organic electroluminescent diode OLED, and the light emitting device is described as an OLED. The first pole of the OLED is an anode, and the second pole of the OLED is a cathode.
Fig. 1 is a schematic structural diagram of an exemplary pixel circuit, as shown in fig. 1, the pixel circuit includes: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first storage capacitor C1, a second storage capacitor C2, and a light emitting device D; one end of the first storage capacitor C1 is connected to the first node N1, and the other end is connected to the second node N2; one end of the second storage capacitor C2 is connected to the second node N2, and the other end is connected to the third node N3; a gate of the first transistor T1 is connected to the first scan signal terminal Sn, a source thereof is connected to the data signal terminal Vdt, and a drain thereof is connected to the third node N3; the gate of the second transistor T2 is connected to the first compensation control signal terminal AZn of the current row, and the source is connected to the drain of the driving transistor T3; the gate of the driving transistor T3 is connected to the first node N1, the source is connected to the first power voltage terminal Vdd, and the drain is connected to the source of the second transistor T2; a gate of the fourth transistor T4 is connected to the first scan signal terminal Sn, a source thereof is connected to the initialization signal terminal Vinit, and a drain thereof is connected to the first node N1; the gate of the fifth transistor T5 is connected to the first compensation control signal terminal AZn-1 of the previous row, the source is connected to the first power voltage terminal Vdd, and the drain is connected to the second node N2; a gate of the sixth transistor T6 is connected to the first compensation control signal terminal AZn of the current row, a source thereof is connected to the initialization signal terminal Vinit, and a drain thereof is connected to the anode of the light emitting device D; a gate of the seventh transistor T7 is connected to the emission control signal terminal EM, a source thereof is connected to the first power voltage terminal Vdd or the reset signal terminal Vref, and a drain thereof is connected to the third node N3; the eighth transistor T8 has a gate connected to the emission control signal terminal EM, a source connected to the drain of the driving transistor T3, and a drain connected to the anode of the light emitting device D; the light emitting device D has an anode connected to the drain of the sixth transistor T6 and the drain of the eighth transistor T8, and a cathode connected to the second power voltage terminal VSS.
Fig. 2 is a timing diagram of the pixel circuit shown in fig. 1, and as shown in fig. 2, in the first stage, the first scan signal terminal Sn inputs a low level signal, the first transistor T1 and the fourth transistor T4 are turned on, the data signal input from the data signal terminal Vdt is written into the third node N3, and simultaneously, the initialization signal input from the initialization signal terminal Vinit is written into the first node to reset the voltage of the first node N1; in the second stage, a low level signal is input to the first compensation control signal terminal AZn of the row, the second transistor T2 and the sixth transistor T6 are turned on, the threshold voltage Vth of the driving transistor T3 is retrieved, the threshold compensation voltage is written into the first node N1 to compensate the threshold voltage Vth of the driving transistor T3, and an initialization signal input from the initialization signal terminal Vini is written into the anode of the light emitting device D to initialize the anode voltage of the light emitting device; in the reset phase and the threshold voltage acquisition phase, the first compensation control signal terminal AZn-1 of the previous row inputs a low level signal, the fifth transistor T5 is turned on, and the first power voltage signal input from the first power voltage terminal Vdd is written into the second node N2 to reset the voltage of the second node N2; in the third stage, the light emitting control signal terminal EM inputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, and the light emitting device D emits light.
After the voltage of the first node N1 is reset, the data signal is written into the third node N3 until the light emitting device emits light, which is the time for detecting the threshold voltage Vth of the driving transistor T3, and during this time, no voltage signal is input to the third node N3, and the voltage of the original data signal is always maintained, but since the data signal on the data line is constantly unchanged, a parasitic capacitance is easily generated between the data line and the third node N3, so that the voltage of the third node N3 is changed in the second phase. In the third phase, the voltage of the third node N3 is changed from the data signal voltage to the reset signal voltage, and the voltage difference is transferred to the first node N1 through the first storage capacitor C1 and the second storage capacitor C2 connected in series, and the light emitting device D is turned on. However, the voltage of the third node N3 is already inaccurate due to the parasitic capacitance, and since the threshold voltage detection time of the driving transistor T3 is longer than 1H (1H is the charging time of one row of pixel cells), it is easy to make the pixel cells in multiple rows display normally, and cause display non-uniformity and other defects.
In order to solve at least one of the above technical problems, embodiments of the present disclosure provide a pixel circuit, a display panel and a display device, which will be described in further detail with reference to the accompanying drawings and detailed description.
Fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure, and as shown in fig. 3, the pixel circuit includes: a first storage capacitor C1, a second storage capacitor C2, a data writing sub-circuit 301, a compensation sub-circuit 302, a driving transistor T3, a first reset sub-circuit 303, a light emission control sub-circuit 304, a voltage stabilization sub-circuit 305, and a light emitting device D; one end of the first storage capacitor C1 is connected to the first node N1, and the other end is connected to the second node N2; one end of the second storage capacitor C2 is connected to the second node N2, and the other end is connected to the third node N3; the data writing sub-circuit 301 is configured to write a data signal to the first node N1 in response to the second scan signal, and charge the first and second storage capacitors C1 and C2 by the data signal; the compensation sub-circuit 302 is configured to write a threshold compensation voltage to the first node N1 in response to a first compensation control signal; the first reset sub-circuit 303 is configured to reset the voltage of the first node N1 with a first power supply voltage signal in response to a first scan signal; the light emission control sub-circuit 304 is configured to supply the driving current output from the driving transistor T3 to the light emitting device D in response to the light emission control signal to operate the light emitting device D; the voltage stabilizing sub-circuit 305 is configured to stabilize the voltage of the second node N2 with the first power supply voltage signal in response to the first scan signal or the second compensation control signal.
In the pixel circuit provided by the embodiment of the disclosure, the voltage stabilizing sub-circuit 305 may write the first power voltage signal into the second node N2 in response to the first scan signal or the second compensation control signal, so that even when no voltage signal is input to the third node N3, the voltage of the second node N2 may be stabilized, the voltage of the second node N2 and the voltage of the first node N1 are prevented from being affected by the parasitic capacitance, and the stability of the voltage of the data signal written into the first node N1 is ensured, so that the light emitting device may emit light according to the preset brightness, thereby preventing the occurrence of defects such as display unevenness, and further improving the display effect.
In some embodiments, the pixel circuit further comprises: a second reset sub-circuit 306, a third reset sub-circuit 307, and a fourth reset sub-circuit 308; the second reset sub-circuit 306 is configured to reset the voltage of the second node N2 with the first power supply voltage signal in response to the first compensation control signal or the second compensation control signal; the third reset sub-circuit 307 is configured to reset the voltage of the anode of the light emitting device D with the first power supply voltage signal in response to the first compensation control signal; the fourth reset sub-circuit 308 is configured to reset the voltage of the third node N3 with the first power supply voltage signal or the reset signal in response to the light emission control signal.
Specifically, the second reset sub-circuit 306 may reset the voltage of the second node N2 by using the first power voltage signal, the third reset sub-circuit 307 may reset the voltage of the anode of the light emitting device D by using the first power voltage signal, and the fourth reset sub-circuit 308 may reset the voltage of the third node by using the first power signal or the reset signal, so as to ensure that the voltages of the second node N2, the third node N3, and the anode of the light emitting device D are restored to the initialization state when displaying a next frame, thereby avoiding that the voltages written into the nodes when displaying the current frame affect the voltages written into the nodes when displaying the next frame, so that the voltages written into the nodes when displaying the next frame are more accurate, and improving the quality of the displayed frame.
Fig. 4 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure, as shown in fig. 4, in which the second reset sub-circuit 306 is multiplexed as a voltage regulation sub-circuit 305, and is configured to regulate the voltage of the second node N2 by using the first power supply voltage signal in response to the second compensation control signal.
The pixel circuit structure shown in fig. 4 is different from the pixel circuit structure shown in fig. 3 in that, in the pixel circuit shown in fig. 4, the voltage stabilizing sub-circuit 305 is not separately provided, but the control terminal of the second reset sub-circuit 306 is connected to an independent second compensation control signal, and the second reset sub-circuit 306 can be independently controlled by the second compensation control signal, so that the second reset sub-circuit 306 can not only reset the voltage of the second node N2 by the first power voltage signal at different times, but also stabilize the voltage of the second node N2 by the first power voltage signal, avoid the voltage of the second node N2 and the voltage of the first node N1 from being affected by parasitic capacitance, ensure the stability of the voltage of the data signal written into the first node N1, so that the light emitting device can emit light according to a preset brightness, and thus can avoid defects such as display unevenness, and further the display effect can be improved. On the other hand, the number of the transistors can be reduced, so that the structure of the pixel circuit is simpler, the pixel aperture opening ratio is improved, the display brightness is further improved, and the energy consumption is saved.
In some embodiments, as shown in fig. 3 and 4, the data write sub-circuit 301 includes: a first transistor T1; the first transistor T1 has a gate connected to the second scan signal terminal Sn2, a source connected to the data signal terminal Vdt, and a drain connected to the third node N3.
Specifically, the scan signal written to the second scan signal terminal Sn2 is a low signal, the first transistor T1 is turned on, and at this time, the data signal written to the data signal terminal Vdt is written to the first node N1 through the first transistor T1, and the first storage capacitor C1 and the second storage capacitor C2 which are connected in series are charged.
In some embodiments, as shown in fig. 3 and 4, the compensation subcircuit 302 includes: a second transistor T2; the second transistor T2 has a gate connected to the first compensation control signal terminal AZn, a source connected to the drain of the driving transistor T3, and a drain connected to the first node N1.
Specifically, the first compensation control signal terminal AZn is written with a low level signal, the second transistor T2 is turned on, the threshold voltage Vth of the driving transistor T3 can be retrieved, and the first storage capacitor C1 and the second storage capacitor C2 are called to write the threshold compensation voltage into the first node N1, i.e., the gate of the driving transistor T3, so as to compensate the threshold voltage of the driving transistor T3.
In some embodiments, as shown in fig. 3 and 4, the first reset subcircuit 303 includes: a fourth transistor T4; the fourth transistor T4 has a gate connected to the first scan signal terminal Sn, a source connected to the initialization signal terminal Vinit, and a drain connected to the first node N1.
Specifically, the first scan signal terminal Sn writes a low level signal, the fourth transistor T4 is turned on, and the initialization signal written by the initialization signal terminal Vinit changes the forward bias state of the anode and the cathode of the light emitting device D to effectively prevent the unidirectional accumulation of space charges in the organic light emitting layer of the OLED due to the long-term forward bias, thereby stabilizing the light emitting characteristics of the OLED during the light emitting process of the OLED. In some embodiments, the emission control subcircuit 304 includes: an eighth transistor T8; the eighth transistor T8 has a gate connected to the emission control signal terminal EM, a source connected to the drain of the driving transistor T3, and a drain connected to the anode of the light emitting device D.
Specifically, the light emitting control signal terminal EM writes a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first storage capacitor C1 and the second storage capacitor C2 are called at this time, so that the driving current generated by the driving transistor T3 drives the light emitting device D to emit light through the eighth transistor T5.
In some embodiments, as shown in fig. 3, the regulator sub-circuit 305 includes: a ninth transistor T9; the ninth transistor T9 has a gate connected to the first scan signal terminal Sn, a source connected to the first power voltage terminal Vdd, and a drain connected to the second node N2.
Specifically, the first scan signal terminal Sn writes a low level signal, the ninth transistor T9 is turned on, and at this time, the first power voltage signal of the first power voltage terminal Vdd may be written into the second node N2, so that even when no voltage signal is input to the third node N3, the voltage of the second node N2 may be stabilized, the voltage of the second node N2 and the voltage of the first node N1 are prevented from being affected by parasitic capacitance, and the stability of the voltage of the data signal written into the first node N1 is ensured, so that the light emitting device may emit light according to a predetermined brightness, thereby preventing defects such as display unevenness from occurring, and further improving the display effect.
In some embodiments, as shown in fig. 3 and 4, the second reset sub-circuit 306 includes: a fifth transistor T5; the fifth transistor T5 has a gate connected to the first compensation signal terminal AZn, a source connected to the first power voltage terminal Vdd, and a second pole connected to the second node N2.
Specifically, the first compensation signal terminal Azn is written with a low level signal, and the fifth transistor T5 is turned on, so that the first power voltage signal of the first power voltage terminal Vdd can be written into the second node to reset the voltage of the second node N2.
In some embodiments, as shown in fig. 3 and 4, the third reset sub-circuit 307 includes: a sixth transistor T6; the sixth transistor T6 has a gate connected to the first compensation signal terminal AZn, a source connected to the initialization signal terminal Vinit, and a drain connected to the anode of the light emitting device D.
Specifically, the first compensation signal terminal Azn writes a low level signal, and the sixth transistor T6 is turned on, so that the initialization signal of the initialization signal terminal Vinit can be written into the anode of the light emitting device D to reset the voltage of the anode of the light emitting device D.
In some embodiments, as shown in fig. 3 and 4, the fourth reset subcircuit 308 includes: a seventh transistor T7; the seventh transistor T7 has a gate connected to the emission control signal terminal EM, a source connected to the first power voltage terminal Vdd or the reset signal terminal Vref, and a drain connected to the third node N3.
Specifically, the light emission control signal terminal EM writes a low level signal, and the seventh transistor T7 is turned on, so that the first power voltage signal of the first power voltage terminal Vdd or the reset signal of the reset signal terminal Vref can be written to the third node N3 to reset the voltage of the third node N3.
Fig. 5 is a timing diagram of the pixel circuit shown in fig. 3, and fig. 6 is a timing diagram of the pixel circuit shown in fig. 4, and the operation principle of the pixel circuit provided by the embodiment of the disclosure will be described in further detail with reference to the timing diagrams.
As shown in fig. 5, in the first phase, the first scan signal terminal Sn inputs a low level signal, the ninth transistor T9 and the fourth transistor T4 are turned on, the first power voltage signal input from the first power voltage terminal Vdd is written into the second node N2, the initialization signal input from the initialization signal terminal Vinit is written into the first node N1, so as to stabilize the voltage of the second node N2 and reset the voltage of the first node N1; in the second stage, the first compensation control signal terminal AZn inputs a low level signal, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned on, the threshold voltage Vth of the driving transistor T3 is detected, and the threshold compensation voltage is written to the first node N1 to compensate the threshold voltage Vth of the driving transistor T3, and simultaneously an initialization signal input from the initialization signal terminal Vinit is written to the anode of the light emitting device D to reset the anode voltage of the light emitting device, and a first power supply voltage signal or a reset signal is written to the third node N3 to reset the voltage of the third node N3, and a first power supply voltage signal input from the first power supply voltage terminal Vdd is written to the second node N2 to reset the voltage of the second node N2; in the third stage, the second scan signal terminal Sn2 inputs a low level signal, the first transistor T1 is turned on, the data signal inputted from the data signal terminal Vdt is written into the third node N3, and is transmitted to the first node N1 through the first storage capacitor C1 and the second storage capacitor C2 which are connected in series; in the fourth stage, the light emitting control signal terminal EM inputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, and the light emitting device D emits light.
As shown in fig. 6, in the first stage, the second compensation control signal terminal AZn2 inputs a low level signal, the fifth transistor T5 is turned on, the first power voltage signal input from the first power voltage terminal Vdd is written into the second node N2 to stabilize the voltage of the second node N2, the first scan signal terminal Sn inputs a low level signal, the fourth transistor T4 is turned on, and the initialization signal input from the initialization signal terminal Vinit is written into the first node N1 to reset the voltage of the first node N1; in the second stage, the first compensation control signal terminal AZn inputs a low level signal, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned on, the threshold voltage Vth of the driving transistor T3 is detected, and the threshold compensation voltage is written to the first node N1 to compensate the threshold voltage Vth of the driving transistor T3, and simultaneously an initialization signal input from the initialization signal terminal Vini is written to the anode of the light emitting device D to reset the anode voltage of the light emitting device, and a first power supply voltage signal or a reset signal is written to the third node N3 to reset the voltage of the third node N3, and a first power supply voltage signal input from the first power supply voltage terminal Vdd is written to the second node N2 to reset the voltage of the second node N2; in the third stage, the second scan signal terminal Sn2 inputs a low level signal, the first transistor T1 is turned on, the data signal inputted from the data signal terminal Vdt is written into the third node N3, and is transmitted to the first node N1 through the first storage capacitor C1 and the second storage capacitor C2 which are connected in series; in the fourth stage, the light emitting control signal terminal EM inputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, and the light emitting device D emits light.
An embodiment of the present disclosure further provides a display panel, where the display panel includes the pixel circuit provided in any of the above embodiments, and the display panel further includes: a data line connected to the data signal terminal Vdt, a first power voltage line connected to the first power voltage terminal Vdd, and a reset signal line connected to the reset signal terminal Vref; the extension directions of the data line, the first power supply voltage line and the reset signal line are the same, and the first power supply voltage line is positioned between the data signal line and the reset signal line.
In the embodiment of the present disclosure, the data line may provide a data signal for the data signal terminal Vdt, the first power voltage line may provide a first power voltage signal for the first power voltage terminal Vdd, and the reset signal line may provide a reset signal for the reset signal terminal Vref, so as to ensure normal operation of the display panel. Wherein, data signal in the data line is constantly changing for produce electric capacity easily between data line and the reset signal line, cause the interference to the voltage signal in the reset signal line, first mains voltage line can set up between data line and the reset signal line, because first mains voltage in the first mains voltage line is invariable high level signal, can avoid producing parasitic capacitance between data line and the reset signal line, in order to guarantee data line and the stability of the voltage signal in the reset signal line.
In some embodiments, the display panel further comprises: a plurality of conductive layers stacked and insulated from each other; the first power voltage line is made of two layers of the multiple conductive layers; the reset signal line is made of two of the multiple conductive layers.
The first power voltage line can be made of two layers of the multilayer conducting layers, so that impedance on the first power voltage line can be reduced, voltage drop of a first power voltage signal on the first power voltage line is reduced, stability of signal transmission is guaranteed, and energy consumption can be reduced. Similarly, the reset signal line can also be made of two layers of the multiple conducting layers, so that the impedance on the reset signal line can be reduced, the voltage drop of the reset signal line on the reset signal line is reduced, the stability of signal transmission is ensured, and the energy consumption can be reduced.
The embodiment of the present disclosure further provides a display device, where the display device includes the display panel provided in any of the above embodiments, and the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator, and its implementation principle and beneficial effect are the same as those of the display panel and the pixel circuit, and are not described herein again.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (15)
1. A pixel circuit, comprising: the circuit comprises a first storage capacitor, a second storage capacitor, a data writing sub-circuit, a compensation sub-circuit, a driving transistor, a first reset sub-circuit, a light-emitting control sub-circuit, a voltage stabilizing sub-circuit and a light-emitting device;
one end of the first storage capacitor is connected with a first node, and the other end of the first storage capacitor is connected with a second node; one end of the second storage capacitor is connected with the second node, and the other end of the second storage capacitor is connected with the third node;
the data writing sub-circuit is configured to write a data signal into the first node in response to a second scan signal, and to charge the first storage capacitor and the second storage capacitor by the data signal;
the compensation sub-circuit is configured to write a threshold compensation voltage to the first node in response to a first compensation control signal;
the first reset sub-circuit is configured to reset a voltage of the first node with a first power supply voltage signal in response to a first scan signal;
the light emitting control sub-circuit is configured to respond to a light emitting control signal and supply the driving current output by the driving transistor to the light emitting device so as to enable the light emitting device to work;
the voltage regulation sub-circuit is configured to regulate a voltage of the second node with a first power supply voltage signal in response to a first scan signal or a second compensation control signal.
2. The pixel circuit according to claim 1, further comprising: a second reset sub-circuit, a third reset sub-circuit and a fourth reset sub-circuit;
the second reset sub-circuit is configured to reset the voltage of the second node with a first power supply voltage signal in response to a first compensation control signal or a second compensation control signal;
the third reset sub-circuit is configured to reset a voltage of the first electrode of the light emitting device with a first power supply voltage signal in response to a first compensation control signal;
the fourth reset sub-circuit is configured to reset a voltage of the third node with a first power supply voltage signal or a reset signal in response to a light emission control signal.
3. The pixel circuit according to claim 2, wherein the second reset sub-circuit is multiplexed as the regulator sub-circuit configured to regulate the voltage of the second node with the first supply voltage signal in response to a second compensation control signal.
4. The pixel circuit according to claim 1, wherein the data writing sub-circuit comprises: a first transistor;
the grid electrode of the first transistor is connected with a second scanning signal end, the first pole of the first transistor is connected with a data signal end, and the second pole of the first transistor is connected with the third node.
5. The pixel circuit of claim 1, wherein the compensation sub-circuit comprises: a second transistor;
the grid electrode of the second transistor is connected with a first compensation control signal end, the first pole of the second transistor is connected with the second pole of the driving transistor, and the second pole of the second transistor is connected with the first node.
6. The pixel circuit of claim 1, wherein the first reset sub-circuit comprises: a fourth transistor;
and the grid electrode of the fourth transistor is connected with a first scanning signal end, the first pole of the fourth transistor is connected with an initialization signal end, and the second pole of the fourth transistor is connected with the first node.
7. The pixel circuit of claim 1, wherein the light emission control sub-circuit comprises: an eighth transistor;
and the grid electrode of the eighth transistor is connected with a light-emitting control signal end, the first electrode of the eighth transistor is connected with the second electrode of the driving transistor, and the second electrode of the eighth transistor is connected with the first electrode of the light-emitting device.
8. The pixel circuit of claim 1, wherein the voltage regulator sub-circuit comprises: a ninth transistor;
and the grid electrode of the ninth transistor is connected with a first scanning signal end, the first pole of the ninth transistor is connected with a first power supply voltage end, and the second pole of the ninth transistor is connected with the second node.
9. The pixel circuit of claim 2, wherein the second reset sub-circuit comprises: a fifth transistor;
and the grid electrode of the fifth transistor is connected with a first compensation signal end, the first pole of the fifth transistor is connected with a first power supply voltage end, and the second pole of the fifth transistor is connected with the second node.
10. The pixel circuit of claim 2, wherein the third reset sub-circuit comprises: a sixth transistor;
and the grid electrode of the sixth transistor is connected with a first compensation signal end, the first pole of the sixth transistor is connected with an initialization signal end, and the second pole of the sixth transistor is connected with the first electrode of the light-emitting device.
11. The pixel circuit of claim 2, wherein the fourth reset sub-circuit comprises: a seventh transistor;
and the grid electrode of the seventh transistor is connected with a light-emitting control signal end, the first pole of the seventh transistor is connected with a first power supply voltage end or a reset signal end, and the second pole of the seventh transistor is connected with the third node.
12. A display panel comprising the pixel circuit according to any one of claims 1 to 11.
13. The display panel according to claim 12, characterized in that the display panel comprises: the data line is connected with the data signal end, the first power supply voltage line is connected with the first power supply voltage end, and the reset signal line is connected with the reset signal end;
the data line, the first power supply voltage line and the reset signal line extend in the same direction, and the first power supply voltage line is located between the data signal line and the reset signal line.
14. The display panel according to claim 12, characterized by further comprising: a plurality of conductive layers stacked and insulated from each other;
the first power voltage line is made of two layers of the multiple conductive layers;
the reset signal line is made of two layers of the multiple conductive layers.
15. A display device characterized by comprising the display panel according to any one of claims 12 to 14.
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