CN118019099A - Wireless time synchronization method for improving precision - Google Patents
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention relates to the technical field of wireless communication, in particular to a wireless time synchronization method for improving precision, which comprises a host computer and a slave computer, wherein a radio frequency unit, a processing unit, a first frequency divider, a first counter, a second frequency divider and a second counter are arranged in the host computer and the slave computer, and the radio frequency unit is used for the mutual communication of the host computer and the slave computer.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a wireless time synchronization method for improving precision.
Background
The method comprises the steps that after two sides receive and dispatch data packets in a bidirectional exchange mode, local equipment can obtain transmission time stamps T1 and T3 and reception time stamps T2 and T4, and a time offset value OT is calculated according to a general formula OT= (((T2-T1) - (T4-T3))/2) and used for correcting local time; however, the processing time difference between the transmitting and receiving parties when processing the code element is superimposed on the time stamp, so that the time offset value OT is error. To this end, the present invention has developed a wireless time synchronization method that improves accuracy to solve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a wireless time synchronization method for improving precision, which solves the technical problems set forth in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the wireless time synchronization method for improving the precision comprises a master machine and a slave machine, wherein the master machine and the slave machine are internally provided with a radio frequency unit, a processing unit, a first frequency divider, a first counter, a second frequency divider and a second counter;
The radio frequency unit is used for communicating the host computer and the slave computer, the radio frequency unit is electrically connected with the processing unit through a communication connecting wire, a receiving and transmitting interrupt connecting wire and a flag bit interrupt connecting wire, and the radio frequency unit is used for receiving and transmitting time synchronization data packets;
The first frequency divider is electrically connected with the processing unit through a high-speed reference clock connecting wire and a correction data wire, and is respectively electrically connected with the first counter and the second frequency divider;
The second frequency divider is electrically connected with the processing unit through a high-speed reference clock connecting wire and a frequency division data wire;
The first counter and the second counter are respectively electrically connected with the processing unit through counting data lines;
The synchronization method comprises the following steps:
S1: the processing unit controls the master computer and the slave computer to complete two time synchronous data packet exchanges through the radio frequency unit, and the processing unit sets a flag bit in the time synchronous data packet;
S2: the processing unit processes two paths of interrupt signals triggered by the radio frequency unit, respectively records receiving and transmitting time stamps T1, T2, T3 and T4 and receiving zone bit time stamps T5 and T6, and simultaneously performs data communication through a communication connection line and acquires data lengths LI and L2, wherein T1 is a slave machine sending time stamp, T2 is a master machine receiving time stamp, T3 is a master machine sending time stamp, T4 is a slave machine receiving time stamp, T5 is a master machine receiving zone bit time stamp, T6 is a slave machine receiving zone bit time stamp, L1 is a data length from a receiving zone bit T5 to a receiving time stamp T2 obtained by the master machine, and L2 is a data length from the receiving zone bit T6 to the receiving time stamp T4 obtained by the slave machine;
S3: the processing unit calculates the time offset OT according to a general bidirectional time difference calculation formula: ot= (((T2-T1) - (T4-T3))/2);
s4: the processing unit calculates the processing time difference CT of the symbol according to the following formula: ct= ((((T2-T5) - (L1× (1/BR))) - ((T4-T6) - (L2× (1/BR)))))/2, where BR is the baud rate;
s5: the processing unit calculates PT= (OT-CT) according to the following formula by using the time offset OT and the processing time difference CT obtained in the steps S3 and S4, eliminates the processing time difference of code elements, and obtains a high-precision time offset value;
S6: after the high-precision time offset value PT is obtained, the processing unit of the slave corrects the local time by using the PT value, and obtains the local time synchronized with high precision and is synchronized with the local time of the host.
Preferably, the radio frequency unit is two mutually matched radio frequency transceivers, and the two radio frequency transceivers are respectively arranged in the host machine and the slave machine.
Preferably, the processing unit is a single chip microcomputer.
Preferably, the method further comprises the following steps: s7: the processing unit outputs a high-speed reference clock to the first frequency divider, the PT value is used for correcting the frequency division value of the first frequency divider to generate a synchronous clock, the first frequency divider outputs the synchronous clock to drive the first counter, and the first counter generates synchronous second pulse output after finishing the count value set by the processing unit.
Preferably, the method further comprises the following steps: s8: the processing unit outputs a high-speed reference clock to the second frequency divider, the processing unit sets a frequency division value of the second frequency divider to generate a high-speed clock, the synchronous clock output by the first frequency divider periodically resets the second frequency divider to generate a high-speed synchronous clock, the second frequency divider outputs the high-speed synchronous clock to drive the second counter, and the second counter generates synchronous high-speed pulse output after finishing the count value set by the processing unit.
Compared with the prior art, the invention has the beneficial effects that:
when the time of the host computer and the time of the slave computer are synchronized, the symbol processing time difference can be eliminated, so that the accuracy of the time offset value is improved, the effect of improving the time synchronization accuracy is achieved, and the second pulse and the high-speed pulse phase of the slave computer can be synchronized with the second pulse and the high-speed pulse of the host computer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a system connection block diagram of a synchronization device of the present invention;
fig. 2 is a schematic diagram of data obtained after two data exchange by the synchronous device of the present invention are completed.
In the drawings, the list of components represented by the various numbers is as follows:
1. A radio frequency unit; 2. a processing unit; 3. a first frequency divider; 4. a first counter; 5. a second frequency divider; 6. a second counter; t1, the slave sends a time stamp; t2, the host receives the time stamp; t3, the host sends a time stamp; t4, receiving a time stamp by the slave; t5, the host receives the mark bit time stamp; and T6, receiving the flag bit time stamp by the slave.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1: the wireless time synchronization method for improving precision comprises a host computer and a slave computer, wherein the host computer and the slave computer are internally provided with a radio frequency unit 1, a processing unit 2 (the processing unit 2 is preferably an ARM single chip microcomputer), a first frequency divider 3, a first counter 4, a second frequency divider 5 and a second counter 6, the radio frequency unit 1 is used for the host computer and the slave computer to communicate with each other, the radio frequency unit 1 is two radio frequency transceivers matched with each other, the two radio frequency transceivers are respectively arranged in the host computer and the slave computer, the radio frequency unit 1 is electrically connected with the processing unit 2 through a communication connecting wire, a transmit-receive interrupt connecting wire and a flag bit interrupt connecting wire, the radio frequency unit 1 is used for transmitting-receiving time synchronization data packets, the first frequency divider 3 is electrically connected with the processing unit 2 through a high-speed reference clock connecting wire and a correction data wire, the first frequency divider 3 is electrically connected with the first counter 4 and the second frequency divider 5 respectively, the second frequency divider 5 is electrically connected with the processing unit 2 through a high-speed reference clock connecting wire and a frequency dividing data wire, the second frequency divider 5 is electrically connected with the second frequency divider 6, and the first frequency divider 4 and the processing unit 6 is electrically connected with the processing unit 2 respectively through a count data wire.
The synchronization method of the synchronization device specifically comprises the following steps:
When wireless synchronization is performed according to a general bidirectional time difference method, two devices of a host and a slave are required to communicate with each other, the local time of the host is used as a time reference, the second pulse and the high-speed pulse of the host are used as pulse references, the local time of the slave is required to be synchronized with the host, the second pulse and the high-speed pulse of the slave are required to be synchronized with the second pulse and the high-speed pulse of the host, and the hardware devices of the two devices are the same.
S1: the processing unit 2 controls the master and the slave to complete two time synchronous data packet exchanges through the radio frequency unit 1, and the processing unit 2 establishes a flag bit in the time synchronous data packet;
S2: the processing unit 2 processes two paths of interrupt signals triggered by the radio frequency unit 1, respectively records receiving and transmitting timestamps T1, T2, T3 and T4 and receiving zone bit timestamps T5 and T6, and simultaneously performs data communication through a communication connection line and acquires data lengths LI and L2, wherein T1 is a slave machine sending timestamp, T2 is a master machine receiving timestamp, T3 is a master machine sending timestamp, T4 is a slave machine receiving timestamp, T5 is a master machine receiving zone bit timestamp, T6 is a slave machine receiving zone bit timestamp, L1 is a data length from a receiving zone bit T5 to a receiving timestamp T2 obtained by the master machine, and L2 is a data length from a receiving zone bit T6 to a receiving timestamp T4 obtained by the slave machine (as shown in fig. 2);
s3: the processing unit 2 in the slave calculates the time offset OT according to a general bidirectional time difference calculation formula: ot= (((T2-T1) - (T4-T3))/2);
s4: the processing unit 2 in the slave calculates the processing time difference CT of the symbol according to the following formula: ct= ((((T2-T5) - (L1× (1/BR))) ((T4-T6) - (L2× (1/BR)))))/2, where BR is the baud rate, and in this embodiment br=250k;
S5: calculating PT= (OT-CT) by using the time offset OT and the processing time difference CT obtained in the steps S3 and S4 according to the following formula by using a processing unit 2 in the slave machine, and eliminating the processing time difference of code elements to obtain a high-precision time offset value;
S6: after obtaining the high-precision time offset value PT, the processing unit 2 of the slave machine corrects the local time by using the PT value to obtain the high-precision synchronous local time which is synchronous with the local time of the host machine;
S7: the method comprises the steps that a high-speed reference clock is output from a processing unit 2 in the slave machine to a first frequency divider 3, the frequency division value of the first frequency divider 3 is corrected by a PT value to generate a synchronous clock, the first frequency divider 3 outputs the synchronous clock to drive a first counter 4, and the first counter 4 generates synchronous second pulse output after the count value set by the processing unit 2 is completed;
s8: the processing unit 2 in the slave machine outputs a high-speed reference clock to the second frequency divider 5, the processing unit 2 sets the frequency division value of the second frequency divider 5 to generate a high-speed clock, the synchronous clock output by the first frequency divider 3 periodically resets the second frequency divider 5 to generate a high-speed synchronous clock, the second frequency divider 5 outputs the high-speed synchronous clock to drive the second counter 6, and the second counter 6 generates synchronous high-speed pulse output after finishing the count value set by the processing unit 2.
When the time of the host computer and the time of the slave computer are synchronized, the symbol processing time difference can be eliminated, so that the accuracy of the time offset value is improved, the effect of improving the time synchronization accuracy is achieved, and the second pulse and the high-speed pulse phase of the slave computer can be synchronized with the second pulse and the high-speed pulse of the host computer.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "configured," "connected," "secured," "screwed," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other, unless explicitly defined otherwise, the meaning of the terms described above in this application will be understood by those of ordinary skill in the art in view of the specific circumstances.
Although embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
Claims (5)
1. A wireless time synchronization method for improving precision is characterized in that: the system comprises a host machine and a slave machine, wherein a radio frequency unit (1), a processing unit (2), a first frequency divider (3), a first counter (4), a second frequency divider (5) and a second counter (6) are arranged in the host machine and the slave machine;
the radio frequency unit (1) is used for the mutual communication of a host computer and a slave computer, the radio frequency unit (1) is electrically connected with the processing unit (2) through a communication connecting wire, a receiving and transmitting interrupt connecting wire and a flag bit interrupt connecting wire, and the radio frequency unit (1) is used for receiving and transmitting time synchronization data packets;
the first frequency divider (3) is electrically connected with the processing unit (2) through a high-speed reference clock connecting wire and a correction data wire, and the first frequency divider (3) is electrically connected with the first counter (4) and the second frequency divider (5) respectively;
the second frequency divider (5) is electrically connected with the processing unit (2) through a high-speed reference clock connecting wire and a frequency division data wire, the second frequency divider (5) is electrically connected with the second counter (6), and the first counter (4) and the second counter (6) are respectively electrically connected with the processing unit (2) through a counting data wire;
The synchronization method comprises the following steps:
S1: the processing unit (2) controls the master and the slave to complete two time synchronous data packet exchanges through the radio frequency unit (1), and the processing unit (2) sets a flag bit in the time synchronous data packet;
S2: the processing unit (2) processes two paths of interrupt signals triggered by the radio frequency unit (1), respectively records the receiving and transmitting time stamps T1, T2, T3 and T4 and the receiving zone bit time stamps T5 and T6, and simultaneously performs data communication through a communication connecting line to obtain data lengths LI and L2, wherein T1 is a slave machine sending time stamp, T2 is a master machine receiving time stamp, T3 is a master machine sending time stamp, T4 is a slave machine receiving time stamp, T5 is a master machine receiving zone bit time stamp, T6 is a slave machine receiving zone bit time stamp, L1 is a data length from a receiving zone bit T5 to a receiving time stamp T2 obtained by the master machine, and L2 is a data length from the receiving zone bit T6 to the receiving time stamp T4 obtained by the slave machine;
S3: the processing unit (2) in the slave computer calculates the time offset OT according to a general bidirectional time difference calculation formula: ot= (((T2-T1) - (T4-T3))/2);
S4: the processing unit (2) in the slave calculates the processing time difference CT of the code element according to the following formula: ct= ((((T2-T5) - (L1× (1/BR))) - ((T4-T6) - (L2× (1/BR)))))/2, where BR is the baud rate;
S5: calculating PT= (OT-CT) by a processing unit (2) in the slave machine according to the following formula by using the time offset OT and the processing time difference CT obtained in the steps S3 and S4, and eliminating the processing time difference of code elements to obtain a high-precision time offset value;
S6: after obtaining the high-precision time offset value PT, the processing unit (2) of the slave corrects the local time by using the PT value, obtains the local time of high-precision synchronization, and synchronizes with the local time of the host.
2. The method for improving precision of wireless time synchronization according to claim 1, wherein: the radio frequency unit (1) is two mutually matched radio frequency transceivers, and the two radio frequency transceivers are respectively arranged in the host machine and the slave machine.
3. The method for improving precision of wireless time synchronization according to claim 1, wherein: the processing unit (2) is a singlechip.
4. A method of wireless time synchronization with improved accuracy as claimed in claim 3, wherein: the method also comprises the following steps: s7: the method comprises the steps that a high-speed reference clock is output from a processing unit (2) in the slave unit to a first frequency divider (3), the frequency division value of the first frequency divider (3) is corrected by a PT value to generate a synchronous clock, the first frequency divider (3) outputs the synchronous clock to drive a first counter (4), and the first counter (4) generates synchronous second pulse output after the count value set by the processing unit (2) is completed.
5. The method for improving precision of wireless time synchronization according to claim 1, wherein: the method also comprises the following steps: s8: the processing unit (2) in the slave machine outputs a high-speed reference clock to the second frequency divider (5), the processing unit (2) sets a frequency division value of the second frequency divider (5) to generate a high-speed clock, the synchronous clock output by the first frequency divider (3) periodically resets the second frequency divider (5) to generate a high-speed synchronous clock, the second frequency divider (5) outputs the high-speed synchronous clock to drive the second counter (6), and the second counter (6) generates synchronous high-speed pulse output after finishing the count value set by the processing unit (2).
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