CN102098153A - Method and device for self-synchronizing data acquisition system - Google Patents
Method and device for self-synchronizing data acquisition system Download PDFInfo
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- CN102098153A CN102098153A CN2011100277519A CN201110027751A CN102098153A CN 102098153 A CN102098153 A CN 102098153A CN 2011100277519 A CN2011100277519 A CN 2011100277519A CN 201110027751 A CN201110027751 A CN 201110027751A CN 102098153 A CN102098153 A CN 102098153A
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Abstract
The invention provides a method for self-synchronizing a data acquisition system. The invention aims to firstly provide a method for realizing hardware counters by using a CPLD (Complex Programmable Logic Device) and keeping counters between different data acquisition apparatus or between different board cards of the same apparatus in the same counting value, or controlling the counting value error in the counting values in a certain range via a time-delay calculation and a real-time synchronization adjustment method. The apparatus can add time information to each acquired data packet according to the counting values so as to ensure sequence between the different apparatus or board card acquisition data, thereby realize the self-synchronizing of the whole system. The invention provides a self-synchronizing method which is low in cost, easy for implementation, and capable of automatically adjusting according to network state of the apparatus; the method is mainly used for self-synchronizing internal part of the data acquisition apparatus and among the data acquisition apparatuses, and also can be used for the electronic apparatus with other synchronizing requirements.
Description
(1) technical field:
The present invention is the self synchronous a kind of new method of data acquisition system.Be mainly used in the motor synchronizing between data acquisition equipment inside and the data acquisition equipment, also can be applied between other electronic equipments that require synchronously.
(2) background technology:
Data acquisition equipment in the communications field will be gathered the data between each interface in the mobile communications network usually so that carry out data analysis and signaling process, thereby learn current mobile network's situation.Because employed equipment need be connected on the different ports, therefore between the different integrated circuit boards of same equipment and need between the distinct device packet that self-synchronizing system comes each is gathered into carry out before and after in proper order differentiation.Could guarantee the correctness of institute's image data when analyzing and use like this.It is a variety of to realize that synchronous method has, and for example uses GPS or 1588 technology, but self cost of its realization is higher, also very high to the requirement of external equipment.Need external antenna such as GPS, the support of 1588 Technology Need synchronous ethernet networks etc., therefore under the service condition that data acquisition equipment often puts together with mobile communication equipment, these methods are restricted often and are difficult to realize.
Under the condition that desired synchronization accuracy can meet the demands, find a kind of cost low that be easy to realize and can carry out self-adjusting motor synchronizing method according to the networking state of equipment, will well solve this technical barrier.The present invention's research has also realized the self synchronous method of a kind of data acquisition system.
(3) summary of the invention:
The objective of the invention is to propose first to use CPLD to realize hardware counter and by time-delay calculation and the method adjusted in real time, make between the different data acquisition equipment or the different integrated circuit boards of same equipment between counter remain on same count value or within the specific limits with the count value ERROR CONTROL between it.The CPU of data collecting plate card can add time information to each packet of gathering into by the count value of these timers, as shown in Figure 1.Guaranteed like this to distinguish institute image data between the different data acquisition integrated circuit board context, thereby realize the self synchronous method of entire equipment.Also can realize motor synchronizing by this method between equipment and the equipment.
As shown in Figure 2, need motor synchronizing between the integrated circuit board of data acquisition equipment A and between the integrated circuit board of data acquisition equipment B.In the equipment count value of other integrated circuit boards can only with one equate wherein, we are called substrate with this piece integrated circuit board.Though there is an integrated circuit board to be selected as substrate, it is the same with other integrated circuit boards on hardware designs, and therefore any integrated circuit board can both be selected as substrate.
To realize between two equipment synchronously, need substrate between two equipment to communicate to revise count value the count value of two equipment substrates is equated, the mode of packet is adopted in communication between substrate, transmit by external sync cap, its concrete form as shown in Figure 3, it comprises packet header, bag content and crc value.Its middle wrapping head comprises two parts content, promptly by the numbering of equipment substrate and bag type.The equipment substrate number is mainly distinguished the substrate of distinct device on the sync cap, and the bag type is meant the function and usage of bag that substrate sends.The bag type of using among the present invention comprises time-delay calculation bag, synchronous bag and the broadcast packet adjusted.The time-delay calculation bag is mainly used to calculate time-delay, adjusts bag synchronously and directly controlled substrate counter is adjusted, and broadcast packet is used for same device interior motor synchronizing and uses.Its bag content of packet for difference bag type is also different, please referring to Fig. 3.
Realize that thereby Counter Value between two equipment substrates equate to realize that motor synchronizing will be by finishing between integrated circuit board through consultation, its negotiations process as shown in Figure 4.At first, the substrate transmission delay of A equipment calculates bag, and its bag content is the current count value of substrate counter.The substrate of B equipment in CRC check in correct and packet header be numbered self numbering substantially the time just can respond, when finding that packet header Zhong Bao type is the time-delay calculation bag, directly the content that will wrap returns to the substrate of A equipment.The substrate of A equipment calculates the time-delay of circuit by the bag content of this packet and the count value of self current counter.The substrate of A equipment sends and to adjust bag synchronously subsequently, its bag content be its current count value with time-delay result of calculation with, in transmission course, compensate its count value to guarantee it.The substrate of B equipment just can respond when the integrated circuit board in correct and packet header is numbered self numbering in CRC check, finding that packet header Zhong Bao type is when adjusting bag synchronously, numerical value in the bag content that receives is write direct will be identical with the Counter Value of A equipment substrate behind self the counter, and then finish motor synchronizing.
The calculating principle of circuit delay is as follows, has the following steps at time-delay calculation packet process of transmitting, and A equipment substrate sends, the circuit transmission, and B equipment substrate receives, and B equipment substrate sends, the circuit transmission, A equipment substrate receives.When the distance between two equipment was far away, the time-delay of circuit transmission should be considered.Because tranmitting data register and the used clock homology of counter of sync cap, so the every transmission of sync cap of two equipment substrates or receive the data of a bit, the value of counter is also mutually deserved to add 1.Though the clock frequency at two equipment substrates transmissions and receive time delay calculated data bag may be slightly different, but its error can not have influence on count value must be changed, therefore can ignore fully, and the substrate of B equipment postbacks it immediately in next clock cycle after receive time delay calculated data bag is finished, therefore the substrate of A equipment send and the difference of himself Counter Value during receive time delay calculated data bag except that 2, be circuit delay just, be designated as M.Concrete computational methods be exactly the substrate of A equipment after the bag content that receives the packet that B equipment substrate returns, its count value with self current counter is subtracted each other the back promptly gets M except that 2.
Calculating is finished metacoxal plate and is sent synchronous adjustment packet again, the clock periodicity of circuit delay is compensated, specific practice be exactly the bag content of adjusting bag synchronously be that the current Counter Value of substrate adds M.Substrate at B equipment receives this packet, and after the value that will wrap content write its counter, the count value of two integrated circuit boards was finished motor synchronizing with identical.
In the common same equipment, sync cap between the integrated circuit board often is connected by backboard, so the cable run distance of sync cap is very short, calculates with per thousand mil of signal lag 180ps, cabling is circuit delay 1.8ns under the situation of 250mm, is equivalent to a clock cycle of 550Mhz clock.Usually the cabling in the same system can not surpass 250mm, and therefore required precision can be satisfied in most cases, does not need to carry out the calculating of circuit delay.Because distance is short, it almost is simultaneously with received packet by synchronous plate that substrate sends packet, so the direct count value that sends oneself adds that the packet length N that sends packet gets final product in the bag content of the packet that substrate sends, quilt integrated circuit board synchronously directly is worth the Counter Value of adjusting self according to this.Owing to do not need other integrated circuit boards that substrate is had the return data bag, therefore the basic packet that sends can be called " broadcast packet " and represent that therefore the information of bag type can be the customizing messages of expression broadcast packet, number-mark sends the substrate number of this broadcast packet in the packet header, for the ease of handling it in internally sync cap transmission.In the same equipment other are only responded the broadcast packet that own equipment plate card sends over by synchronous plate.Therefore self synchronous process is reduced to shown in Figure 5 in same equipment.Therefore negotiations process shown in Figure 4 only occurs between the substrate of two equipment, does not need at device interior.
In order to control synchronization accuracy and to prevent unexpected the generation, the substrate between two equipment will carry out timing synchronously, promptly carries out once above-described synchronizing process at regular intervals.If two employed clocks of equipment are with frequently then carry out a synchronizing process and get final product in theory, but the counting clock between distinct device is different often frequently, so need adjust in real time as required, promptly must adjust synchronously once more at set intervals.Its is selected and following two relating to parameters in time interval, promptly the precision of patient counting error scope and used counting clock.Being 10Mhz ± 1ppm with the precision of the counting clock of two equipment is example, the counting clock of two equipment differs 2ppm at most, be per second difference 20hz, the counter that is to say two equipment rooms may differ 20 count values at most in value in 1 second, the count value of supposing two equipment rooms of permission differs less than 10, does not then have 0.5 second needs once to adjust.Even like this between the equipment because relative position changes, cause that the wire length of sync cap changes between the equipment, do not need manual intervention yet, it will realize motor synchronizing next time after carrying out adjusting synchronously.In same equipment, the employed clock of the counter of all integrated circuit boards is easy to realize homology, and its relative distance also can not change, and does not generally need to carry out once more synchronously, only carries out synchronizing process once more under the situation that new integrated circuit board insertion or other integrated circuit board power down are arranged.Be generally prevent that above-mentioned situation from causing unusual, after the substrate of two equipment rooms was finished synchronously, the substrate of each equipment internally sent a broadcast packet immediately and gets final product.
(4) description of drawings:
Motor synchronizing realizes schematic diagram between Fig. 1 data collecting plate card;
Each integrated circuit board sync cap connection diagram of Fig. 2 equipment room and device interior;
Fig. 3 packet structure schematic diagram;
Fig. 4 synchronizing process schematic diagram;
Fig. 5 device interior data collecting plate card synchronizing process schematic diagram;
Fig. 6 implementation method schematic diagram of the present invention;
Fig. 7 CPLD cut-away view;
Number in the figure is described as follows:
The local crystal oscillator 2-CPLD of 1-3-data acquisition interface
The external sync cap 6-of 4-phase-locked loop 5-is to interior sync cap
(5) embodiment:
The present invention is the self synchronous a kind of new method of data acquisition system.Its implementation as shown in Figure 6, the local clock that local crystal oscillator (1) produces meets the global clock pin GC of CPLD (Complex Programmable LogicDevice) (2).Also insert the GC of CPLD (2) after line-recovered clock process phase-locked loop (4) frequency multiplication of data acquisition interface (3).The GPIO of CPLD (2) realizes external sync cap (5) and internal sync cap (6).CPLD (2) communicates with the mode of master cpu (7) by register.
The characteristics that CPLD is programmable and implementation is easily changed, be widely used in the design of digital circuit, the CPLD among the present invention mainly realizes following function: with CPU communication interface, counter, CRC maker, CRC check device, pin multiplexing logic etc. as shown in Figure 6 shown in the empty frame of CPLD.Wherein the tranmitting data register of the counting clock of counter and sync cap needs homology, is designed to synchronous logic, guarantees that the value of sync cap transmission 1bit data counter adds 1.
Among the present invention the internal structure of CPLD as shown in Figure 7, itself and CPU communication interface be mainly open a following register, Counter Value register, working mode selection register, state alarm register, regularly the sync interval time is provided with register.These registers are mainly used in CPU and read the count value of CPLD and CPLD is controlled.These registers will hang under the parallel bus of CPU self, and CPU can directly visit by its inner addressing space.
The Counter Value register is used for the count value that CPU reads the CPLD counter, comes to add time information is gathered bag with the district office sequencing for each packet of gathering into.
It is as substrate or by synchronous plate and set multiplexing logic of GPIO and the input and output direction of CPLD that the working mode selection register is used for the used counting clock of gated counter and this integrated circuit board.In the working method register, select the employed clock of CPLD counter can also can use the recovered clock of institute's acquisition interface for local crystal oscillator, the frequency of general recovered clock is lower, recovered clock as the E1 interface is 2.048MHZ, therefore need add phase-locked loop clock frequency is brought up in the available scope.Its counting clock is selected and can be carried out with data acquisition interface type and current state, can be by joining under the CPU automatic or manual.Pin multiplexing logic that this register is controlled guarantees to receive and sends and all realizes on the same GPIO of CPLD, has reduced the quantity of cabling, also can guarantee in the CPLD logical design at substrate to be identical with other by synchronous plate.When it is chosen as by synchronous plate, only stays internal sync cap and be set to input.If elect substrate as then its external sync cap is made as two-wayly, only other are input constantly for output when sending, and internally sync cap gets final product for output.
State alarm register is used to react synchronous regime, CRC (Cyclic RedundancyCheck) fault alarm for example occurs, the state that sends and receive etc.
To occur mistake in the data transmission procedure in order preventing among the design, data to have been carried out CRC check.By substrate the packet header and the bag content that send packet are carried out the CRC computing, and the some of operation values as packet sent together, carried out same CRC computing by synchronous plate packet header and bag content to the packet that receives after receiving packet, and result calculated compared with the CRC that receives, think in the time of consistent that transmission is correct.It is specifically realized by CRC maker and CRC check device, it is designed to asynchronous logic and carries out the CRC computing, can guarantee the real-time that data send and receive like this, thereby some bit that the method for CRC computing is about in packet header and the bag content bit sequence carries out the bit position that XOR obtains CRC.
Regularly the sync interval time is provided with register and is mainly used in regularly synchronization of time intenals of design.This register mainly is provided with the divide ratio of counting clock, is time reference with the counting clock, regularly initiates synchronizing process.
The simple calculations logic is meant when time-delay is calculated subtracts each other the value of current Counter Value and return value register and calculates time-delay except that 2.
Claims (7)
1. self synchronous implementation method of data acquisition equipment, use hardware counter and by time-delay calculation and the method adjusted in real time, make counter between the different data acquisition equipment remain on same count value or within the specific limits the count value ERROR CONTROL between it; Equipment can add time information to each packet of gathering into by these count values, has guaranteed to distinguish the context between the distinct device image data like this, thereby has realized the self synchronous method of whole system.
2. the self synchronous implementation method of a kind of data acquisition equipment according to claim 1, it is characterized in that: use can be weaved into logic device (CPLD) and realize hardware counter and sync cap and carry out CRC check, sync cap sends employed clock of data and the employed clock homology of its rolling counters forward, and is synchronous to guarantee data transmission procedure and rolling counters forward process.
3. the self synchronous implementation method of a kind of data acquisition equipment according to claim 1, it is characterized in that: the form of its bag that transmits and receive data, be divided into packet header, bag content and CRC three parts, packet header is used to deposit the synchronous integrated circuit board numbering of wanting and the information of sign packet function, the bag content is the synchronous numerical value after count value or process are calculated, and CRC is in order to prevent data transmission errors.
4. the self synchronous implementation method of a kind of data acquisition equipment according to claim 1 is characterized in that: calculate each transmission, transmit and accept the used circuit time delay of packet by the mode of external sync cap transmission and receive time delay calculated data bag between the substrate of two equipment; Computational methods deduct the bag content of received packet for the main equipment substrate with current Counter Value and obtain after 2.
5. the self synchronous implementation method of a kind of data acquisition equipment according to claim 1, it is characterized in that: the substrate of main equipment makes that by sending synchronous adjustment packet the substrate of other equipment is synchronous with oneself, and the bag content of adjusting packet synchronously is that the current Counter Value of substrate adds the circuit time delay.
6. the self synchronous implementation method of a kind of data acquisition equipment according to claim 1, it is characterized in that: carry out when synchronous at the integrated circuit board of same device interior, do not need the calculating of delaying time, it is the bit figure place N that the count value of current counter adds packet that substrate directly sends " broadcast packet " its bag content, and other are received that by integrated circuit board synchronously " broadcast packet " back directly writes the content of bag self counter and carries out synchronously.
7. the self synchronous implementation method of a kind of data acquisition equipment according to claim 1 is characterized in that: adopt and regularly to carry out synchronous mode and guarantee that Counter Value error between different integrated circuit boards is in certain scope; In order to control synchronization accuracy and to prevent unexpected the generation, the time interval should be satisfied formula: T＜u/ (F * a).Wherein T is regularly a synchronization of time intenals, unit second; U is the maximum count error that allows between integrated circuit board, and F is employed counting clock frequency, the Mhz of unit; A is the maximal accuracy error of counting clock between integrated circuit board, the ppm of unit.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102607645A (en) * | 2012-02-24 | 2012-07-25 | 华为终端有限公司 | Data acquisition method, data acquisition device and mobile terminal |
| CN103124204A (en) * | 2011-11-18 | 2013-05-29 | 北京旋极信息技术股份有限公司 | Signal relay system, data transmission method thereof and data transmission format thereof |
| CN103684735A (en) * | 2013-11-12 | 2014-03-26 | 航天科工深圳（集团）有限公司 | Synchronous method of distributed device |
| CN107147443A (en) * | 2017-05-08 | 2017-09-08 | 重庆邮电大学 | A kind of synthesis of photon detection array signal and open loop synchronous method |
| CN111830340A (en) * | 2020-06-18 | 2020-10-27 | 中国电力科学研究院有限公司 | Method and device for evaluating performance of relay protection device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200941609Y (en) * | 2006-08-24 | 2007-08-29 | 中国科学院武汉物理与数学研究所 | Digital precision phaser |
| CN101080894A (en) * | 2004-12-16 | 2007-11-28 | 三星电子株式会社 | Synchronization method and apparatus and location awareness method and apparatus in chaotic communication system |
| CN101755419A (en) * | 2007-05-21 | 2010-06-23 | 思达伦特网络公司 | Globally synchronized timestamp value counter |
-
2011
- 2011-01-26 CN CN2011100277519A patent/CN102098153A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101080894A (en) * | 2004-12-16 | 2007-11-28 | 三星电子株式会社 | Synchronization method and apparatus and location awareness method and apparatus in chaotic communication system |
| CN200941609Y (en) * | 2006-08-24 | 2007-08-29 | 中国科学院武汉物理与数学研究所 | Digital precision phaser |
| CN101755419A (en) * | 2007-05-21 | 2010-06-23 | 思达伦特网络公司 | Globally synchronized timestamp value counter |
Non-Patent Citations (1)
| Title |
|---|
| 陈靖等: "高速数据采集***中精确时标的CPLD实现方法", 《继电器》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103124204A (en) * | 2011-11-18 | 2013-05-29 | 北京旋极信息技术股份有限公司 | Signal relay system, data transmission method thereof and data transmission format thereof |
| CN102607645A (en) * | 2012-02-24 | 2012-07-25 | 华为终端有限公司 | Data acquisition method, data acquisition device and mobile terminal |
| CN102607645B (en) * | 2012-02-24 | 2014-12-03 | 华为终端有限公司 | Data acquisition method, data acquisition device and mobile terminal |
| US9483543B2 (en) | 2012-02-24 | 2016-11-01 | Huawei Device Co., Ltd. | Data collecting method and apparatus, and mobile terminal |
| CN103684735A (en) * | 2013-11-12 | 2014-03-26 | 航天科工深圳（集团）有限公司 | Synchronous method of distributed device |
| CN107147443A (en) * | 2017-05-08 | 2017-09-08 | 重庆邮电大学 | A kind of synthesis of photon detection array signal and open loop synchronous method |
| CN107147443B (en) * | 2017-05-08 | 2019-04-26 | 重庆邮电大学 | A kind of synthesis of photon detection array signal and open loop synchronous method |
| CN111830340A (en) * | 2020-06-18 | 2020-10-27 | 中国电力科学研究院有限公司 | Method and device for evaluating performance of relay protection device |
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