CN108155965A - SDH transmits IEC61588 methods - Google Patents
SDH transmits IEC61588 methods Download PDFInfo
- Publication number
- CN108155965A CN108155965A CN201711480648.3A CN201711480648A CN108155965A CN 108155965 A CN108155965 A CN 108155965A CN 201711480648 A CN201711480648 A CN 201711480648A CN 108155965 A CN108155965 A CN 108155965A
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- Prior art keywords
- ethernet
- clock
- module
- ptp
- sdh
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of SDH to transmit IEC61588 methods.Step S1：Level-one PTP master clocks include the Ethernet code stream of PTP protocol message by Ethernet transmission.Step S2：Ethernet code stream in step S1 is converted to E1 HDB3 code streams by protocol converter.Step S3：SDH network transmits the E1 HDB3 code streams in step S2 step by step.Step S4：E1 HDB3 code streams in step S3 are converted to Ethernet code stream by protocol converter.Step S5：PTP protocol message is obtained, and the time from clock is adjusted according to the hardware timestamping of above-mentioned PTP protocol message from clock from the Ethernet code stream in step S4.SDH disclosed by the invention transmits IEC61588 methods, transmits clock signal using SDH transmission and then is effectively saved cost, while the precision of PTP networkings is higher, nanosecond class precision is can reach by accurately compensating.
Description
Technical field
The invention belongs to Clock Synchronization Technology fields, and in particular to a kind of SDH transmits IEC61588 methods.
Background technology
With power grid develop towards intelligentized direction and measuring and control data acquisition, the networking of transmission, to time calibration in network
Precision propose higher requirement.IEC61588, also referred to as PTP, it is synchronous with the precision interval clock measured to be directed to Industry Control
Consensus standard, the especially distributed motion control field of automation generate it keen interest, in the world military field should
With also having started to walk, the related fields such as telecommunication and electric system are applied to also flourish.
The realization of clock synchronization system mainly carries out satellite positioning by the GPS/BD receivers that each system carries at present
It completes, however the receiver apparatus spread in performance of each producer is uneven, precision differs and mutual isolated operation, can not ensure each system
Time synchronization between system, and reliability is low, can not realize centralized management and monitoring.
Invention content
The present invention is directed to the situation of the prior art, provides a kind of SDH transmission IEC61588 methods.
The present invention includes pressing step below using following technical scheme, the SDH transmission IEC61588 methods：
Step S1：Level-one PTP master clocks include the Ethernet code stream of PTP protocol message by Ethernet transmission；
Step S2：Ethernet code stream in step S1 is converted to E1HDB3 code streams by protocol converter；
Step S3：SDH network transmits the E1HDB3 code streams in step S2 step by step；
Step S4：E1HDB3 code streams in step S3 are converted to Ethernet code stream by protocol converter；
Step S5：PTP protocol message is obtained, and assist according to above-mentioned PTP from clock from the Ethernet code stream in step S4
The hardware timestamping adjustment of message is discussed from the time of clock.
According to above-mentioned technical proposal, the protocol converter uses E1/Ethernet protocol converters.
According to above-mentioned technical proposal, the protocol converter includes：
E1 transceivers, FPGA module and CPU module establish both-way communication company between the E1 transceivers and FPGA module
It connects, both-way communication connection is established between the CPU module and FPGA module；
Network transformer establishes both-way communication connection, the network transformation between the network transformer and E1 transceivers
Device is connected with bnc interface, and the network transformer is connected by common mode inductance with RJ45 interfaces.
According to above-mentioned technical proposal, the protocol converter further includes：
First clock module, first clock module are connected with E1 transceivers；
Second clock module, the second clock module are connected with CPU module；
First jtag interface establishes both-way communication connection between first jtag interface and CPU module；
Reset key and LED state indicator light, the reset key and LED state indicator light respectively with FPGA module phase
Even；
Second jtag interface establishes both-way communication connection between second jtag interface and FPGA module；
50Mhz crystal oscillators and 2 frequency multiplication chips, the 50Mhz crystal oscillators are connected by 2 frequency multiplication chips with FPGA module；
Ethernet transceiver and the RJ45 interfaces with network transformer, the FPGA module pass through ethernet transceiver and band
The RJ45 interfaces of network transformer are connected, described to be connected simultaneously with CPU module with outer net transceiver.
SDH disclosed by the invention transmits IEC61588 methods, and advantage is, is transmitted using SDH with transmission clock
Signal and then cost is effectively saved, while the precision of PTP networkings is higher, nanosecond class precision is can reach by accurately compensating.
Description of the drawings
Fig. 1 is PTP over SDH time synchronization networking schematic diagrams.
Fig. 2 is PTP Primary Clock node schematic diagrames.
Fig. 3 is two level clock synchronization compliant with precision time protocol node schematic diagram.
Fig. 4 is the function structure chart of protocol converter.
Fig. 5 is the Delay computing flow chart of protocol converter.
Fig. 6 is the system block diagram of the preferred embodiment of the present invention.
Fig. 7 is the function structure chart of the IEC61588 protocol modules in Fig. 6.
Fig. 8 is the function structure chart of the timestamp unit in Fig. 6.
Fig. 9 is timestamp capture moment schematic diagram.
Figure 10 is to obtain timestamp process status machine schematic diagram.
Figure 11 is timestamp transmittance process schematic diagram.
Figure 12 is the function structure chart of the local clock unit in Fig. 6.
Specific embodiment
The invention discloses a kind of SDH to transmit IEC61588 methods, with reference to preferred embodiment, to the specific of the present invention
Embodiment is further described.
Referring to Figure 1 of the drawings to Figure 12, the operation principle of the SDH transmission IEC61588 methods is shown.
Referring to Figure 1 of the drawings to Fig. 3, PTP protocol message is transmitted by SDH.In the user interface of SDH, typically
E1 interfaces convert the HDB3 code streams of E1 (protocol converter) and Ethernet protocol code stream form.As shown in Fig. 2, when
Between at source, master clock (level-one PTP master clocks) sends out protocol massages by Ethernet, through protocol converter, by Ethernet code stream
E1HDB3 code streams are converted into, are then transmitted step by step by SDH network, are reached before clock, as shown in figure 3, using agreement
E1HDB3 code streams are converted into Ethernet code stream by converter, to pass to from clock.From clock according to the hardware of these messages
Timestamp calculates and adjusts the time from clock.
In other words, the SDH transmission IEC61588 methods include the following steps：
Step S1：Level-one PTP master clocks include the Ethernet code stream of PTP protocol message by Ethernet transmission；
Step S2：Ethernet code stream in step S1 is converted to E1HDB3 code streams by protocol converter；
Step S3：SDH network transmits the E1HDB3 code streams in step S2 step by step；
Step S4：E1HDB3 code streams in step S3 are converted to Ethernet code stream by protocol converter；
Step S5：PTP protocol message is obtained, and assist according to above-mentioned PTP from clock from the Ethernet code stream in step S4
The hardware timestamping adjustment of message is discussed from the time of clock.
Referring to Fig. 4 of attached drawing, the protocol converter (E1/Ethernet protocol converters), mainly including following 4 portions
Point.
(1) Ethernet transmission circuit：It is responsible for the conversion of ethernet hardware interface and agreement；It is responsible for the receipts of Ethernet data
Hair.
(2) E1 transmission circuits：It is responsible for the conversion of E1 hardware interfaces and agreement；It is responsible for the transmitting-receiving of E1 data.
(3) field programmable gate array (FPGA) circuit：It is responsible for completing the bidirectional protocol conversion between Ethernet and E1, and
Accurately calculate the delay converted therebetween.
(4) processor circuit：The communication of host computer is assisted, completes host computer to the inquiry of equipment and parameter configuration function；
It is responsible for the power-up initializing configuration of E1 transceivers；It is responsible for the power-up initializing configuration of ethernet transceiver；Host computer setting
Parameter passes to fpga chip.
In other words, the protocol converter is preferably using E1/Ethernet protocol converters, the protocol converter packet
It includes：
E1 transceivers, FPGA module and CPU module establish both-way communication company between the E1 transceivers and FPGA module
It connects, both-way communication connection is established between the CPU module and FPGA module；
Network transformer establishes both-way communication connection, the network transformation between the network transformer and E1 transceivers
Device is connected with bnc interface, and the network transformer is connected by common mode inductance with RJ45 interfaces；
First clock module, first clock module are connected with E1 transceivers；
Second clock module, the second clock module are connected with CPU module；
First jtag interface establishes both-way communication connection between first jtag interface and CPU module；
Reset key and LED state indicator light, the reset key and LED state indicator light respectively with FPGA module phase
Even；
Second jtag interface establishes both-way communication connection between second jtag interface and FPGA module；
50Mhz crystal oscillators and 2 frequency multiplication chips, the 50Mhz crystal oscillators are connected by 2 frequency multiplication chips with FPGA module；
Ethernet transceiver and the RJ45 interfaces with network transformer, the FPGA module pass through ethernet transceiver and band
The RJ45 interfaces of network transformer are connected, described to be connected simultaneously with CPU module with outer net transceiver.
Referring to Fig. 5 of attached drawing, link delay includes hardware handles delay T1 and protocol conversion delay T2, and code stream is from Ethernet
It when being passed in and out between interface and E1 interfaces, is recorded by FPGA, when protocol conversion delay T2, T1 is obtained after subtracting each other as the fixed processing of hardware
Prolong.
Referring to Fig. 6 of attached drawing, PTP group network systems include IEC61588 protocol engine modules, timestamp unit, local clock
Unit.
Referring to Fig. 7 of attached drawing, the IEC61588 protocol engine modules include IEC61588 protocol elements and with
PTP ports that IEC61588 protocol elements are connected, clock synchronization compliant with precision time protocol interface, PTP timestamps interface, PTP log services interfaces, it is described
The driving of PTP ports and network interface is connected, and the clock synchronization compliant with precision time protocol interface drives with clock to be connected, the PTP timestamps make an excuse and when
Between stamp driving be connected.
Referring to Fig. 8 of attached drawing, the timestamp unit is responsible for beating timestamp to the disengaging of IEC61588 messages, including message
Resolver, timestamp clock, the queue for storage time stamp.Packet parsing device is linked on the MII interfaces of network, for supervising
Survey the data sent and received.Once PTP messages are detected, it will the timestamp and message of recorded message in queue
Some attributes supply subsequent processing.Meanwhile a timestamp sampling clock built in timestamp unit, for beating for event message
Stamp.
Referring to Fig. 9 of attached drawing, the capture of timestamp can be serviced at application layer (C in Fig. 9) in kernel or other interruptions
Program (B in Fig. 9) or at physical layer (A in Fig. 9).Closer to true network connection, the error of generation is with regard to smaller.
This method will be stabbed in physical layer capture time.
Table one
| Ethernet packet header | IP | UDP packet header | PTP packet header and data |
Referring to table 1, in order to identify PTP packets, hardware will identify the heading of four kinds of procotols, be Ethernet in order,
IP agreement, udp protocol and PTP protocol.Figure 10 shows the institutional framework of the message under network bytes sequence.
Timestamp unit is found and parses the qualified message of all disengaging, comprising IP agreement data, UDP packet header,
And UDP destination interfaces etc..SYNC the and DELAY request messages of only PTP allow to use the udp port.If these conditions
All meet, some attributes of hardware event stamp and the PTP messages will be conserved to be used for software.
Referring to Figure 1 of the drawings 0, it obtains timestamp process status machine and includes following state：
1. idle state
2. read receiving queue：It finds PTP and receives the relevant timestamp of event
3. read transmit queue：It finds PTP and sends the relevant timestamp of event
4. deposit timestamp state：It preserves PTP and receives Event Timestamp
5. deposit sending time stamp：It preserves PTP and sends Event Timestamp.
Referring to Figure 1 of the drawings 1, elaborate how the timestamp that hardware obtains passed into PTP protocol stack.The interface is ceaselessly
The timestamp newly received is detected, when a new timestamp reaches the interface, time stamp data will be forwarded to PTP protocol
Stack.
Wherein, the local clock unit adjusts two parts by clock timing and temporal frequency and forms, and is the PTP networking times
Synchronization system realizes key at accurate pair.Clock timing part mainly maintains the normal time when walking, time adjustment part
Algorithm is mainly adjusted by clock to improve the precision of local clock.
Referring to Figure 1 of the drawings 2, elaborate frequency calibration principle.When being triggered from the referrer module of clock, if
When FreqOsc deviates FreqCnt, the size of FreqCompValue values is recalculated by clock skew Offset from clock and is tired out
The value of device itself is added to be added, and judge whether the carry flag in accumulator overflows, in case of overflowing, system time increases by one
The numerical value of a clock cycle realizes the relative constant of Freqcnt values, i.e., rate is constant when clock is walked, conversely, then counter is protected
It holds constant.
For a person skilled in the art, the technical solution recorded in foregoing embodiments can still be repaiied
Change or equivalent replacement is carried out to which part technical characteristic, all within the spirits and principles of the present invention, that is made any repaiies
Change, equivalent replacement, improvement etc., should be included in protection scope of the present invention.
Claims (4)
1. a kind of SDH transmits IEC61588 methods, which is characterized in that includes the following steps：
Step S1：Level-one PTP master clocks include the Ethernet code stream of PTP protocol message by Ethernet transmission；
Step S2：Ethernet code stream in step S1 is converted to E1 HDB3 code streams by protocol converter；
Step S3：SDH network transmits the E1 HDB3 code streams in step S2 step by step；
Step S4：E1 HDB3 code streams in step S3 are converted to Ethernet code stream by protocol converter；
Step S5：PTP protocol message is obtained, and according to above-mentioned PTP protocol report from clock from the Ethernet code stream in step S4
The hardware timestamping of text adjusts the time from clock.
2. SDH according to claim 1 transmits IEC61588 methods, which is characterized in that the protocol converter uses E1/
Ethernet protocol converters.
3. SDH according to claim 1 transmits IEC61588 methods, which is characterized in that the protocol converter includes：
E1 transceivers, FPGA module and CPU module establish both-way communication connection, institute between the E1 transceivers and FPGA module
It states and both-way communication connection is established between CPU module and FPGA module；
Network transformer, established between the network transformer and E1 transceivers both-way communication connection, the network transformer with
Bnc interface is connected, and the network transformer is connected by common mode inductance with RJ45 interfaces.
4. SDH according to claim 3 transmits IEC61588 methods, which is characterized in that the protocol converter further includes：
First clock module, first clock module are connected with E1 transceivers；
Second clock module, the second clock module are connected with CPU module；
First jtag interface establishes both-way communication connection between first jtag interface and CPU module；
Reset key and LED state indicator light, the reset key and LED state indicator light are connected respectively with FPGA module；
Second jtag interface establishes both-way communication connection between second jtag interface and FPGA module；
50Mhz crystal oscillators and 2 frequency multiplication chips, the 50Mhz crystal oscillators are connected by 2 frequency multiplication chips with FPGA module；
Ethernet transceiver and the RJ45 interfaces with network transformer, the FPGA module is by ethernet transceiver and with network
The RJ45 interfaces of transformer are connected, described to be connected simultaneously with CPU module with outer net transceiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711480648.3A CN108155965A (en) | 2017-12-29 | 2017-12-29 | SDH transmits IEC61588 methods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711480648.3A CN108155965A (en) | 2017-12-29 | 2017-12-29 | SDH transmits IEC61588 methods |
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| Publication Number | Publication Date |
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| CN108155965A true CN108155965A (en) | 2018-06-12 |
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| CN201711480648.3A Pending CN108155965A (en) | 2017-12-29 | 2017-12-29 | SDH transmits IEC61588 methods |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109525353A (en) * | 2018-12-28 | 2019-03-26 | 浙江赛思电子科技有限公司 | SDH transmits the method that IEC61588 eliminates non-symmetric error |
| CN110673201A (en) * | 2019-09-12 | 2020-01-10 | 吉林大学 | Low-power-consumption wired seismograph based on single-chip FPGA and high-speed ad hoc network method thereof |
| CN114268400A (en) * | 2021-11-17 | 2022-04-01 | 北京航天科工世纪卫星科技有限公司 | PTP network time service system based on E1 optical fiber |
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| CN105376006A (en) * | 2015-12-02 | 2016-03-02 | 张大伟 | High-precision time service device based on electric power SDH transmission network and time service method thereof |
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Patent Citations (1)
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| CN105376006A (en) * | 2015-12-02 | 2016-03-02 | 张大伟 | High-precision time service device based on electric power SDH transmission network and time service method thereof |
Non-Patent Citations (2)
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| 曾志雄等: "PTP时间同步***中E1/Ethernet协议转换器的设计与实现", 《电信技术》 * |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109525353A (en) * | 2018-12-28 | 2019-03-26 | 浙江赛思电子科技有限公司 | SDH transmits the method that IEC61588 eliminates non-symmetric error |
| CN110673201A (en) * | 2019-09-12 | 2020-01-10 | 吉林大学 | Low-power-consumption wired seismograph based on single-chip FPGA and high-speed ad hoc network method thereof |
| CN110673201B (en) * | 2019-09-12 | 2022-03-08 | 吉林大学 | Low-power-consumption wired seismograph based on single-chip FPGA and high-speed ad hoc network method thereof |
| CN114268400A (en) * | 2021-11-17 | 2022-04-01 | 北京航天科工世纪卫星科技有限公司 | PTP network time service system based on E1 optical fiber |
| CN114268400B (en) * | 2021-11-17 | 2023-09-01 | 北京航天科工世纪卫星科技有限公司 | PTP network time service system based on E1 optical fiber |
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Application publication date: 20180612 |