CN117990999A

CN117990999A - ESD detection method and device and chip

Info

Publication number: CN117990999A
Application number: CN202211349080.2A
Authority: CN
Inventors: 汪瀚; 王富中
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2024-05-07

Abstract

The invention discloses an ESD detection method, an ESD detection device and a chip, wherein the method comprises the following steps: when the MIPI interface exits from the high-speed data transmission state, respectively acquiring the time of the level change of the clock path high-speed enabling signal and the data path high-speed enabling signal; and determining whether the ESD occurs according to the relative relation between the time when the clock path high-speed enabling signal and the data path high-speed enabling signal change in level. By the scheme of the invention, the generated ESD can be accurately detected in real time, and the normal operation of electronic products or chips or elements and the like is further ensured.

Description

ESD detection method and device and chip

Technical Field

The invention relates to the technical field of electrostatic discharge detection, in particular to an ESD detection method and device and a chip.

Background

Static electricity is an objectively existing natural phenomenon, and various modes are generated, such as contact, friction, induction between electric appliances and the like. Static electricity is characterized by long-time accumulation, high voltage, low electric quantity, small current and short acting time. Friction electrification and human static electricity are two major hazards in the electronic industry, and often cause unstable operation and even damage of electronic and electric products.

ESD (Electro-STATIC DISCHARGE, electrostatic discharge) causes damage and injury to electronic products, both sudden and potential. By bursty damage is meant that the device is severely damaged and has lost functionality, which damage can typically be found in quality testing during production. While potential damage refers to the fact that the device is partially damaged, the function is not lost yet, and the device cannot be found in the detection of the production process, but the product becomes unstable in use, and the product is good and bad, so that the quality of the product is more endangered. Of these two types of damage, the potential damage occupies a larger proportion, so how to more effectively detect whether ESD occurs or not has an extremely important role in quality and normal operation of electronic products or chips or elements and the like.

The display driver chip is a key chip of many electronic products, such as mobile terminals like mobile phones, and in the prior art, it is generally determined whether ESD occurs by periodically reading a flag register or a TE (TEARING EFFECT ) signal inside the chip. The detection method mainly has the following two problems: firstly, because the detection period is fixed, the chip cannot timely react when ESD occurs; and secondly, the condition that ESD occurs and the internal flag register or TE signal is not damaged can occur, so that omission is generated.

Disclosure of Invention

The embodiment of the invention provides an ESD detection method, an ESD detection device and a chip, which are used for solving the problems of untimely detection and missed detection existing in the existing ESD detection method.

In one aspect, an embodiment of the present invention provides an ESD detection method, including:

When the MIPI interface exits from the high-speed data transmission state, respectively acquiring the time of the level change of the clock path high-speed enabling signal and the data path high-speed enabling signal;

And determining whether the ESD occurs according to the relative relation between the time when the clock path high-speed enabling signal and the data path high-speed enabling signal change in level.

Optionally, the determining whether ESD occurs according to a relative relationship between the time when the clock path high-speed enable signal and the data path high-speed enable signal change in level includes:

Determining that ESD has occurred if the time at which the level of the clock path high-speed enable signal has changed is advanced or equivalent to the time at which the level of the data path high-speed enable signal has changed;

if the time when the level of the clock path high speed enable signal changes lags behind the time when the level of the data path high speed enable signal changes and the interval time between the two is less than the first time, it is determined that ESD has occurred.

In another aspect, an embodiment of the present invention further provides an ESD detection device, including: the sampling module is in signal connection with a data path and a clock path of the MIPI interface; the sampling module is used for respectively acquiring the time when the clock path high-speed enabling signal and the data path high-speed enabling signal change in level when the MIPI interface exits from the high-speed data transmission state, and outputting an ESD detection signal.

Optionally, the sampling module is configured to make the output ESD detection signal level jump when the time of the level change of the clock path high speed enable signal is advanced, equal to, or delayed and the interval time between the two is smaller than the first time.

Optionally, the ESD detection signal transitions from a low level to a high level or from a high level to a low level.

Optionally, the sampling module includes: a delay unit and a state latch unit;

the delay unit is used for inputting the data path high-speed enabling signal, delaying the data path high-speed enabling signal when the MIPI interface exits from a high-speed data transmission state, generating a delayed data path high-speed enabling signal, and the delay time is smaller than the first time;

the state latch unit is configured to sample and latch the delayed data path high-speed enable signal by using a transition edge of the clock path high-speed enable signal, and output the ESD detection signal.

Optionally, the state latch unit includes a first D flip-flop, an input terminal of the first D flip-flop inputs the delayed data path high-speed enable signal, a clock terminal of the first D flip-flop inputs the clock path high-speed enable signal, and an output terminal of the first D flip-flop outputs the ESD detection signal.

Optionally, the sampling module further includes: a pulse generating unit; the pulse generation unit is used for inputting the clock path high-speed enabling signal and the delayed data path high-speed enabling signal, and outputting a pulse signal to the state latch unit when detecting that the clock path high-speed enabling signal is advanced to jump in advance of the delayed data path high-speed enabling signal;

the state latch unit changes a level of the ESD detection signal when the pulse signal is received.

Optionally, the pulse generating unit comprises an or gate.

Optionally, the pulse generating unit includes an not gate and an and gate; the NOT gate inputs the clock path high-speed enabling signal; one input end of the AND gate is connected with the output end of the delay unit, and the other input end of the AND gate is connected with the output end of the NOT gate.

Optionally, the state latch unit includes a second D flip-flop, an input terminal of the second D flip-flop is connected to a high level or a low level, a clock terminal of the second D flip-flop is connected to an output terminal of the and gate, and an output terminal of the second D flip-flop outputs the ESD detection signal.

Optionally, the delay time is adjustable.

In another aspect, an embodiment of the present invention further provides a chip, where the chip includes the ESD detection device described above.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

According to the ESD detection method and device provided by the embodiment of the invention, by utilizing the characteristic that an MIPI (Mobile Industry Processor Interface ) interface module is subjected to ESD interference through pins, when the MIPI interface exits from a high-speed data transmission state, the time when the level of a clock path high-speed enabling signal changes and the time when the level of a data path high-speed enabling signal changes are acquired, and whether the ESD occurs is determined according to the relative relation between the time when the level of the clock path high-speed enabling signal and the time when the level of the data path high-speed enabling signal changes. By utilizing the scheme of the invention, whether the ESD occurs can be timely and accurately judged, and further, measures for dealing with the ESD can be timely made for corresponding electronic products or chips or elements and the like.

Drawings

FIG. 1 is a schematic diagram of the data and clock paths and corresponding high speed enable signals of an MIPI interface;

FIG. 2 is a schematic diagram of the relationship between the data path high speed enable signal and the clock path high speed enable signal of the MIPI interface of FIG. 1;

FIG. 3 is a flow chart of an ESD detection method provided by an embodiment of the present invention;

Fig. 4 is a schematic block diagram of an ESD detection device provided by an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a specific implementation of an ESD detection device according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a configuration in which the state latch unit in the ESD detection device shown in FIG. 5 is implemented by a D flip-flop;

FIG. 7 is a signal timing diagram of the MIPI interface in the ESD detection device shown in FIG. 6 when operating normally;

FIG. 8 is a signal timing diagram of the ESD detection device shown in FIG. 6 when ESD occurs;

FIG. 9 is a timing diagram of another signal when ESD occurs in the ESD detection device shown in FIG. 6;

FIG. 10 is a signal timing diagram of the ESD detection device shown in FIG. 6 when ESD occurs;

FIG. 11 is a schematic diagram of another implementation structure of an ESD detection device according to an embodiment of the present invention;

FIG. 12 is a signal timing diagram of the MIPI interface in the ESD detection device shown in FIG. 11 when operating normally;

FIG. 13 is a signal timing diagram of the ESD detection device shown in FIG. 11 when ESD occurs;

FIG. 14 is a timing diagram of another signal when ESD occurs in the ESD detection device shown in FIG. 11;

FIG. 15 is a signal timing diagram of the ESD detection device shown in FIG. 11 when ESD occurs;

fig. 16 is a schematic structural diagram of still another implementation of the ESD detection device according to the embodiment of the invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

The purpose of the MIPI interface is to standardize interfaces inside the handset, such as cameras, display interfaces, radio frequency/baseband interfaces, etc., thereby reducing the complexity of the handset design and increasing the design flexibility.

The MIPI interface module in the display driving chip consists of a clock path and a plurality of data paths, and is connected with the MIPI interface of the host through a chip pin (pad). When ESD occurs, ESD charge typically enters the display driver chip through the chip pins, and thus the MIPI interface module is affected by the ESD.

As shown in fig. 1, when the MIPI interface performs high-speed data transmission, the data path 11 and the clock path 12 generate corresponding high-speed enable signals, respectively. When the MIPI interface enters a high-speed data transmission state from a low-power consumption state, the high-speed enabling signal jumps from a first level to a second level; when the MIPI interface exits the high speed data transfer state and returns to the low power state, the high speed enable signal transitions from the second level to the first level, as shown in FIG. 2. According to the MIPI protocol, when the MIPI interface normally exits the high-speed data transmission state, the high-speed enable signal of the data path 11 should jump ahead of the high-speed enable signal of the clock path 12, and the minimum value of the advanced interval time T is the first time Tmin. The first time Tmin is a time specified in MIPI interface related standards MIPI SPEC V1-2 (Specification v1-2, specification version v 1-2). When ESD occurs, the data path 11 and the clock path 12 are affected, and random exit from the high-speed data transmission state occurs, where the interval time T may be less than the first time Tmin.

Therefore, the embodiment of the invention provides an ESD detection method and device, which utilize the characteristic that an MIPI interface module receives ESD interference through a pin to detect whether ESD occurs or not.

As shown in fig. 3, a flowchart of the ESD detection method of the present invention includes the following steps:

Step 301, when the MIPI interface exits the high-speed data transmission state, the time when the clock path high-speed enable signal changes in level and the time when the data path high-speed enable signal changes in level are acquired, respectively.

Step 302, determining whether ESD has occurred according to the relative relationship between the time when the clock path high-speed enable signal and the data path high-speed enable signal have changed in level.

Specifically, if the time at which the clock path high speed enable signal changes in level leads the time at which the data path high speed enable signal changes in level, or the time at which the clock path high speed enable signal changes in level is the same as the time at which the data path high speed enable signal changes in level, it is determined that ESD has occurred.

In addition, if the time at which the level of the clock path high-speed enable signal changes lags behind the time at which the level of the data path high-speed enable signal changes and the interval time between the two is less than the first time Tmin, it is determined that ESD has occurred.

It should be noted that, in practical application, the interval time T may be obtained by using a corresponding hardware circuit, for example, a sampling module may be used to obtain the interval time T and output a corresponding ESD detection signal. Determining whether or not ESD has occurred based on the ESD detection signal.

According to the ESD detection method provided by the embodiment of the invention, by utilizing the characteristic that the MIPI interface module is subjected to ESD interference through the pins, when the MIPI interface exits from a high-speed data transmission state, the time when the clock path high-speed enabling signal and the data path high-speed enabling signal change in level is respectively acquired, and whether the ESD occurs is determined according to the relative relation between the two times. If the time at which the level of the clock path high speed enable signal changes leads or is equivalent to the time at which the level of the data path high speed enable signal changes, it is determined that ESD has occurred. In the case where the time of the level change of the clock path high speed enable signal lags behind the time of the level change of the data path high speed enable signal, it is necessary to further detect the interval time between both, and in the case where the interval time is smaller than the first time, it is determined that ESD has occurred.

By utilizing the ESD detection method provided by the embodiment of the invention, whether the ESD occurs can be timely and accurately judged, and further measures against the ESD can be timely made for corresponding electronic products or chips or elements and the like.

Correspondingly, the embodiment of the invention also provides an ESD detection device, as shown in fig. 4, which is a functional block diagram of the device.

The ESD detection device includes: and the sampling module 40 is in signal connection with the data path 11 and the clock path 12 of the MIPI interface, and the sampling module 40 is used for respectively acquiring the time when the clock path high-speed enabling signal and the data path high-speed enabling signal change in level and outputting an ESD detection signal when the MIPI interface exits from the high-speed data transmission state. Specifically, in the case where the time at which the level of the clock path high-speed enable signal changes is advanced, equalized, or delayed, and the interval time T between the two is smaller than the first time Tmin, the output ESD detection signal is caused to jump in level, that is, the ESD detection signal level is changed. This condition indicates an abnormal MIPI interface state due to ESD.

The ESD detection signal generates a level jump from a low level to a high level or from a high level to a low level.

In practical applications, the sampling module 40 may be implemented in a variety of ways, which are described in detail below by way of example.

As shown in fig. 5, in one non-limiting embodiment, the sampling module 40 includes: a delay unit 41, and a state latch unit 43. Wherein:

The delay unit 41 is configured to input the data path high-speed enable signal, delay the data path high-speed enable signal when the MIPI interface exits from the high-speed data transmission state, generate a delayed data path high-speed enable signal, and delay time Tdly is less than the first time Tmin;

the state latch unit 43 is configured to sample and latch the delayed data path high-speed enable signal by using a transition edge of the clock path high-speed enable signal, and output an ESD detection signal.

In a specific application, as shown in fig. 6, the state latch unit 43 may be implemented by a first D flip-flop, where an input terminal of the first D flip-flop inputs the delayed data path high-speed enable signal, a clock terminal of the first D flip-flop inputs the clock path high-speed enable signal, and an output terminal of the first D flip-flop outputs the ESD detection signal.

In the ESD detection device shown in fig. 6, when the MIPI interface is operating normally, the signal level output from the state latch unit 43 does not change as shown in fig. 7.

Based on the embodiment shown in fig. 6, the data path 11 and the clock path 12 may randomly exit the high-speed data transmission state, and three abnormal situations may occur as shown in fig. 8 or fig. 9 or fig. 10. Wherein:

the abnormal situation shown in fig. 8 is that the clock path high-speed enable signal jumps ahead of the data path high-speed enable signal;

the abnormal situation shown in fig. 9 is that the clock path high-speed enable signal and the data path high-speed enable signal are hopped simultaneously;

The abnormal situation shown in fig. 10 is that the data path high-speed enable signal transitions in advance of the clock path high-speed enable signal, but the time interval between the two transitions is smaller than the first time Tmin.

In another non-limiting embodiment, as shown in FIG. 11, the sampling module 40 includes: a delay unit 41, a pulse generation unit 42, and a state latch unit 43. Wherein:

The pulse generating unit 42 is configured to input the clock path high-speed enable signal and the delayed data path high-speed enable signal, and output a pulse signal to the state latch unit 43 when detecting that the clock path high-speed enable signal is advanced by the delayed data path high-speed enable signal; of course, if the clock path high speed enable signal is not detected to be hopped in advance of the delayed data path high speed enable signal, the output signal level of the pulse generating unit 42 remains unchanged.

The state latch unit 43 is configured to output the ESD detection signal and change the level of the ESD detection signal, that is, the ESD detection signal undergoes a level transition when the pulse signal is received.

It should be noted that, in the above embodiments, the delay time Tdly of the delay unit 41 for the data path high speed enable signal is adjustable, but the delay time Tdly should be ensured to be smaller than the first time Tmin.

The operation principle of the ESD detection device according to the present invention will be described below by taking the embodiment shown in fig. 11 as an example.

In the ESD detection device shown in fig. 11, when the MIPI interface is operating normally, as shown in fig. 12, the signal levels output from the pulse generating unit 42 and the state latch unit 43 do not change.

Based on the embodiment shown in fig. 11, when ESD occurs, the data path 11 and the clock path 12 may randomly exit the high-speed data transmission state, and three abnormal situations as shown in fig. 13 or 14 or 15 may occur. Wherein:

the abnormal situation shown in fig. 13 is that the clock path high-speed enable signal jumps ahead of the data path high-speed enable signal;

The abnormal situation shown in fig. 14 is that the clock path high-speed enable signal and the data path high-speed enable signal are hopped at the same time;

The abnormal situation shown in fig. 15 is that the data path high speed enable signal transitions in advance of the clock path high speed enable signal, but the time interval between the two transitions is smaller than the first time Tmin.

In either case, the clock path high-speed enable signal transitions in advance of the data path enable signal delayed by the delay unit 41, and accordingly, the pulse generating unit 42 outputs a pulse signal when detecting that the clock path high-speed enable signal transitions in advance of the delayed data path high-speed enable signal. Upon receiving the pulse signal, the state latch unit 43 changes the level of the output ESD detection signal, and causes the ESD detection signal to transition from low to high or from high to low, thereby latching the current abnormal state.

Fig. 16 is a schematic structural diagram of another implementation of the ESD detection device according to the embodiment of the invention.

In comparison with the embodiment shown in fig. 11, in this embodiment, the pulse generating unit 42 includes an not gate and an and gate; the NOT gate inputs the clock path high-speed enabling signal; one input of the and gate is connected to the output of the delay unit 41, and the other input of the and gate is connected to the output of the not gate.

In addition, in this embodiment, the state latch unit is implemented by a second D flip-flop, an input terminal of the second D flip-flop is connected to a high level, a clock terminal of the second D flip-flop is connected to an output terminal of the and gate, and an output terminal of the second D flip-flop outputs the ESD detection signal.

In another non-limiting embodiment, the pulse generating unit 42 may be replaced with an equivalent logic structure using OR gates. Accordingly, the input terminal of the second D flip-flop may also be grounded, and when ESD occurs, the ESD detection signal jumps from high level to low level.

It should be noted that, in practical applications, the specific structures of the modules and units are not limited to the examples, and other devices may be used to implement the same or similar logic, for example, the state latch unit 43 may be replaced by other flip-flops to implement the same logic function.

According to the ESD detection device provided by the embodiment of the invention, by utilizing the characteristic that the MIPI interface module is subjected to ESD interference through the pins, when the MIPI interface exits from a high-speed data transmission state, the time of level change of a clock path high-speed enabling signal and a data path high-speed enabling signal of the MIPI interface is respectively obtained, and an ESD detection signal is output. Further, when the time of the level change of the clock path high-speed enable signal is advanced, equal to or delayed, and the interval time T between the two is smaller than the first time Tmin, the output ESD detection signal is subjected to level jump, namely, the occurrence of ESD is determined. By utilizing the scheme of the invention, whether the ESD occurs can be timely and accurately judged, and further, measures for dealing with the ESD can be timely made for corresponding electronic products or chips or elements and the like.

Correspondingly, the embodiment of the invention also provides a chip, which comprises the ESD detection device of any embodiment.

In a specific implementation, regarding each apparatus and each module/unit included in each product described in the above embodiments, it may be a software module/unit, or a hardware module/unit, or may be a software module/unit partially, or a hardware module/unit partially.

For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least some modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) part of modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented in hardware such as a circuit, where different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least some modules/units may be implemented in a software program, where the software program runs on a processor integrated within the terminal, and the remaining (if any) some modules/units may be implemented in hardware such as a circuit.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present application limited, and no limitation on the embodiments of the present application should be construed.

The "connection" in the embodiment of the present application refers to various connection manners such as direct connection or indirect connection, so as to implement communication between devices, which is not limited in the embodiment of the present application.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of ESD detection, the method comprising:

2. The method of claim 1, wherein determining whether ESD has occurred based on a relative relationship of times at which the clock path high speed enable signal and the data path high speed enable signal have changed in level comprises:

3. An ESD detection device, the device comprising: the sampling module is in signal connection with a data path and a clock path of the MIPI interface;

The sampling module is used for respectively acquiring the time when the clock path high-speed enabling signal and the data path high-speed enabling signal change in level when the MIPI interface exits from the high-speed data transmission state, and outputting an ESD detection signal.

4. The apparatus of claim 3, wherein the device comprises a plurality of sensors,

The sampling module is used for enabling the output ESD detection signal to generate level jump under the condition that the time of the level change of the clock path high-speed enabling signal is advanced, equal or lagging the time of the level change of the data path high-speed enabling signal and the interval time of the clock path high-speed enabling signal and the data path high-speed enabling signal is smaller than the first time.

5. The apparatus of claim 4, wherein the ESD detection signal transitions from low to high or from high to low.

6. The apparatus of claim 4, wherein the sampling module comprises: a delay unit and a state latch unit;

7. The apparatus of claim 6, wherein the state latch unit comprises a first D flip-flop having an input terminal for inputting the delayed data path high speed enable signal, a clock terminal for inputting the clock path high speed enable signal, and an output terminal for outputting the ESD detection signal.

8. The apparatus of claim 6, wherein the sampling module further comprises: a pulse generating unit;

the pulse generation unit is used for inputting the clock path high-speed enabling signal and the delayed data path high-speed enabling signal, and outputting a pulse signal to the state latch unit when detecting that the clock path high-speed enabling signal is advanced to jump in advance of the delayed data path high-speed enabling signal;

9. The apparatus of claim 8, wherein the pulse generating unit comprises an or gate.

10. The apparatus of claim 8, wherein the pulse generating unit comprises an not gate and an and gate; the NOT gate inputs the clock path high-speed enabling signal; one input end of the AND gate is connected with the output end of the delay unit, and the other input end of the AND gate is connected with the output end of the NOT gate.

11. The apparatus of claim 10, wherein the state latch unit comprises a second D flip-flop having an input terminal connected to a high level or a low level, a clock terminal connected to an output terminal of the and gate, and an output terminal of the second D flip-flop outputting the ESD detection signal.

12. The apparatus according to any one of claims 6 to 11, wherein the delay time is adjustable.

13. A chip comprising an ESD detection device as claimed in any one of claims 3 to 12.