CN116381471B - Scan test circuit, method and chip - Google Patents
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- CN116381471B CN116381471B CN202310655330.3A CN202310655330A CN116381471B CN 116381471 B CN116381471 B CN 116381471B CN 202310655330 A CN202310655330 A CN 202310655330A CN 116381471 B CN116381471 B CN 116381471B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318597—JTAG or boundary scan test of memory devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the application provides a scan test circuit, a scan test method and a scan test chip. The scanning test circuit comprises a circuit to be tested, a monitoring module and a control module, wherein the first signal input end of the circuit to be tested, which is necessary when scanning test is carried out, is multiplexed, and the first signal input end is connected with the test signal input end of the monitoring module, so that the test signal can be input into the monitoring module at the same time when being input into the circuit to be tested without adding an additional input pin, and the cost of scanning test and the complexity of design are reduced.
Description
Technical Field
The embodiment of the application relates to the field of chip scanning test, in particular to a scanning test circuit, a scanning test method and a chip.
Background
The scan test of the chip is to insert a scan chain into a register, solve an error model established according to physical defects, and generate a structural test vector to complete the test of the digital logic of the chip. Scan testing is typically done based on the joint test group (Joint Test Action Group, JTAG) protocol or a communication protocol.
In the case of performing the scan test, an input/output pin for the scan test needs to be added, which increases the cost of the scan test and the complexity of the scan test design.
Disclosure of Invention
In view of the above problems, embodiments of the present application provide a scan test circuit, a method, and a chip, which complete the configuration of the chip required for performing the scan test by multiplexing signal input/output pins necessary for the scan test, thereby reducing additional input/output pins, and reducing the cost of the scan test and the complexity of the scan test design.
According to an aspect of an embodiment of the present application, there is provided a scan test circuit, the circuit including:
the circuit to be tested, the monitoring module and the control module; the monitoring module is provided with an enabling signal input end and a test signal input end; the test signal input end is connected with the first signal input end of the circuit to be tested; the output end of the monitoring module is connected with the input end of the control module; the first output end of the control module is connected with the second signal input end of the circuit to be tested, and the second output end of the control module is connected with the output end of the circuit to be tested; the monitoring module is used for receiving the enabling signal through the enabling signal input end, receiving the test signal through the test signal input end, adjusting the scanning test state according to the enabling signal, and outputting the scanning test state and the test signal to the control module; the control module is used for generating a test enabling signal when the signal sequence of the test signal is judged to be effective according to the scanning test state, and sending the test enabling signal to the circuit to be tested; the circuit to be tested is used for completing the scanning test task according to the test enabling signal.
In some embodiments, the monitoring module includes: the first receiving unit is used for receiving the enabling signal through the enabling signal input end and receiving the test signal through the test signal input end; a monitoring unit for monitoring a level electromotive force state of the enable signal; the state unit is used for adjusting the scanning test state according to the level electromotive force state of the enabling signal; and the sending unit is used for outputting the scanning test state and the test signal to the control module.
In some embodiments, the monitoring module further comprises: a clock signal input for receiving a clock signal; the clock signal is used for triggering the monitoring module to monitor the level electromotive force state of the enabling signal so as to adjust the scanning test state according to the level electromotive force state.
In some embodiments, the control module includes: the second receiving unit is used for receiving the scanning test state and the test signal; the judging unit is used for acquiring a signal sequence of the test signal according to the test signal and judging the validity of the signal sequence of the test signal according to the scanning test state; and the enabling unit is used for generating a test enabling signal when the validity is valid and outputting the test enabling signal to the circuit to be tested.
In some embodiments, the determining unit is specifically configured to: counting the signal sequence of the test signal according to the scanning test state to obtain a count value; obtaining a sign signal value according to the count value, and judging the validity of a signal sequence of the test signal according to the sign signal value; the control module further includes: and the registering unit is used for registering the signal sequence of the test signal when the validity of the signal sequence of the test signal is valid.
According to a second aspect of the embodiments of the present application, there is provided a scan test method applied to the circuit according to any one of the embodiments of the first aspect of the embodiments of the present application, the scan test method includes:
acquiring an enabling signal and a test signal; adjusting a scanning test state according to the level dynamic state of the enabling signal; and generating a test enabling signal when the signal sequence of the test signal is judged to be effective according to the scanning test state, and scanning and testing the circuit to be tested according to the test enabling signal.
In some embodiments, adjusting the scan test state according to the level-motive state of the enable signal includes: monitoring the level electromotive state of the enable signal when the clock signal is received; and adjusting the scanning test state according to the electric translation potential state.
In some embodiments, adjusting the scan test state according to the level-motive state of the enable signal includes: when the level of the enabling signal is changed from low level to high level, the level dynamic state is a rising state, and the scanning test state is adjusted to be a starting state; when the level of the enabling signal keeps the high level unchanged, the level dynamic state is static and keeps the high level unchanged, and the scanning test state is adjusted to be a counting state; when the level of the enabling signal is changed from high level to low level, the electric potential state is a falling state, and the scanning test state is adjusted to be an updating state; when the level of the enabling signal keeps the low level unchanged, the level dynamic state is static and keeps the low level, and the scanning test state is adjusted to be the reset state.
In some embodiments, determining the validity of the signal sequence of the test signal based on the scan test state includes: when the scanning test state is a counting state, counting the number of bits of a signal sequence of the test signal to obtain a counting value, and obtaining a marking signal value according to the counting value; when the scanning test state is in the updating state, judging the validity of the signal sequence of the test signal according to the sign signal value, and updating the signal sequence of the test signal into a control module of the scanning test circuit when the validity is valid; and when the scanning test state is in the reset state, resetting the count value of the signal sequence of the test signal and the sign signal value.
In some embodiments, the flag signal value comprises: a flag compare signal value and a flag overflow signal value; obtaining a sign signal value according to the count value, including: comparing the count value with a preset count value; when the count value is smaller than the preset count value, setting the flag comparison signal value to 0 and setting the flag overflow signal value to 0; when the count value is equal to the preset count value, setting the flag comparison signal value to 1 and setting the flag overflow signal value to 0; when the count value is greater than the preset count value, the flag comparison signal value is set to 1, and the flag overflow signal value is set to 1.
According to a third aspect of the embodiments of the present application, there is provided a scan test chip, including a scan test circuit according to any one of the embodiments of the first aspect of the present application.
According to the scan test circuit, the scan test method and the scan test chip, the first signal input end of the circuit to be tested is connected with the test signal input end of the monitoring module, the first signal input end of the circuit to be tested is multiplexed to input the test signal to the monitoring module, the test signal is input into the control module through the monitoring module, the control module processes the signal sequence of the test signal and outputs the test enabling signal to the circuit to be tested, the circuit to be tested executes the scan test task according to the signal sequence of the test signal, the configuration required by the circuit to be tested in the scan test is completed, the input and output pins required by the circuit to be tested in the scan test are reduced, the cost of the scan test is reduced, and the complexity of the scan test control design is greatly reduced.
The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and may be implemented according to the content of the specification, so that the technical means of the embodiments of the present application can be more clearly understood, and the following specific embodiments of the present application are given for clarity and understanding.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a scan test circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a monitoring module of a scan test circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a control module of a scan test circuit according to an embodiment of the present application;
fig. 4 is a flowchart of a scan test method according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The terms "comprising" and "having" and any variations thereof in the description and claims of the application and in the description of the drawings are intended to cover and not exclude other matters. The word "a" or "an" does not exclude the presence of a plurality.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Furthermore, the terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order, and may be used to improve one or more of these features either explicitly or implicitly.
In the description of the present application, unless otherwise indicated, the meaning of "plurality" means two or more (including two), and similarly, "plural sets" means two or more (including two).
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may refer to not only physical connection but also electrical connection or signal connection, for example, direct connection, i.e. physical connection, or indirect connection via at least one element therebetween, as long as electrical communication is achieved, and also internal communication between two elements; signal connection may refer to signal connection through a medium such as radio waves, in addition to signal connection through a circuit. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
The scheme of the application is further described by the specific embodiments with reference to the accompanying drawings:
fig. 1 is a schematic structural diagram of a scan test circuit according to an embodiment of the present application, as shown in fig. 1, the scan test circuit of the present embodiment includes a circuit to be tested 1110, a monitoring module 1120 and a control module 1130; the monitor module 1110 has an enable signal input and a test signal input; the test signal input end is connected with the first signal input end of the circuit to be tested; the output end of the monitoring module is connected with the input end of the control module; the first output end of the control module is connected with the second signal input end of the circuit to be tested, and the second output end of the control module is connected with the output end of the circuit to be tested.
The monitoring module 1120 receives the enable signal through the enable signal input terminal, receives the test signal through the test signal input terminal, adjusts the scan test state according to the enable signal, and outputs the scan test state and the test signal to the control module 1130.
The monitoring module monitors the level electromotive force of the enabling signal, so that the level electromotive force state of the enabling signal is obtained according to the monitored level electromotive force, and the scanning test state of the scanning test circuit is adjusted according to the level electromotive force state.
Specifically, fig. 2 is a schematic diagram of a monitoring module of a scan test circuit according to an embodiment of the present application, as shown in fig. 2, the monitoring module 1120 may include a first receiving unit 1121, a monitoring unit 1122, a status unit 1123, and a sending unit 1124. A first receiving unit 1121 for receiving an enable signal through an enable signal input terminal and receiving a test signal through a test signal input terminal; a monitoring unit 1122 for monitoring a level electromotive force state of the enable signal; a state unit 1123 for adjusting a scan test state according to a level electromotive state of the enable signal; and a transmitting unit 1124 for outputting the scan test status and the test signal to the control module 1130.
The level-electromotive state of the enable signal includes: the level of the enable signal changes from low to high, the level of the enable signal remains high, the level of the enable signal changes from high to low, and the level of the enable signal remains low.
In this embodiment, when the level electromotive force state is that the level of the enable signal changes from low level to high level, the corresponding scan test state is a start state; when the level electromotive force state is that the level of the enabling signal keeps high level unchanged, the corresponding scanning test state is a counting state; when the level electromotive force state is that the level of the enabling signal is changed from high level to low level, the corresponding scanning test state is an updating state; when the level electromotive force state is that the level of the enabling signal keeps the low level unchanged, the corresponding scanning test state is a reset state.
That is, the state unit 1123 can correspondingly adjust the scan test state according to the state of the electric potential of the enable signal, and output the scan test state to the control module.
The control module 1130 is configured to generate a test enable signal and output the test enable signal to the circuit to be tested when the signal sequence of the test signal is determined to be valid according to the scan test state. In an example, fig. 3 is a schematic diagram of a control module of a scan test circuit according to an embodiment of the present application, as shown in fig. 3, the control module 1130 may include a second receiving unit 1131 and a determining unit 1132; the second receiving unit 1131 is configured to receive the scan test state and the test signal; a determining unit 1132, configured to obtain a signal sequence of the test signal according to the test signal, and determine validity of the signal sequence of the test signal according to the scan test state; when the validity is valid, the test enable unit generation 1133 generates a test enable signal and outputs the test enable signal to the circuit to be tested.
In this embodiment, when determining whether the signal sequence of the test signal is valid, the determining unit 1132 may specifically count the signal sequence of the test signal according to the scan test state to obtain a count value; and obtaining a sign signal value according to the count value, and judging the validity of the signal sequence of the test signal according to the sign signal value. Further, the control module 1130 may further include a register unit 1134, configured to register the signal sequence of the test signal when the validity of the signal sequence of the test signal is valid, so as to facilitate transmission to a subsequent circuit.
It should be noted that, when the validity of the signal sequence of the test signal is valid and the signal sequence of the test signal is registered in the register unit, the test enabling unit generates the test enabling signal and outputs the test enabling signal to the circuit to be tested 1110 through the first output end, so that the circuit to be tested completes the scan test task according to the test enabling signal.
Further, in practical applications, the monitoring module 1120 may further include a clock signal input terminal for receiving a clock signal; the clock signal is used for triggering the monitoring module to monitor the level dynamic potential state of the enabling signal so as to adjust the scanning test state according to the level dynamic potential state. Therefore, the monitoring module can be prevented from still monitoring the enabling signal when the circuit to be tested does not need to be subjected to scanning test, and unnecessary resource waste is avoided.
The circuit to be tested is used for receiving the test signal through the first signal input end, receiving the test enabling signal through the second signal input end, completing the scanning test task according to the test enabling signal, and outputting the test result through the output end.
The scan test circuit provided in this embodiment multiplexes the first signal input terminal necessary for the scan test of the circuit 1110 to be tested, where the first signal input terminal is connected with the test signal input terminal of the monitoring module, so that the test signal can be input into the circuit 1110 to be tested and the monitoring module 1120 at the same time, without requiring an additional input pin, thereby reducing the cost of the scan test and the complexity of the scan test control design.
Fig. 4 is a flowchart of a scan test method according to an embodiment of the present application. As shown in fig. 4, the scan test method provided by the embodiment of the present application can be applied to the scan test circuit shown in fig. 1, and specifically, the method includes the following steps S2101 to S2103:
s2101, acquiring an enabling signal and a test signal.
S2102, adjusting the scanning test state according to the level dynamic state of the enabling signal.
Specifically, after the scan test circuit acquires the enable signal, the scan test circuit starts to monitor the electro-translational potential state of the enable signal, and adjusts the scan test state according to the level-dynamic potential state of the enable signal.
Wherein, the level dynamic state of the enabling signal includes: the level of the enable signal changes from low to high, the level of the enable signal remains high, the level of the enable signal changes from high to low, and the level of the enable signal remains low.
In one example, when the level electromotive force state is that the level of the enable signal changes from low level to high level, the corresponding scan test state is a start state; when the level electromotive force state is that the level of the enabling signal keeps high level unchanged, the corresponding scanning test state is a counting state; when the level electromotive force state is that the level of the enabling signal is changed from high level to low level, the corresponding scanning test state is an updating state; when the level electromotive force state is that the level of the enabling signal keeps the low level unchanged, the corresponding scanning test state is a reset state.
Optionally, in order to avoid unnecessary resource waste caused by the scan test circuit monitoring the enable signal for a long time, the scan test circuit may further receive a clock signal, and only after the scan test circuit acquires the clock signal, the scan test circuit starts to monitor the electric translation potential state of the enable signal, and adjusts the scan test state according to the electric translation potential state.
S2103, when the signal sequence of the test signal is judged to be effective according to the scanning test state, a test enabling signal is generated, and scanning test is carried out on the circuit to be tested according to the test enabling signal.
After the scanning test state is adjusted, the scanning test circuit processes the signal sequence of the test signal according to the scanning test state so as to judge the effectiveness of the test signal sequence. Specifically, when the scanning test state is the counting state, counting the number of bits of the signal sequence of the test signal to obtain a count value, and obtaining a sign signal value according to the count value; and when the scanning test state is in the updating state, judging the validity of the signal sequence of the test signal according to the sign signal value, and updating the signal sequence of the test signal into a control module of the scanning test circuit when the validity is valid.
Wherein the flag signal value comprises a flag comparison signal value and a flag overflow signal value; obtaining a sign signal value according to the count value, wherein the sign signal value comprises comparing the count value with a preset count value, and setting the sign comparison signal value and the sign overflow signal value to be 0 when the count value is smaller than the preset count value; when the count value is equal to the preset count value, setting the flag comparison signal value to be 1, and setting the flag overflow signal value to be 0; when the count value is greater than the preset count value, the set flag comparison signal value remains at 1, and the set flag overflow signal is at 1.
After the marking signal value is obtained, processing the signal sequence of the test signal according to the marking signal value; when the flag comparison signal value is 1 and the flag overflow signal value is 0, the validity of the signal sequence of the test signal is determined to be valid, and the value of the signal sequence of the test signal is registered in the scan test circuit.
When the validity of the signal sequence of the test signal is valid and the value of the signal sequence of the test signal is registered in the scan test circuit, the scan test circuit generates a test enabling signal and outputs the test enabling signal to the circuit to be tested, and the circuit to be tested completes the scan test task according to the test enabling signal.
In the embodiment of the application, a scanning test circuit obtains an enabling signal and a test signal; adjusting a scanning test state according to the level dynamic state of the enabling signal; and generating a test enabling signal when the signal sequence of the test signal is judged to be effective according to the scanning test state, and carrying out scanning test according to the test enabling signal. Thus, the cost of the scan test and the complexity of the scan test design are reduced without adding additional input/output pins.
The embodiment of the application also provides a scan test chip, which comprises the scan test circuit provided by the embodiment shown in fig. 1.
Those skilled in the art will appreciate that while some embodiments herein include certain features that are included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (11)
1. A scan test circuit, comprising:
the circuit to be tested, the monitoring module and the control module;
the monitoring module is provided with an enabling signal input end and a test signal input end; the test signal input end is connected with the first signal input end of the circuit to be tested; the output end of the monitoring module is connected with the input end of the control module; the first output end of the control module is connected with the second signal input end of the circuit to be tested, and the second output end of the control module is connected with the output end of the circuit to be tested;
the monitoring module is used for receiving an enabling signal through the enabling signal input end, receiving a test signal through the test signal input end, adjusting a scanning test state according to the enabling signal, and outputting the scanning test state and the test signal to the control module;
the control module is used for counting the number of bits of the signal sequence of the test signal to obtain a count value when the scanning test state is a counting state, and obtaining a sign signal value according to the count value;
the control module is further used for judging the validity of the signal sequence of the test signal according to the sign signal value when the scanning test state is in an updating state, generating a test enabling signal when the validity is valid, and updating the test enabling signal to the circuit to be tested;
the circuit to be tested is used for completing a scanning test task according to the test enabling signal.
2. The circuit of claim 1, wherein the monitoring module comprises: the first receiving unit is used for receiving the enabling signal through the enabling signal input end and receiving the test signal through the test signal input end;
a monitoring unit for monitoring the level electromotive force state of the enable signal;
the state unit is used for adjusting the scanning test state according to the level dynamic state of the enabling signal;
and the sending unit is used for outputting the scanning test state and the test signal to the control module.
3. The circuit of claim 2, wherein the monitoring module further comprises: a clock signal input for receiving a clock signal; the clock signal is used for triggering the monitoring module to monitor the level dynamic state of the enabling signal so as to adjust the scanning test state according to the level dynamic state.
4. The circuit of claim 1, wherein the control module comprises:
the second receiving unit is used for receiving the scanning test state and the test signal;
the judging unit is used for counting the number of bits of the signal sequence of the test signal to obtain a count value when the scanning test state is a counting state, and obtaining a sign signal value according to the count value; when the scanning test state is in an updating state, judging the validity of a signal sequence of the test signal according to the sign signal value;
and the test enabling unit is used for generating the test enabling signal when the validity is valid and outputting the test enabling signal to the circuit to be tested.
5. The circuit of claim 4, wherein the control module further comprises: and the registering unit is used for registering the signal sequence of the test signal when the validity of the signal sequence of the test signal is valid.
6. A scan test method for use in the circuit of any one of claims 1 to 5, the scan test method comprising:
acquiring an enabling signal and a test signal;
adjusting a scanning test state according to the level dynamic state of the enabling signal;
when the scanning test state is a counting state, counting the number of bits of a signal sequence of the test signal to obtain a count value, and obtaining a sign signal value according to the count value; when the scanning test state is in the updating state, judging the validity of the signal sequence of the test signal according to the sign signal value, generating a test enabling signal when the validity is valid, updating the test enabling signal to the circuit to be tested, and scanning the circuit to be tested according to the test enabling signal.
7. The method of claim 6, wherein adjusting the scan test state according to the level-motive state of the enable signal comprises:
monitoring the level electromotive state of the enabling signal when the clock signal is received;
and adjusting the scanning test state according to the level electromotive force state.
8. The method of claim 6, wherein said adjusting said scan test state according to a level-motive state of said enable signal comprises:
when the level of the enabling signal is changed from low level to high level, the level dynamic state is a rising state, and the scanning test state is adjusted to be a starting state;
when the level of the enabling signal keeps the high level unchanged, the level dynamic state is static and keeps the high level unchanged, and the scanning test state is adjusted to be a counting state;
when the level of the enabling signal is changed from high level to low level, the level dynamic state is a falling state, and the scanning test state is adjusted to be an updating state;
when the level of the enabling signal keeps low level unchanged, the level dynamic state is static and keeps low, and the scanning test state is adjusted to be a reset state.
9. The method of claim 8, wherein said determining the validity of the signal sequence of the test signal based on the scan test status comprises:
and resetting the count value of the signal sequence of the test signal and the sign signal value when the scanning test state is in the reset state.
10. The method of claim 9, wherein the flag signal value comprises: a flag compare signal value and a flag overflow signal value;
the obtaining a sign signal value according to the count value comprises the following steps:
comparing the count value with a preset count value;
when the count value is smaller than the preset count value, setting the flag comparison signal value to 0 and setting the flag overflow signal value to 0;
when the count value is equal to the preset count value, setting the flag comparison signal value to 1 and setting the flag overflow signal value to 0;
and when the count value is larger than the preset count value, setting the sign comparison signal value to be 1, and setting the sign overflow signal value to be 1.
11. A scan test chip comprising a scan test circuit according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310655330.3A CN116381471B (en) | 2023-06-05 | 2023-06-05 | Scan test circuit, method and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310655330.3A CN116381471B (en) | 2023-06-05 | 2023-06-05 | Scan test circuit, method and chip |
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