CN117976706A - 高电子迁移率晶体管 - Google Patents

高电子迁移率晶体管 Download PDF

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CN117976706A
CN117976706A CN202410020383.2A CN202410020383A CN117976706A CN 117976706 A CN117976706 A CN 117976706A CN 202410020383 A CN202410020383 A CN 202410020383A CN 117976706 A CN117976706 A CN 117976706A
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layer
gate electrode
hemt
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barrier layer
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刘安淇
林俊贤
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管，其主要包含一缓冲层设于一基底上；一阻障层设于该缓冲层上；一栅极电极设于该阻障层上；一第一保护层设于该栅极电极两侧；以及一P型半导体层设于该栅极电极以及该阻障层之间，其中该P型半导体层接触该第一保护层侧壁的一角落包含一第一曲面。

Description

高电子迁移率晶体管
本申请是中国发明专利申请(申请号：201910874778.8，申请日：2019年09月17日，发明名称：高电子迁移率晶体管)的分案申请。
技术领域
本发明涉及一种高电子迁移率晶体管。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽带隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通讯元件等应用的元件的制作。
发明内容
本发明一实施例公开一种高电子迁移率晶体管，其主要包含一缓冲层设于一基底上；一阻障层设于该缓冲层上；一栅极电极设于该阻障层上；一第一保护层设于该栅极电极两侧；以及一P型半导体层设于该栅极电极以及该阻障层之间，其中该P型半导体层接触该第一保护层侧壁的一角落包含一第一曲面。
本发明另一实施例公开一种高电子迁移率晶体管(high electron mobilitytransistor,HEMT)，其主要包含：一缓冲层设于一基底上；一阻障层设于该缓冲层上；一栅极电极设于该阻障层上；一第一保护层设于该栅极电极两侧；以及一P型半导体层设于该栅极电极以及该阻障层之间，其中设于该第一保护层正上方的该P型半导体层的一角落包含一曲面。
附图说明
图1至图4为本发明一实施例制作一高电子迁移率晶体管的方法示意图；
图5为本发明一实施例的一高电子迁移率晶体管的结构示意图。
主要元件符号说明
12 基底 14 缓冲层
16 阻障层 18 保护层
20 保护层 22 保护层
24 凹槽 26 角落
28 曲面 30 倾斜面
32 P型半导体层 34 栅极材料层
36 栅极结构 38 栅极电极
40 场极板 42 角落
44 曲面 46 源极电极
48 漏极电极 50 曲面
具体实施方式
请参照图1至图4，图1至图4为本发明一实施例制作一高电子迁移率晶体管的方法示意图。如图1所示，首先提供一基底12，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
然后于基底12表面形成一缓冲层14。在一实施例中，缓冲层14包含III-V族半导体例如氮化镓，其厚度可介于0.5微米至10微米之间。在一实施例中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层14。
接着形成一阻障层16于缓冲层14表面。在本实施例中阻障层16较佳包含III-V族半导体例如氮化铝镓(AlxGa1-xN)，其中0<x<1，且阻障层16较佳包含一由外延成长制作工艺所形成的外延层。如同上述形成缓冲层14的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层14上形成阻障层16。
随后形成一保护层18，例如一保护层20以及一保护层22于阻障层16表面。在本实施例中，保护层20与保护层22较佳包含不同材料，其中保护层20较佳选自由氮化铝、氧化铝、碳化硅以及氮氧化硅所构成的群组而保护层22较佳包含氮化硅。需注意的是，本实施例形成于阻障层16表面的保护层18虽以双层结构为例，但不局限于此，依据本发明其他实施例又可仅形成由单层结构所构成的保护层18于阻障层16表面，其中单层结构可由上述的保护层20或保护层22所构成，这些变化型均属本发明所涵盖的范围。
然后如图2所示，进行一图案转移制作工艺，例如可先形成一图案化掩模(图未示)如图案化光致抗蚀剂于保护层18表面，再进行至少一道蚀刻制作工艺去除部分保护层22及部分保护层20以形成一凹槽24暴露出阻障层16表面。更具体而言，本实施例较佳依序进行一干蚀刻制作工艺以及一湿蚀刻制作工艺来去除部分保护层18形成凹槽24，其中干蚀刻制作工艺可包含例如四氟化碳(CF4)、三氟甲烷(CHF3)以及/或氦气等蚀刻气体而湿蚀刻制作工艺则可包含例如稀释氢氟酸。在本实施例中，四氟化碳的流量较佳介于30～100每分钟标准毫升(standard cubic centimeter per minute,sccm)，三氟甲烷的流量较佳介于30～100每分钟标准毫升，氦气的流量较佳介于160～180每分钟标准毫升，而稀释氢氟酸的稀释比例较佳约100:1。
需注意的是，本实施例利用上述干蚀刻与湿蚀刻的组成与配方形成凹槽24时较佳修整凹槽24底部两侧接触保护层20的角落使暴露出保护层20的两侧角落26分别形成曲面28，而凹槽24正下方的底表面也可依据制作工艺需求调整蚀刻配方呈现完全平坦的表面或曲面。换句话说，相较于现有制作工艺所形成的凹槽24角落大多呈现由两条直线交界处所构成的非曲面锐角或钝角型态，本实施例较佳通过上述干蚀刻与湿蚀刻制作工艺的组合将凹槽24两侧角落26由原本锐角或钝角的型态修整为弧状或曲面28，其中凹槽24两侧倾斜面30与曲面28的转折点可由保护层20与保护层22交界处上方便渐渐由平坦的倾斜面30转变为曲面28。依据本发明的较佳实施例，具有曲面28的凹槽24角落可有效避免后续所形成的栅极电极产生尖端放电并影响元件效能。
随后如图3所示，依序形成一P型半导体层32以及一栅极材料层34于保护层20表面并填入凹槽24内，再利用光刻暨蚀刻制作工艺去除部分栅极材料层34与部分P型半导体层32以形成一栅极结构36于阻障层16及保护层18上，其中栅极结构36较佳于图案化后包含一栅极电极38以及场极板(field plate)40设于栅极电极38两侧。更具体而言，设于之前凹槽24内的栅极材料层34较佳构成栅极电极38，而设于栅极电极38两侧保护层18上方的栅极材料层34则作为场极板40，其中栅极电极38较佳用来作为开启与关闭通道区的开关，而场极板40则负责将电场向上牵引并平衡与分散被牵引的大电流，进而提升元件可承受的最大电压。在本实施中，P型半导体层32较佳包含P型氮化镓(pGaN)，而栅极材料层34则较佳包含金属，例如可包含金、银或铂等萧特基(Schottky)金属。
此外，本阶段利用光刻暨蚀刻制作工艺图案化栅极材料层34以及P型半导体层32的过程中较佳依序进行一干蚀刻制作工艺以及一湿蚀刻制作工艺来去除部分栅极材料层34及部分P型半导体层32形成栅极电极38与场极板40，其中干蚀刻制作工艺可包含例如甲烷(CH4)以及/或氯气(Cl2)等蚀刻气体而湿蚀刻制作工艺则可包含例如羟基胺(hydroxylamine)。在本实施例中，甲烷的流量较佳介于10～100每分钟标准毫升(standardcubic centimeter per minute,sccm)，氯气的流量较佳介于10～100每分钟标准毫升，而稀释氢氟酸的稀释比例较佳约100:1。依据本发明一实施例，形成栅极电极38与场极板40之后可再选择性进行一退火制作工艺，利用氢气以及氮气在约摄氏400度的环境下将图案化的P型半导体层32与栅极材料层34定型。
另外需注意的是，本实施例利用上述蚀刻制作工艺进行图案转移时较佳先利用干蚀刻将P型半导体层32与栅极材料层34的侧壁修整为倾斜侧壁，再利用湿蚀刻制作工艺将设于保护层18正上方的P型半导体层32角落42形成曲面44。换句话说，相较于现有制作工艺所形成的P型半导体层32底部角落大多呈现由两条直线交界处所构成的非曲面锐角或钝角型态，本实施例较佳通过上述蚀刻制作工艺将位于保护层18正上方的P型半导体层32两侧角落42由原本锐角或钝角的型态修整为弧状或曲面。
随后如图4所示，形成一源极电极46以及一漏极电极48于栅极结构36两侧。在本实施例中，源极电极46与漏极电极48较佳由金属所构成，但有别于栅极电极38与场极板40由萧特基金属所构成，源极电极46与漏极电极48较佳由欧姆接触金属所构成。依据本发明一实施例，源极电极46与漏极电极48可各自包含钛、铝、钨、钯或其组合。在一些实施例中，可先以光刻暨蚀刻制作工艺去除栅极结构36两侧的部分保护层18、部分阻障层16甚至部分缓冲层14形成凹槽，利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于凹槽内形成电极材料，然后再以蚀刻将电极材料图案化以形成源极电极46与漏极电极48。
请再参照图4，图4又揭露本发明一实施例的一高电子迁移率晶体管的结构示意图。如图4所示，高电子迁移率晶体管主要包含缓冲层14设于基底12上，阻障层16设于缓冲层14上，栅极电极38设于阻障层16上，保护层18设于栅极电极38两侧，场极板40设于栅极电极38两侧的保护层18上以及P型半导体层32设于栅极电极38与阻障层16之间，其中保护层18较佳包含一双层结构，例如可细部包含保护层20与保护层22，保护层20较佳选自由氮化铝、氧化铝、碳化硅以及氮氧化硅所构成的群组而保护层22较佳包含氮化硅。
在本实施例中，P型半导体层32接触保护层20侧壁的一角落26包含一曲面28，同时设于保护层22正上方的P型半导体层32的另一角落42又包含另一曲面44，其中上述两个曲面的设计可有效避免栅极结构产生尖端放电进而影响元件效能。另外P型半导体层32接触阻障层16的底表面在本实施例中虽较佳为平坦表面，但依据本发明一实施例又可于图2形成凹槽24时调整蚀刻制作工艺的配方，使后续P型半导体层32接触阻障层16的底表面形成曲面，此变化型也属本发明所涵盖的范围。
请再参照图5，图5另揭露本发明一实施例的一高电子迁移率晶体管的结构示意图。如图5所示，相较于前述实施例的场极板侧壁具有平坦的倾斜面，
依据本发明又一实施例又可于图3图案化形成栅极电极38与场极板40的时候调整蚀刻制作工艺的配方，使场极板40以及/或P型半导体层32侧壁形成内凹曲面50，此变化型也属本发明所涵盖的范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种高电子迁移率晶体管，其特征在于，包含：
缓冲层，设于基底上；
阻障层，设于该缓冲层上；
栅极电极，设于该阻障层上；
场极板，相邻于该栅极电极的两侧，其中该栅极电极的顶表面与该场极板的顶表面齐平，且该场板的侧壁包含第一曲线；
第一保护层，相邻于该栅极电极两侧；以及
P型半导体层，设于该栅极电极以及该阻障层之间且直接接触该第一保护层，其中该P型半导体层的侧壁包含第二曲面，且该第一曲面连接到该第二曲面。
2.如权利要求1所述的高电子迁移率晶体管，其中该缓冲层包含III-V族半导体。
3.如权利要求2所述的高电子迁移率晶体管，其中该缓冲层包含氮化镓。
4.如权利要求1所述的高电子迁移率晶体管，其中该阻障层包含氮化铝镓(AlxGa1-xN)。
5.如权利要求1所述的高电子迁移率晶体管，其中该第一保护层包含氮化硅。
6.如权利要求1所述的高电子迁移率晶体管，另包含第二保护层，设于该第一保护层以及该阻障层之间。
7.如权利要求6所述的高电子迁移率晶体管，其中该第二保护层选自由氮化铝、氧化铝、碳化硅以及氮氧化硅所构成的群组。
8.如权利要求1所述的高电子迁移率晶体管，其中该P型半导体层包含P型氮化镓。
9.如权利要求1所述的高电子迁移率晶体管，其中该P型半导体层的底表面包含第三曲面。
10.如权利要求1所述的高电子迁移率晶体管，其中该场极板以及该栅极电极包含相同材料。
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