CN117879326A - GaN-FET parallel current sharing control circuit and method for multi-level driving signals - Google Patents
GaN-FET parallel current sharing control circuit and method for multi-level driving signals Download PDFInfo
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- CN117879326A CN117879326A CN202410281640.8A CN202410281640A CN117879326A CN 117879326 A CN117879326 A CN 117879326A CN 202410281640 A CN202410281640 A CN 202410281640A CN 117879326 A CN117879326 A CN 117879326A
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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Abstract
The invention relates to the technical field of power electronics, and discloses a GaN-FET parallel current sharing control circuit and method for a multi-level driving signal, wherein the GaN-FET parallel current sharing control circuit comprises the following steps: through the technical scheme, the current monitoring module and the control module sample and calculate the current flowing through each power module unit to obtain each effective value and peak value respectively, after the unbalance degree of the effective value and the peak value is calculated, the driving voltage signal VCC required by the next switching moment can be calculated, and then the output voltage VCC is changed by correspondingly adjusting the multi-level generating module, so that the opening time of the power module units can be changed, and the current balance degree of the three power module units is affected.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a GaN-FET parallel current sharing control circuit and method for a multi-level driving signal.
Background
Power devices are a class of electronic components specifically designed to handle and manage high current, high voltage, and high power electrical energy. These devices are used to control the transfer, conversion, distribution and regulation of electrical energy, and generally involve high efficiency and high power applications of electrical energy. The primary function of a power device is to convert electrical energy from one form to another, for example from direct current to alternating current, or from low voltage to high voltage, to meet the needs of different applications. Some common power devices include: insulated Gate Bipolar Transistors (IGBTs), effect transistors (FETs), thyristors (SCRs), and TRIAC (TRIACs);
through research and analysis on the third generation of semiconductors and GaN materials, compared with the semiconductors in the first two ages, gaN has the advantages of wider energy gap, better breakdown field strength, better thermal conductivity, better electron saturation rate and better radiation resistance. Because GaN has higher switching frequency, higher output power and higher working temperature, the GaN field effect transistor (GaN_FET) is suitable for high-frequency working conditions, has wide development prospect, and obviously improves the power density and the efficiency of products along with the increase of frequency.
However, due to the limitation of manufacturing process and cost, the current capacity of a single GaN chip is only tens of amperes, in high-power application occasions such as electric transmission, new energy sources and the like, a multi-chip parallel module is often needed, parasitic parameter uneven distribution and power tube parameter consistency problems are inevitably encountered in a parallel circuit, the switching frequency of a GaN material power device is higher, the current change rate is larger, and larger voltage interference than that of a Si device is caused, so that a more serious current imbalance problem is caused.
The reasons for the imbalance are mainly the on-resistance, temperature, branch inductance distribution, gate drive resistance, parasitic capacitance, threshold voltage and drive signal imbalance of the device. The unbalanced phenomenon can lead the parallel devices to generate asymmetric switching speeds, so that in the switching-on process of the devices, a device with a high switching-on speed is easy to overload, the device is easy to damage, and the whole system is damaged. It is therefore necessary to improve the GaN FET shunt current sharing problem.
Disclosure of Invention
The invention aims to provide a GaN-FET parallel current sharing control circuit and method for a multi-level driving signal, which solve the following technical problems:
how to improve the parallel current sharing problem of GaN_FET.
The aim of the invention can be achieved by the following technical scheme:
a gan_fet parallel current sharing control circuit of a multi-level drive signal, comprising:
the multi-level generation module is used for responding to the adjusting instruction to generate a driving voltage signal VCC and a negative voltage signal VEE with specified amplitude;
the grid driving module is connected with the multi-level generating module and is used for outputting corresponding grid driving signals according to the driving voltage signal VCC, the negative voltage signal VEE and the PWM driving signals;
the main power module comprises a plurality of groups of power module units connected with the grid driving modules, and each power module unit is used for realizing on-off according to the corresponding grid driving signals and realizing the adjustment of on-off speeds according to the amplitude change of the corresponding driving voltage signals VCC;
the current monitoring module is connected with the main power module and the control module and is used for acquiring an analog feedback signal representing the current of a transistor passing through the main power module and transmitting the analog feedback signal to the control module;
and the control module is connected with the multi-level generation module, the grid driving module and the current monitoring module and is used for calculating a driving voltage signal VCC required by the next switching moment according to the analog feedback signal and sending out the regulating instruction and the PWM driving signal.
As a further scheme of the invention: the multi-level generating module comprises a resistor R1, a parallel resistor array R2, a parallel signal switch array K, a resistor R3, a reference voltage Vref, a comparator comp, a MOS tube M1 and a diode D1;
wherein the parallel resistor array R2 comprises n resistors R2_i, the parallel signal switch array K comprises n signal switches K_i,one end of the signal switch K_i is connected with one end of the resistor R3, the other end of the signal switch K_i is connected with one end of the resistor R2_i, the other end of the resistor R2_i is connected with one end of the resistor R1 and grounded, and the other end of the resistor R3 is connected with an input voltage Vin;
the positive electrode of the comparator comp is grounded, the positive electrode of the reference voltage Vref is connected with the negative electrode of the comparator comp, and one end of the resistor R1, which is far away from the grounding end, and the negative electrode of the reference voltage Vref are output ends VEE;
the grid electrode of the MOS tube M1 is connected with the output side of the comparator comp, the drain electrode of the MOS tube M1 is used as an output end VCC to be connected with the cathode of the diode D1, and the source electrode of the MOS tube M1 is connected with the output end VEE and the anode of the diode D1;
the output terminal VCC outputs the driving voltage signal VCC, and the output terminal VEE outputs the negative voltage signal VEE.
As a further scheme of the invention: the grid driving module comprises an N-type transistor N_MOS, a P-type transistor P_MOS, an on resistor Ron, an on diode Don, an off resistor Roff, an off diode Doff, a pull-down resistor R_down and a voltage stabilizing diode D_hold;
the grid electrodes of the N-type transistor N_MOS and the P-type transistor P_MOS are connected, and then the PWM driving signal output end of the control module is connected;
the source electrode of the N-type transistor N_MOS is connected with the drain electrode of the P-type transistor P_MOS, the drain electrode of the N-type transistor N_MOS is connected with the output end VCC, and the drain electrode of the P-type transistor P_MOS is connected with the output end VEE;
one end of the on resistor Ron is connected with the anode of the on diode Don, one end of the off resistor Roff is connected with the cathode of the off diode Doff, the other end of the on resistor Ron is connected with one end of the off resistor Roff and then connected with the source electrode of the N-type transistor N_MOS, the cathode of the on diode Don is connected with the anode of the off diode Doff and then connected with one end of the pull-down resistor R_down and the cathode of the voltage stabilizing diode D_hold, and the anode of the voltage stabilizing diode D_hold is connected with the other end of the pull-down resistor R_down and then grounded.
A GaN_FET parallel current sharing control method of a multi-level driving signal comprises the following steps:
s100, after the control circuit is electrified, configuration and initialization are carried out, and PWM driving signals with the same phase sequence are output;
s200, a multi-level generating module and a grid driving module work, and corresponding power module units are driven to be turned on and turned off by the same driving voltage signal VCC and negative voltage signal VEE;
s300, obtaining transistor current of the power module unit and an analog feedback signal of the transistor current through a current monitoring module;
s400, calculating the peak value of each transistor current through the control moduleAnd effective value；
S500, respectively calculating peak uniformity of the transistor currentAnd effective value uniformity->；
S600, judging whether a uniformity calculation result meets a preset requirement, if so, returning to the step S300, otherwise, entering into the step S700;
s700, determining a corresponding adjustment strategy of the driving voltage signal VCC according to the influence trend of the key parameters in the power module unit opening process;
s800, the input and output of the multi-level generation module are adjusted according to the adjustment strategy, and then the step S300 is returned.
As a further scheme of the invention: the step S500 includes:
wherein->Is peak valueAverage value of>For the current peak value of the h-th power module unit, m is the total number of the power module units,/->，/>Is the effective value of current->Is the effective value of current->Average value of>Is the current effective value of the h-path power module unit.
As a further scheme of the invention: the step S700 includes:
for each power module unit, recording the uniformity of the jth cycleAnd the high-low level quantity of the IO port of the multi-level control unit;
synthesizing an opening time algorithm formula according to the driving voltage signal VCC and the opening speed, and the peak valueInversely proportional to on time and said validityValue->And obtaining the adjustment strategy of the driving voltage signal VCC for reducing the uniformity of the next switching moment according to the inverse relation of the on time.
Synthesizing an opening time algorithm formula according to the driving voltage signal VCC and the opening speed, and the peak valueInversely proportional to the on-time and said effective value +.>And obtaining the adjustment strategy of the driving voltage signal VCC for reducing the uniformity of the next switching moment according to the inverse relation of the on time.
As a further scheme of the invention: the opening time algorithm formula is as follows:
wherein Cdg and Cgs are parasitic capacitances of the drain gate and the gate source of the power module unit, respectively, +.>For the threshold voltage of the power module unit, < >>For the power module cell drain current, +.>For the transconductance of the power module unit, +.>Is the on time.
The invention has the beneficial effects that: the invention samples and calculates the current flowing through each power module unit through the current monitoring module and the control module to obtain each effective value and peak value respectively, after the unbalance degree of the effective value and the peak value is calculated, the driving voltage signal VCC required by the next switching moment can be calculated, and then the output voltage VCC is changed by correspondingly adjusting the multi-level generating module, so that the opening time of the power module units can be changed, and the current balance degree of the three power module units is influenced.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the overall module of the GaN-FET parallel current sharing control circuit of the invention;
FIG. 2 is a circuit diagram of a multi-level generation module according to the present invention;
FIG. 3 is a schematic diagram of a gate driving module according to the present invention;
FIG. 4 is a control module workflow diagram of the present invention;
FIG. 5 is a flowchart of PWM driving signal generation according to the present invention;
fig. 6 is a flowchart of calculating the driving voltage signal VCC in the control module of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention is a gan_fet parallel current sharing control circuit for multi-level driving signals, comprising:
a main power module including three groups of power module units, which in this embodiment are gallium nitride field effect transistors (gan_fets);
the drain electrode of each GaN_FET is connected with Ubus, the source electrode is connected with PGND, and the on-off is realized according to the corresponding grid driving signal;
the multi-level generation module is provided with three groups corresponding to the number of the power module units, is respectively connected with the three GaN-FETs and is used for responding to the adjusting instruction to generate a driving voltage signal VCC and a negative voltage signal VEE with specified amplitude; the amplitude of the driving voltage signal VCC is controllable, the range of 3V-7V is adjustable, and the driving voltage signals VCC with different amplitudes can influence the on time of the GaN_FET, so that the on and off speeds of each GaN_FET are adjusted;
the grid driving module is also provided with three groups corresponding to the power module units, namely the number of GaN_FETs, is connected with the multi-level generating module and the control module, and is used for outputting corresponding grid driving signals according to the driving voltage signals VCC, the negative voltage signals VEE and PWM driving signals, carrying out power amplification after receiving the PWM driving signals, outputting driving currents and correspondingly controlling the on and off of each GaN_FET;
the current monitoring module is connected with the main power module and the control module and is used for acquiring an analog feedback signal of the current flowing through each GaN-FET and sending the analog feedback signal to the control module; the sensor of the current monitoring module adopts an AH3503 linear Hall sensor, and the AH3503 linear Hall sensor has the advantages of high sensitivity, low power consumption, high reliability, small size, portability and the like, and is very suitable for application occasions requiring high precision, low power consumption and small size.
The control module comprises an FPGA and a peripheral circuit thereof, and can be used for receiving an analog feedback signal, calculating the current uniformity, outputting a PWM driving signal, and simultaneously sending out an adjusting instruction to control the multi-level generation module to output a driving voltage signal VCC with a corresponding amplitude required by the next switching moment.
The peripheral circuit comprises a PWM driving signal generating unit, a multi-level signal control unit, an ADC sampling unit, a closed loop judging unit and crystal oscillator configuration and reset in a minimum system; the PWM driving signal generating unit consists of three IO ports, the multi-level signal control unit connected with the multi-level generating module is divided into three groups, each group consists of n IO ports, and the ADC sampling unit comprises three groups of ADC sampling modules.
As shown in fig. 2, the multi-level generating module includes a resistor R1, a parallel resistor array R2, a parallel signal switch array K, a resistor R3, a reference voltage Vref, a comparator comp, a MOS transistor M1, and a diode D1;
wherein the parallel resistor array R2 comprises n resistors R2_i, the parallel signal switch array K comprises n signal switches K_i,one end of the signal switch K_i is connected with one end of the resistor R3, the other end of the signal switch K_i is connected with one end of the resistor R2_i, the other end of the resistor R2_i is connected with one end of the resistor R1 and grounded, and the other end of the resistor R3 is connected with an input voltage Vin;
the positive electrode of the comparator comp is grounded, the positive electrode of the reference voltage Vref is connected with the negative electrode of the comparator comp, and one end of the resistor R1, which is far away from the grounding end, and the negative electrode of the reference voltage Vref are output ends VEE;
the grid electrode of the MOS tube M1 is connected with the output side of the comparator comp, the drain electrode of the MOS tube M1 is used as an output end VCC to be connected with the cathode of the diode D1, and the source electrode of the MOS tube M1 is connected with the output end VEE and the anode of the diode D1;
the output terminal VCC outputs the driving voltage signal VCC, and the output terminal VEE outputs the negative voltage signal VEE.
The sum of absolute values of a driving voltage signal VCC and a negative voltage signal VEE at the output end of the multi-level generation module is equal to Vin, and the amplitudes of the driving voltage signal VCC and the negative voltage signal VEE are controlled by a parallel resistor array R2, a resistor R1 and a reference voltage Vref, wherein the specific relation is as follows:in this embodiment, the reference voltage Vref is set to 1V, the resistance value of the resistor R1 is set to 10kΩ, the parallel resistor array R2 is configured by connecting n 60 kresistors r2_i in parallel, the signal switch k_i is a signal MOS with 3.3V on, the resistance value of the resistor R3 is set to 10kΩ, and the MOS transistor M1 selects a model with a threshold voltage of 3V or less.
Thus, after the input voltage Vin and the reference voltage Vref are determined, the voltage values at both ends of the resistor R1 represent the positive and negative input voltage difference V0 of the comparator comp;
when V0 is larger than Vref, the comparator comp outputs high level to enable the MOS tube M1 to be conducted, at the moment, the resistor R3, the parallel resistor array R2 and the resistor R1 are equivalent to being short-circuited, and at the moment, V0 starts to decline;
when V0 is reduced to be lower than the reference voltage Vref, the comparator comp outputs a low level, and at the moment, the voltages of the resistor R3, the parallel resistor array R2 and the resistor R1 start to rise; returning to the initial state until V0> Vref moment;
the above is the fast dynamic adjustment process of the multi-level generation module, and the final result is that the voltage values at two ends of the resistor R1 are stably equal to the reference voltage Vref, so that the voltage (i.e., VCC) at two ends of the parallel resistor array R2 is in proportional relation with the resistor R1 through the series voltage division principle;
that is, by changing the resistance of the parallel resistor array R2, the driving voltage signal VCC can be changed.
It is noted that the resistance values of the resistor R3, the parallel resistor array R2 and the resistor R1 are selected to be more than 4.7KΩ as much as possible, and the resistance value of the parallel resistor array R2 is 60KΩ at the maximum; i.e. the maximum output 7V of the drive voltage signal VCC is the maximum gate drive voltage that can be tolerated to meet the GaN _ FET.
As shown in fig. 3, the gate driving module includes an N-type transistor n_mos, a P-type transistor p_mos, an on resistor Ron, an on diode Don, an off resistor Roff, an off diode Doff, a pull-down resistor r_down, and a zener diode d_hold;
the grid electrodes of the N-type transistor N_MOS and the P-type transistor P_MOS are connected, and then the PWM driving signal output end of the control module is connected;
the source electrode of the N-type transistor N_MOS is connected with the drain electrode of the P-type transistor P_MOS, the drain electrode of the N-type transistor N_MOS is connected with the output end VCC, and the drain electrode of the P-type transistor P_MOS is connected with the output end VEE;
one end of the on resistor Ron is connected with the anode of the on diode Don, one end of the off resistor Roff is connected with the cathode of the off diode Doff, the other end of the on resistor Ron is connected with one end of the off resistor Roff and then connected with the source electrode of the N-type transistor N_MOS, the cathode of the on diode Don is connected with the anode of the off diode Doff and then connected with one end of the pull-down resistor R_down and the cathode of the voltage stabilizing diode D_hold, and the anode of the voltage stabilizing diode D_hold is connected with the other end of the pull-down resistor R_down and then grounded.
In this embodiment, the resistance value of the on resistor Ron is smaller than the off resistor Roff, the on diode Don and the off diode Doff both select schottky fast recovery diodes, and the voltage stabilizing diode d_hold selects a voltage stabilizing value of 7V.
Thus, when the PWM driving signal is at a high level, the N-type transistor n_mos is turned on, the P-type transistor p_mos is turned off, the driving voltage signal VCC flows through the on-resistance Ron and the on-diode Don to reach the gate of the gan_fet, and when the voltage of the capacitor Cgs reaches the threshold voltage, the gan_fet starts to be turned on; when the PWM driving signal is at a low level, the N-type transistor N_MOS is turned off, the P-type transistor P_MOS is turned on, and the charge stored by the capacitor Cgs flows through the P-type transistor P_MOS to a negative voltage signal VEE through the turn-off diode Doff and the turn-off resistor Roff;
the pull-down resistor R_Down is used for preventing the GaN_FET from being turned on by mistake, and the voltage stabilizing diode D_hold is used for preventing the grid electrode of the GaN_FET from being damaged by overvoltage.
A GaN_FET parallel current sharing control method of a multi-level driving signal comprises the following steps:
s100, after the control circuit is electrified, configuration and initialization are carried out, and PWM driving signals with the same phase sequence are output;
specifically, after 3.3V is supplied to the FPGA for electric stabilization, the FPGA is configured with an external crystal oscillator, and a system crystal oscillator of 200MHz is obtained by frequency division and frequency multiplication through configuration of InitPll (PLLCR, DIVSEL) functions, and configuration is carried outIs the expected value;
three paths of same-phase-sequence PWM driving signals are output through a counting register CNT_PWM, and a PWM driving signal generating unit consists of three IO ports and outputs three paths of pulse waveforms with the same phase, 500kHz and 50% duty ratio respectively; each group of IO ports controlled by multiple levels defaults n/2 high levels and n/2 low levels, namely defaults output driving voltage signals VCC are 5V and negative voltage signals VEE level signals are-1V;
as shown in fig. 5, a flow chart of generating three PWM driving signals for the PWM driving signals is shown, and the design number registers cnt_pwm=0, data 1=0, data 2=0, data 3=0 correspond to the output IO ports 1, 2, 3. The system frequency is 200MHz, a square wave with the duty ratio of 500KHz and 50% is expected to be output, the count register CNT_PWM is increased along with the system crystal oscillator, so that the CNT_PWM is increased to 400 to be one period, and when the CNT_PWM=200, the data 1=1, the data 2=1 and the data 3=1 can ensure that the duty ratio is 50%.
S200, a multi-level generating module and a grid driving module work, and corresponding power module units are driven to be turned on and turned off by the same driving voltage signal VCC and negative voltage signal VEE; however, due to the difference in parasitic parameters inside and outside the device of each gan_fet, the dynamic and static characteristics of the currents Ia, ib, ic flowing through the three gan_fets are all different;
s300, obtaining transistor current of the power module unit and an analog feedback signal of the transistor current through a current monitoring module; wherein, the analog feedback signals are converted by Ia, ib and Ic;
s400, calculating the peak value of each transistor current through the control moduleAnd effective value；
S500, respectively calculating peak uniformity of the transistor currentAnd effective value uniformity->；
Specifically, the step S500 includes:wherein (1)>For peak +.>Average value of>For the current peak value of the h-th power module unit, m is the total number of the power module units,/->，/>Is the effective value of current->Is the effective value of current->Average value of>Is the current effective value of the h-path power module unit.
As shown in FIG. 6, S600, judging whether the uniformity calculation result is larger thanI.e. as long as the peak uniformity +.>And effective value uniformity->Any one of uniformity +.>Greater than the expected value->If the result is not satisfied, the result is regarded as satisfied, otherwise, the result is not satisfied;
if yes, returning to the step S300, otherwise, entering a step S700;
s700, determining a corresponding adjustment strategy of the driving voltage signal VCC according to the influence trend of the key parameters in the power module unit opening process;
wherein, step S700 includes:
for each power module unit, recording the uniformity of the jth cycleAnd the high-low level quantity of the IO port of the multi-level control unit;
synthesizing an opening time algorithm formula according to the driving voltage signal VCC and the opening speed, and the peak valueInversely proportional to the on-time and said effective value +.>And obtaining the adjustment strategy of the driving voltage signal VCC for reducing the uniformity of the next switching moment according to the inverse relation of the on time.
As shown, the strategy is adjusted such that, whenWhen the peak current is the same, the parallel resistor array R2 of the loop with the maximum peak current is reduced to 0.5 times of the original parallel resistor array R2 of the loop with the minimum peak current is increased to 2 times of the original parallel resistor array R2; when (when)In this case, the parallel resistor array R2 of the peak current maximum loop is reduced by 0.75 times, and the parallel resistor array R2 of the peak current minimum loop is increased by 1.5 times.
The above-mentioned open time algorithm formula is:wherein Cdg and Cgs are parasitic capacitances of the drain gate and the gate source of the power module unit, respectively, < >>For the threshold voltage of the power module unit, < >>For the power module cell drain current, +.>For the transconductance of the power module unit,is the on time.
S800, the input and output of the multi-level generation module are adjusted according to the adjustment strategy, and then the step S300 is returned.
In summary, after the system is powered stably, the control module works first, after the three paths of driving signals and the multi-level control signals are output, the grid driving module and the multi-level generating module start to work, then three GaN_FETs connected in parallel start to have current flowing, after the current monitoring module and the ADC sampling module work, the main control chip FPGA can obtain the characteristic quantity of the three paths of current, and the balance degree of the three paths of current can be obtained through calculation; comparing the calculated value with the expected balance degree, if the balance degree obtained by actual measurement is poor, greatly changing the driving voltage signal VCC, otherwise, fine tuning, and if the calculated value reaches the expected value, not changing the amplitude of VCC; and then the sampling and operation processes are repeated continuously, so that the balance degree can be kept within the expected value in real time.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (7)
1. The GaN-FET parallel current sharing control circuit of the multi-level driving signal is characterized by comprising:
the multi-level generation module is used for responding to the adjusting instruction to generate a driving voltage signal VCC and a negative voltage signal VEE with specified amplitude;
the grid driving module is connected with the multi-level generating module and is used for outputting corresponding grid driving signals according to the driving voltage signal VCC, the negative voltage signal VEE and the PWM driving signals;
the main power module comprises a plurality of groups of power module units connected with the grid driving modules, and each power module unit is used for realizing on-off according to the corresponding grid driving signals and realizing the adjustment of on-off speeds according to the amplitude change of the corresponding driving voltage signals VCC;
the current monitoring module is connected with the main power module and the control module and is used for acquiring an analog feedback signal representing the current of a transistor passing through the main power module and transmitting the analog feedback signal to the control module;
and the control module is connected with the multi-level generation module, the grid driving module and the current monitoring module and is used for calculating a driving voltage signal VCC required by the next switching moment according to the analog feedback signal and sending out the regulating instruction and the PWM driving signal.
2. The gan_fet parallel current sharing control circuit of a multi-level driving signal according to claim 1, wherein the multi-level generating module comprises a resistor R1, a parallel resistor array R2, a parallel signal switch array K, a resistor R3, a reference voltage Vref, a comparator comp, a MOS transistor M1, and a diode D1;
wherein the parallel resistor array R2 comprises n resistors R2_i, the parallel signal switch array K comprises n signal switches K_i,one end of the signal switch K_i is connected with one end of the resistor R3, the other end of the signal switch K_i is connected with one end of the resistor R2_i, the other end of the resistor R2_i is connected with one end of the resistor R1 and grounded, and the other end of the resistor R3 is connected with an input voltage Vin;
the positive electrode of the comparator comp is grounded, the positive electrode of the reference voltage Vref is connected with the negative electrode of the comparator comp, and one end of the resistor R1, which is far away from the grounding end, and the negative electrode of the reference voltage Vref are output ends VEE;
the grid electrode of the MOS tube M1 is connected with the output side of the comparator comp, the drain electrode of the MOS tube M1 is used as an output end VCC to be connected with the cathode of the diode D1, and the source electrode of the MOS tube M1 is connected with the output end VEE and the anode of the diode D1;
the output terminal VCC outputs the driving voltage signal VCC, and the output terminal VEE outputs the negative voltage signal VEE.
3. The gan_fet parallel current sharing control circuit of claim 1, wherein the gate drive module comprises an N-type transistor n_mos, a P-type transistor p_mos, an on resistor Ron, an on diode Don, an off resistor Roff, an off diode Doff, a pull-down resistor r_down, and a zener diode d_hold;
the grid electrodes of the N-type transistor N_MOS and the P-type transistor P_MOS are connected, and then the PWM driving signal output end of the control module is connected;
the source electrode of the N-type transistor N_MOS is connected with the drain electrode of the P-type transistor P_MOS, the drain electrode of the N-type transistor N_MOS is connected with the output end VCC, and the drain electrode of the P-type transistor P_MOS is connected with the output end VEE;
one end of the on resistor Ron is connected with the anode of the on diode Don, one end of the off resistor Roff is connected with the cathode of the off diode Doff, the other end of the on resistor Ron is connected with one end of the off resistor Roff and then connected with the source electrode of the N-type transistor N_MOS, the cathode of the on diode Don is connected with the anode of the off diode Doff and then connected with one end of the pull-down resistor R_down and the cathode of the voltage stabilizing diode D_hold, and the anode of the voltage stabilizing diode D_hold is connected with the other end of the pull-down resistor R_down and then grounded.
4. A gan_fet parallel current sharing control method of a multi-level driving signal, applied to the gan_fet parallel current sharing control circuit of a multi-level driving signal according to any one of claims 1 to 3, comprising:
s100, after the control circuit is electrified, configuration and initialization are carried out, and PWM driving signals with the same phase sequence are output;
s200, a multi-level generating module and a grid driving module work, and corresponding power module units are driven to be turned on and turned off by the same driving voltage signal VCC and negative voltage signal VEE;
s300, obtaining transistor current of the power module unit and an analog feedback signal of the transistor current through a current monitoring module;
s400, calculating the peak value of each transistor current through the control moduleAnd effective value +.>；
S500, respectively calculating peak uniformity of the transistor currentAnd effective value uniformity->；
S600, judging whether a uniformity calculation result meets a preset requirement, if so, returning to the step S300, otherwise, entering into the step S700;
s700, determining a corresponding adjustment strategy of the driving voltage signal VCC according to the influence trend of the key parameters in the power module unit opening process;
s800, the input and output of the multi-level generation module are adjusted according to the adjustment strategy, and then the step S300 is returned.
5. The gan_fet parallel current sharing control method of multi-level driving signal according to claim 4, wherein said step S500 comprises:
wherein->For peak +.>Average value of>A current peak value for the h-th power module unit, m is the total number of the power module units,，/>is the effective value of current->Is the effective value of current->Average value of>Is the current effective value of the h-path power module unit.
6. The gan_fet parallel current sharing control method of multi-level driving signal according to claim 4, wherein said step S700 comprises:
for each power module unit, recording the uniformity of the jth cycleAnd the high-low level quantity of the IO port of the multi-level control unit;
synthesizing an opening time algorithm formula according to the driving voltage signal VCC and the opening speed, and the peak valueInversely proportional to the on-time and said effective value +.>And obtaining the adjustment strategy of the driving voltage signal VCC for reducing the uniformity of the next switching moment according to the inverse relation of the on time.
7. The gan_fet parallel current sharing control method of a multi-level driving signal according to claim 1, wherein the on-time algorithm formula is:wherein Cdg and Cgs are parasitic capacitances of the drain gate and the gate source of the power module unit, respectively, +.>For the threshold voltage of the power module unit, < >>For the power module cell drain current, +.>For the transconductance of the power module unit, +.>Is the on time.
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