CN114629333A - Multi-level driving circuit for restraining dv/dt crosstalk of high-frequency GaN power device - Google Patents
Multi-level driving circuit for restraining dv/dt crosstalk of high-frequency GaN power device Download PDFInfo
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- CN114629333A CN114629333A CN202210419111.0A CN202210419111A CN114629333A CN 114629333 A CN114629333 A CN 114629333A CN 202210419111 A CN202210419111 A CN 202210419111A CN 114629333 A CN114629333 A CN 114629333A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
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Abstract
The invention belongs to the technical field of driving of power electronic devices, and particularly relates to a multi-level driving circuit for inhibiting dv/dt crosstalk of a high-frequency GaN power device. The driving signal gating circuit is used for gating positive and negative square waves to drive the GaN power device, the negative voltage generating circuit is used for generating negative voltage to prevent misconduction of the GaN power device during the turn-off period, and the comparator control circuit is used for realizing intermediate level clamping to prevent reverse breakdown of the GaN power device at the turn-on moment. The intermediate level clamping response speed is higher, so that the GaN power device can safely work at the switching frequency of 5MHz or above, and the advantage of high-frequency application of the GaN power device is fully exerted; the negative voltage generating circuit has a simple structure and a wider working frequency range, so that the switch tube which can be driven by the negative voltage generating circuit comprises but is not limited to a high-frequency GaN power device; meanwhile, the method has the advantage of reducing the loss of the driving circuit.
Description
Technical Field
The invention belongs to the technical field of driving of power electronic devices, and particularly relates to a multi-level driving circuit for restraining dv/dt crosstalk of a high-frequency GaN power device.
Background
Compared with a first-generation semiconductor Si power device, the high-frequency GaN power device has smaller parasitic capacitance, so that the switching loss is further reduced, the switching frequency can reach the level above MHz, the size of a magnetic element can be effectively reduced, and the conversion efficiency and the power density of a system are improved, so that the high-frequency GaN power device is widely applied to the power conversion fields of consumption fast charging, automobile electronics and the like.
Due to the fast switching speed, the fast voltage change (dv/dt) between the drain and the source of the GaN power device is often accompanied in the application of a direct current high voltage circuit, and the dv/dt phenomenon can generate a positive or negative crosstalk spike pulse on the grid of the GaN power device. In addition, because of the high electron mobility of GaN materials, GaN power devices are often used in high frequency switching applications above MHz. At present, the minimum threshold voltage of a commercial GaN power device is about 0.8-1.1V, the minimum grid safety negative voltage is only-4-10V, and the switching frequency can reach more than 10 MHz. Therefore, under the working condition of high switching frequency, the problems of misconduction, reverse breakdown and the like of the high-frequency GaN power device are easily caused by dv/dt positive and negative crosstalk in the turn-off process, and the efficient and reliable work of the system is further influenced.
In existing multilevel driving schemes for suppressing dv/dt crosstalk, including but not limited to high frequency GaN power device driving, the basic technical path mainly includes: 1) a single power supply, multiple control signals, 2) a single control signal, multiple power supplies (positive, negative, and mid-level power supplies), 3) a single power supply, single control signal.
The technical idea of adopting a single power supply and a plurality of control signals is to generate negative voltage required by a driving circuit by means of the principle of generating negative voltage by a capacitance charge pump and matching with a PWM control signal. The technical idea of adopting a single control signal and multiple power supplies (a positive power supply, a negative power supply and a middle level power supply) is to control the on-off of a PMOS tube through an auxiliary circuit during the turn-off period of a high-frequency GaN power device so as to realize middle level clamping, but the mode of the multiple power supplies increases the complexity and the cost of circuit and board level design. The technical idea of using a single power supply and a single control signal is to combine the advantages of the two schemes, so that not only can crosstalk be suppressed, but also the circuit design is simple, but in an auxiliary circuit for generating a clamping intermediate level control signal, an RC delay circuit scheme is generally used.
The RC delay circuit controls the on-off of the PMOS tube by using the voltage change waveform of capacitor charge and discharge so as to clamp the intermediate level. Although the circuit is simple in structure, the voltage change of the RC circuit is slow, and the response time of a level clamp in the existing scheme is about 100ns at the fastest speed. For GaN power devices with high frequency switching advantages, the response speed of 100ns may cause the GaN power devices to have a risk of reverse breakdown in switching applications with frequencies of 5MHz (T/2 ═ 100ns) and above, because the negative level cannot be raised to near the zero level in time, and the high frequency GaN power devices are superimposed with negative spike pulses. Therefore, the scheme of generating the intermediate level clamp control signal by adopting the RC delay circuit is difficult to exert the high-frequency switching characteristic of the GaN power device with the frequency of 5MHz or more.
Disclosure of Invention
The invention aims to overcome the problems in the multilevel driving of the scheme 3) and provides an improved multilevel driving circuit suitable for GaN power devices with the switching frequency of 5MHz or more. The circuit not only realizes the function of suppressing dv/dt positive and negative crosstalk of a single power supply and a single control signal in the scheme 3), but also generates a signal for controlling the on-off of the PMOS tube by means of a low-delay high-speed comparator, realizes the faster turn-on speed of the PMOS tube, and ensures that the multilevel drive is suitable for the switch application of a high-frequency GaN power device at the frequency of 5MHz or more. In addition, when the negative voltage generating circuit in the circuit is matched with the comparator control circuit, the circuit can stably work in a wider working frequency range, so that the switch tube which can be driven by the circuit comprises but is not limited to a high-frequency GaN power device, and the circuit has the advantage of reducing the loss of a driving circuit.
In order to achieve the purpose, the invention adopts the technical scheme that: a multi-level driving circuit for suppressing dv/dt crosstalk of a high-frequency GaN power device comprises a driving signal gating circuit, a negative voltage generating circuit and a comparator control circuit. The driving signal gating circuit is used for gating positive and negative square waves to drive the GaN power device, the negative voltage generating circuit is used for generating negative voltage to prevent misconduction of the GaN power device during the turn-off period, and the comparator control circuit is used for realizing intermediate level clamping to prevent reverse breakdown of the GaN power device at the turn-on moment. The intermediate level clamping response speed is higher, so that the GaN power device can safely work at the switching frequency of 5MHz or above, and the advantage of high-frequency application of the GaN power device is fully exerted; the negative voltage generating circuit has a simple structure and a wider working frequency range, so that the switch tube which can be driven by the negative voltage generating circuit comprises but is not limited to a high-frequency GaN power device; meanwhile, the method has the advantage of reducing the loss of the driving circuit.
Further, the driving signal gating circuit includes: the PMOS transistor M1 and the NMOS transistor M2, wherein the source electrode of the PMOS transistor M1 is connected with the output end of the half-bridge drive IC and is used for gating the positive square wave generated by the half-bridge drive IC; the source electrode of the NMOS tube M2 is connected with the output end of the negative voltage generating circuit and is used for gating the negative square wave generated by the negative voltage generating circuit, and the grid electrode of the PMOS tube M1 and the grid electrode of the NMOS tube M2 are grounded together and are used for serving as reference for gating positive and negative pulses.
The negative voltage generating circuit includes: a capacitor C1 and a Schottky diode D1, wherein one end of the capacitor C1 is connected with the output end of the half-bridge driving IC, the cathode of the Schottky diode D1 is connected with the circuit reference point, the other end of the capacitor C1 is connected with the anode of the Schottky diode D1 in series, and the middle node is used as the output end of the negative voltage generating circuit.
The comparator control circuit includes: the high-frequency GaN power device comprises a high-speed comparator chip U1, an RC parallel circuit, current-limiting resistors R1 and R3, a Schottky diode D2 and a PMOS tube M3, wherein one end of the RC parallel circuit is connected with the non-inverting input end of the high-speed comparator chip U1, the current-limiting resistors R1 and R3 are respectively connected with the non-inverting input end and the inverting input end of the high-speed comparator chip U1, the grid electrode of the PMOS tube M3 is connected with the output end of the high-speed comparator chip U1, the drain electrode of the PMOS tube M3 is connected with the anode electrode of the Schottky diode D3, and the cathode electrode of the Schottky diode D3 is connected with the grid electrode of the driven high-frequency GaN power device.
It should be noted that the dv/dt phenomenon is essentially caused by the high applied dc voltage or the fast switching speed of the device, so that the applied dc voltage of the wide bandgap device such as SiC MOSFET and SiC IGBT is higher although the switching speed is lower than that of the high frequency GaN power device, and the dv/dt crosstalk problem is still an important factor that is not negligible in driving, so the topology and method of multilevel driving described in the present invention is applicable to all power devices having dv/dt crosstalk influence in switching application, not limited to the high frequency GaN power device, and the specific circuit parameters are determined by the characteristics of the specific device itself.
By adopting the technical scheme, the invention has the beneficial effects that:
the invention provides a multilevel driving circuit for inhibiting dv/dt crosstalk of a high-frequency GaN power device. The circuit not only realizes the function of restraining dv/dt positive and negative crosstalk by a single power supply and a single control signal, but also has the following advantages: 1) the comparator control circuit can generate a signal for controlling the on-off of the PMOS tube by means of a low-delay high-speed comparator, and can realize faster conduction of the PMOS tube relative to an RC delay circuit because the output signal of the high-speed comparator is a rapidly-jumping square wave signal. Simulation verification proves that the invention realizes the 8ns switching-on speed of the PMOS tube, improves the switching-on speed by more than ten times compared with an RC delay circuit, and can effectively avoid the risk that the high-frequency GaN power device is reversely punctured due to the fact that the negative level can not be lifted in time in the switch application of the high-frequency GaN power device with the frequency of 5MHz or more; 2) the negative voltage generating circuit has a simple structure and a wider working frequency range, is only composed of a capacitor and a Schottky diode, has a simpler structure, can meet the requirement of switching frequency application of 5MHz or more, and can still stably work in low-frequency application with the switching frequency of about hundred KHz due to the fact that the load impedance is larger and the negative voltage energy stored by the capacitor is difficult to discharge rapidly when the output end is connected to the comparator control circuit, so that the negative voltage generating circuit has a wider working frequency range and can drive a switching tube comprising but not limited to a high-frequency GaN power device; 3) the input end of the negative voltage generating circuit is a pulsating positive voltage square wave generated by a half-bridge driving IC, the output negative voltage is not constant negative voltage but pulsating negative voltage square wave, the negative voltage is generated only when the control circuit of a rear-stage comparator and a driven high-frequency GaN power device are needed, and the negative voltage is almost zero (small PN junction conduction voltage drop) when the negative voltage is not needed.
Drawings
FIG. 1 is a schematic diagram of the multi-level driving scheme for suppressing dv/dt crosstalk according to the present invention
FIG. 2 is a schematic diagram of an application of a half-bridge of a high frequency GaN device in an embodiment of the invention
FIG. 3 is a waveform diagram of the half-bridge circuit operating switch according to the embodiment of the present invention
FIGS. 4(a) - (b) are gate-source voltage waveforms of a conventional two-level driving circuit
FIG. 5 is a gate-source voltage waveform using an RC delay circuit as a control circuit
FIG. 6 is a gate-source voltage waveform of a high frequency GaN power device employing the invention
FIG. 7 shows the pulsating negative voltage waveform outputted from the negative voltage generating circuit of the present invention
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments, so that how to solve the technical problems in practical engineering and implement the corresponding technical objectives will be fully understood and implemented.
Also, in order to understand the present invention and to make the above objects, features and advantages of the present invention more apparent, the present invention will be described in detail in the following description with reference to the accompanying drawings and specific embodiments. However, the present invention can be implemented in many different ways and can be applied to any situation where dv/dt crosstalk is present, and is not limited to the specific embodiments listed herein. Therefore, it will be apparent to those skilled in the art that similar or corresponding modifications may be made without departing from the spirit of the invention and that the invention is not limited to the specific embodiments disclosed below.
The embodiment provides a half-bridge DC-DC circuit based on a high-frequency GaN power device, the half-bridge application topology of which is shown in FIG. 2 and comprises an upper bridge arm circuit and a lower bridge arm circuit.
In the lower bridge arm circuit, as shown in fig. 2, the multilevel driving circuit for suppressing dv/dt crosstalk of the high-frequency GaN power device according to the present invention includes a driving signal gating circuit, a negative voltage generating circuit, and a comparator control circuit.
Further, the driving signal gating circuit includes: the PMOS transistor M1 and the NMOS transistor M2, wherein the source electrode of the PMOS transistor M1 is connected with the output end of the half-bridge drive IC and is used for gating the positive square wave generated by the half-bridge drive IC; the source electrode of the NMOS tube M2 is connected with the output end of the negative voltage generating circuit and is used for gating the negative square wave generated by the negative voltage generating circuit, and the grid electrode of the PMOS tube M1 and the grid electrode of the NMOS tube M2 are grounded together and are used for serving as reference for gating positive and negative pulses.
The negative voltage generating circuit includes: a capacitor C1 and a Schottky diode D1, wherein one end of the capacitor C1 is connected with the output end of the half-bridge driving IC, the cathode of the Schottky diode D1 is connected with the circuit reference point, the other end of the capacitor C1 is connected with the anode of the Schottky diode D1 in series, and the middle node is used as the output end of the negative voltage generating circuit.
The comparator control circuit includes: the high-speed GaN power device comprises a high-speed comparator chip U1, an RC parallel circuit, current-limiting resistors R1 and R3, a Schottky diode D2 and a PMOS tube M3, wherein one end of the RC parallel circuit is connected with the non-inverting input end of the high-speed comparator chip U1, one ends of the current-limiting resistors R1 and R3 are respectively connected with the non-inverting input end and the inverting input end of the high-speed comparator chip U1, the grid electrode of the PMOS tube M3 is connected with the output end of the high-speed comparator chip U1, the drain electrode of the PMOS tube M3 is connected with the anode electrode of a Schottky diode D3, and the cathode electrode of the Schottky diode D3 is connected with the grid electrode of a driven high-frequency GaN power device.
The working principle of the multilevel driving circuit for suppressing dv/dt crosstalk of the high frequency GaN power device according to the present invention is explained below with reference to the half-bridge circuit shown in fig. 2 and the switching waveforms shown in fig. 3:
at stage t1, when the output of the lower half-bridge control signal LO of the half-bridge drive IC is high, the PMOS transistor M1 is turned on, the NMOS transistor M2 is turned off, the output of the node 1 is high level, the driving voltage drives the high-frequency GaN power device Q2 of the lower bridge arm of the half-bridge circuit, and at the same time, the capacitor C2 is charged through the current-limiting resistor R1 and the RC parallel circuits R2 and C2, at this time, the non-inverting input end of the high-speed comparator, that is, the node 3, is high level, the inverting input end, that is, the node 4, is a very small positive voltage (voltage drop of the schottky diode D1), the output of the high-speed comparator, that is, the node 5, is zero level, the PMOS transistor M3 is turned off, and the comparator control circuit does not function. At this time, the left side of the capacitor C1 is at a high level. When the output of the lower half-bridge control signal LO of the half-bridge driving IC is low, the right side of the capacitor C1, i.e. the node 2, is suddenly changed to a negative voltage, and the depth of the negative voltage can be adjusted by the capacitance value of the capacitor C1 (the absolute value of the negative voltage is in direct proportion to the capacitance value of the capacitor).
And in a stage t2, the PMOS tube M1 is turned off, the NMOS tube M2 is turned on, the voltage of the node 2 is gated, the node 1 is enabled to be negative, and the high-frequency GaN power device Q2 of the lower bridge arm of the half-bridge circuit is rapidly turned off. At this time, a fast boosting process from a low voltage to a bus voltage exists at the half-bridge switch node 6(sw), and the voltage change generates a large miller current on the miller capacitor Cgd _ L, and a forward crosstalk voltage is generated when the current flows through the gate-source capacitor Cgs _ L and the gate resistor Rg _ L. The crosstalk voltage increases with increasing switching frequency and bus voltage. The negative voltage turn-off mode can effectively inhibit the false conduction influence of the crosstalk voltage. At the same time, the capacitor C2 in this phase discharges through the resistors R1 and R2, the voltage at node 4 jumps from a very small positive voltage to a negative voltage, and the voltage at node 3 is always higher than the reference voltage at node 4 in this phase.
At stage t3, after the capacitor C2 discharges for a period of time, the voltage at node 3 is lower than the voltage at node 4, the voltage at node 5 rapidly changes from zero to a negative voltage at node 2, and the PMOS transistor M3 turns on. The anode voltage of the schottky diode D2 is 0V, the cathode voltage higher than D2 is a negative voltage, at this time, D2 is turned on, and the Q2 gate voltage is clamped from the negative voltage to the negative D2 turn-on voltage, so that the risk of reverse breakdown of the high-frequency GaN tube caused by reverse crosstalk voltage (caused by rapid voltage reduction change at the switch node 6 (sw)) can be effectively avoided. The rapid jump of the voltage at the node 5 greatly improves the response speed of the intermediate level clamp, and the time obtained by the simulation result is only 8ns, so that the method is suitable for the switching process of frequencies of 5MHz and above.
And in the stage t4, a bridge arm high-frequency GaN power device Q1 on the half-bridge circuit is turned off, a rapid voltage reduction process from bus voltage to low voltage exists at the switch node 6(sw), and a reverse crosstalk voltage is generated. And rapidly clamping the negative voltage to an intermediate level at a stage t3 before the reverse crosstalk voltage arrives, so that the risk of reverse breakdown of the high-frequency GaN power device caused by superposition of the negative voltage and the reverse crosstalk voltage can be effectively avoided.
And in the stage t5, the output of a lower half-bridge control signal LO of the half-bridge drive IC is high, the PMOS tube M1 is connected, the NMOS tube M2 is disconnected, the LO signal is gated, the node 1 is at a high level, and the drive voltage drives the lower bridge arm high-frequency GaN power device Q2 of the half-bridge circuit to enter the next switching period.
In order to show the suppression effect of introducing positive and negative crosstalk to dv/dt and the advantage of applying switching frequency of 5MHz and above in the application of the half-bridge DC-DC circuit of the high-frequency GaN power device, the present embodiment is based on ltspy simulation software, adopts a GS66502B 650V enhanced GaN device model provided by GaN Systems, and performs simulation of the half-bridge circuit, and compares the simulation with the conventional two-level driving and the driving using RC delay as a control circuit, respectively. In this embodiment, the dc bus voltage V1 is 48V, the input filter capacitor C _ i is 3.3uF, the output filter capacitor C _ o is 60nF, the power inductor L1 is 2.4uH, and the load resistor R _ load is 4.8 ohm. In the multi-level driving circuit, PWM signals are provided by an FPGA, an MCU, a DSP or a signal generator, a half-bridge driving IC is a special half-bridge driving chip LMG1210 for a high-frequency GaN power device provided by TI company, M1 in a driving signal gating circuit selects BSS84, and M2 is Si1555DL _ N; a capacitor C1 in the negative voltage generating circuit is 1.5nF, and a Schottky diode D1 selects BAT46WJ, 115; in the comparator control circuit, a MAX9203ESA + provided by a high-speed comparator for Maxim, an RC parallel circuit R2 is 1Kohm, a C2 is 15pF, a current-limiting resistor R1 is 120Kohm, a R3 is 30Kohm, a PMOS tube M3 selects Si9400DY, and a Schottky diode D2 selects BAT46WJ and 115.
The obtained simulation waveforms are shown in fig. 4, fig. 5, fig. 6 and fig. 7, respectively, and it can be known from comparing fig. 4 and fig. 6 that the positive and negative crosstalk pulse spikes of the conventional two-level driving reach 1.6V and-4.8V, respectively, and the forward pulse voltage of 1.6V already exceeds the lowest threshold voltage of the high-frequency GaN power device GS66502B by 1.1V. With the increase of the direct current bus voltage and the increase of the switching frequency, the dv/dt crosstalk problem of the high-frequency GaN power device is more serious, and the negative breakdown risk brought by the negative crosstalk voltage pulse is increased. When the driving circuit is adopted, the relative peak value of the positive crosstalk voltage pulse is reduced, the turn-off speed of the high-frequency GaN power device is increased, and the turn-off loss is reduced; the negative crosstalk voltage pulse is weakened, and the risk of reverse breakdown of the high-frequency GaN power device is effectively reduced. Comparing fig. 5 and fig. 6, it can be seen that the level clamping time of the control circuit using the RC delay circuit is greater than 80ns, and at the switching frequency of 5MHz, the response speed cannot clamp the negative voltage to zero level in time, so that the risk of reverse breakdown of the high-frequency GaN power device will increase. When the driving circuit is adopted, the response time of the low-delay high-speed comparator is quick, the clamping time of the intermediate level is only 8ns, and the clamping time is improved by at least 10 times compared with that of an RC delay circuit, which shows that the multi-level driving circuit can effectively work at the switching frequency of more than 10MHz, has the potential of fully exerting the high-frequency characteristic of a GaN power device, and simultaneously provides possibility for further reducing the volume of power electronic equipment and improving the power density. As can be seen from fig. 7, the negative voltage generating circuit according to the present invention outputs a negative voltage only when the pulsating positive voltage is zero and the high-frequency GaN power device is turned off, and outputs a zero voltage when the pulsating positive voltage is positive and the high-frequency GaN power device is turned on.
Claims (5)
1. A multilevel drive circuit to suppress dv/dt crosstalk for a high frequency GaN power device, the drive circuit comprising: the GaN power device comprises a driving signal gating circuit, a negative voltage generating circuit and a comparator control circuit, wherein the driving signal gating circuit is used for gating positive and negative square waves to drive the GaN power device, the negative voltage generating circuit is used for generating negative voltage to prevent misconduction of the GaN power device during turn-off, and the comparator control circuit is used for realizing intermediate level clamping to prevent reverse breakdown of the GaN power device at turn-on moment.
2. The multilevel driving circuit for suppressing dv/dt crosstalk of a high frequency GaN power device according to claim 1, wherein said driving signal gating circuit comprises: the PMOS transistor M1 and the NMOS transistor M2, wherein the source electrode of the PMOS transistor M1 is connected with the output end of the half-bridge drive IC and is used for gating the positive square wave generated by the half-bridge drive IC; the source electrode of the NMOS tube M2 is connected with the output end of the negative voltage generating circuit and is used for gating the negative square wave generated by the negative voltage generating circuit, and the grid electrode of the PMOS tube M1 and the grid electrode of the NMOS tube M2 are grounded together and are used for serving as reference for gating positive and negative pulses.
3. The multi-level driving circuit for suppressing dv/dt crosstalk in a high frequency GaN power device according to claim 1, wherein said negative voltage generating circuit comprises: a capacitor C1 and a Schottky diode D1, wherein one end of the capacitor C1 is connected with the output end of the half-bridge driving IC, the cathode of the Schottky diode D1 is connected with the circuit reference point, the other end of the capacitor C1 is connected with the anode of the Schottky diode D1 in series, and the middle node is used as the output end of the negative voltage generating circuit.
4. The multilevel driving circuit for suppressing dv/dt crosstalk of a high frequency GaN power device according to claim 1, wherein said comparator control circuit comprises: the high-frequency GaN power device comprises a high-speed comparator chip U1, an RC parallel circuit, current-limiting resistors R1 and R3, a Schottky diode D2 and a PMOS tube M3, wherein one end of the RC parallel circuit is connected with the non-inverting input end of the high-speed comparator chip U1, one ends of the current-limiting resistors R1 and R3 are respectively connected with the non-inverting input end and the inverting input end of the high-speed comparator chip U1, the grid of the PMOS tube M3 is connected with the output end of the high-speed comparator chip U1, the drain of the PMOS tube M3 is connected with the anode of the Schottky diode D3, and the cathode of the Schottky diode D3 is connected with the grid of the driven high-frequency GaN power device.
5. The multilevel driving circuit for suppressing dv/dt crosstalk of high frequency GaN power devices according to claim 1, wherein the topology and method of the multilevel driving circuit is applicable to wide bandgap semiconductor devices such as SiC MOSFETs and SiC IGBTs that have dv/dt crosstalk problems also in switching applications, and the specific circuit parameters are determined by the characteristics of the specific devices themselves.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117879326A (en) * | 2024-03-13 | 2024-04-12 | 合肥安赛思半导体有限公司 | GaN-FET parallel current sharing control circuit and method for multi-level driving signals |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117879326A (en) * | 2024-03-13 | 2024-04-12 | 合肥安赛思半导体有限公司 | GaN-FET parallel current sharing control circuit and method for multi-level driving signals |
| CN117879326B (en) * | 2024-03-13 | 2024-06-07 | 合肥安赛思半导体有限公司 | GaN-FET parallel current sharing control circuit and method for multi-level driving signals |
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