CN111740619A - CMOS (complementary Metal oxide semiconductor) rectifying circuit with synchronous rectifying function, circuit compensation method and rectifier - Google Patents

Abstract

The invention discloses a novel radio frequency-direct current (RF-DC) rectifier circuit, and provides a switch control type threshold compensation rectifier circuit structure, wherein the fixed voltage of an internal node of the rectifier circuit is adopted for threshold compensation, and simultaneously, the concept of synchronous rectification is adopted, the switch state is controlled by using an input sinusoidal voltage, the switch speed is ensured, and the power conversion efficiency is improved.

Description

CMOS (complementary Metal oxide semiconductor) rectifying circuit with synchronous rectifying function, circuit compensation method and rectifier

Technical Field

The invention relates to a CMOS (complementary metal oxide semiconductor) rectifying circuit with a synchronous rectifying function, belonging to the field of semiconductor devices.

Background

The radio frequency-direct current conversion refers to: the energy of the radio frequency signals is collected by utilizing the spatial wireless radio frequency signals and converted into a direct current power supply, so that the power is supplied to the self system of the microelectronic communication equipment with low power consumption.

Regardless of the mechanism and ultimate application of rf energy conduction, the rf power output by the energy converter when conducting rf circuit energy should be in the form of transmission by ac rf current or ac rf voltage. Since ac RF energy cannot be used directly, RF-DC rectifiers are required in order to provide a directly available RF DC power supply to all electronic RF circuit devices, as shown in fig. 1.

The induction coil or antenna captures the radio frequency signal and then transfers the coupled energy to a resonant tuned circuit to produce a high ac voltage which is then converted by a rectifier to a dc voltage for powering a signal processor downstream. It follows that a high efficiency rectifier is essential in extending the read distance and reducing the power requirements of the transmitter.

Conventional full-wave bridge rectifiers are most often designed and implemented using a combination of diodes and rectifying capacitors. The simplest diode rectifying circuit consists of a half-wave rectifying diode and a capacitor, and the full-wave bridge rectifier only realizes half-wave rectification by the diode, so that not only is the half period of an alternating voltage signal input by the diode greatly wasted, but also the ripple of the whole output alternating voltage is large. In order to effectively improve the output of diode half-wave rectification, a full-wave bridge rectifier is provided, the whole input period can be fully utilized, the power conversion efficiency is greatly improved compared with the half-wave rectification, and the half-wave rectification circuit can reduce ripples so that the waveform of output voltage is smoother. However, the diode needs to consume a conduction voltage drop of 0.7V to 1V, and the rectifying operation cannot be performed normally at all in the case of inputting a low-power ac signal. Therefore, a schottky diode with low forward conduction voltage drop occurs, the voltage drop is only 0.4V, and the PCE of the circuit is greatly improved. However, the schottky diode is expensive and cannot be applied to a large scale integrated circuit, and thus its use is limited. Thereafter, diode-connected MOS transistors replace conventional diodes and schottky diodes, and CMOS rectifying structures are widely used.

The disadvantages of diode rectification are obvious that the size is too large to be integrated, the voltage drop of each diode is 0.7V, and the voltage loss applied to the circuit is immeasurable. The application of the conventional diode rectifier is greatly limited. The MOS tube has a small area relatively, and is convenient to integrate, so that the MOS tube can replace a traditional diode to perform rectification to a certain extent. Rectification blocks can be divided into two broad categories, voltage multiplying and full bridge rectifiers, all of which share common problems. First, a low rf input voltage results in low voltage conversion efficiency and thus low output voltage. Because the low input signal is equal to the threshold voltage, it is just enough to compensate for the forward voltage drop required by the MOS transistor. Or in the worst case below the threshold voltage. Second, reverse leakage is introduced during the charge transfer state (ON-OFF) of the diode-connected transistor. The voltage drop and leakage current of the voltage doubler rectifier have a large impact on the power transfer efficiency (PCE) of the rectifier. Therefore, circuit improvement on the rectifying module is needed in an actual circuit.

Disclosure of Invention

The technical scheme is that the CMOS rectifying circuit with the synchronous rectifying function comprises a power supply VRF, at least two resistors, transistors MP0, MN0, a capacitor C and switches S1 and S2, and is characterized in that the power supply VRF sends out a grid control signal, the grid control signal is transmitted to at least two switching transistors, and the switching transistors are controlled to be switched on and switched off, so that the synchronous control function that the whole rectifying circuit follows input signals is achieved.

Further, a compensation voltage V is introduced between the grid electrode and the drain electrode of the switch transistor_CAnd the grid source is connected into a cross-coupled structure.

Further, a voltage-doubling rectifying circuit is adopted, at least two diodes are arranged in the voltage-doubling rectifying circuit, and each diode corresponds to one self-threshold adjusting module.

Further, the switch transistor comprises MP1, MN2, and the self-threshold adjusting module comprises: a first module: by adjusting the resistance R₁And parameters of MP1, generating voltage V_G1For biasing the transistor MP 0; and a second module: by adjusting the resistance R₂Parameters of transistor MN2, generation and V_outProportional fixed voltage V_G2。

Further, the MP1 and MP0 are the same size.

Further, the voltage V is fixed_G2Tending to the threshold voltage V of the NMOS transistor_thnApplied to the gate of transistor MN 0.

Another object of the present invention is to provide a compensation method of a threshold compensation circuit, which applies the rectifier circuit of any one of claims 1 to 6, comprising the following processes: first, when the input source is in the negative half-cycle, MN0 conducts and couples capacitor C₁Charging, and carrying out threshold compensation on MN0 to reduce voltage loss; the control circuit, now giving the gate bias to MN0, is turned on and switch S2 is closed. Meanwhile, when the input source is in a negative half period, the MP0 tube is not conducted, the branch giving the MP0 bias is controlled to be closed, and the reverse leakage current possibly existing in the MP0 tube at the moment is reduced, namely S1 is disconnected; thereafter, the input signal transitions to a positive half cycle, MP0 conducts, and transfers charge to C₂，V_CThe capacitor maintains the characteristic of voltage and jumps to obtain high voltage at the output end when switching, so that the threshold value of MP0 is compensated, S1 is closed, and S2 is opened.

Further, the gate voltage is the same phase as the input signal.

Further, the sources of MN1 and MP2 are connected to two nodes, and the current flow is opposite to the normal MOS flow when the two nodes are turned on.

Another object of the present invention is to provide a rectifier, which employs the above-mentioned rectifying circuit and compensation method of threshold compensation circuit, and uses the transistor MP0 as the upper diode and the transistor MN0 as the lower diode; selecting an NMOS transistor as S1 and a PMOS transistor as S2; compensation voltage V_G1And V_G2Outputting in a pulse form; under the condition of meeting the requirement of synchronously driving the switching tubes MN1 and MP2, the gate of MN1 is connected to V_RFWhile the gate of MP2 is set at V_CDriving; connecting the substrate of PMOS to a voltage higher than zero to adjust to reduce V_THThe substrate of the NMOS is connected to the lowest voltage, i.e., GND.

The invention has the following beneficial effects:

the improved concept of the present invention includes two parts, firstly, in order to effectively use the available rf input power, the rectifier needs to have a low turn-on voltage to minimize the area where all the input power is wasted, and secondly, to limit the reverse leakage of these devices to reduce the power conversion efficiency after the rectifier is turned on.

As in the invention of fig. 4, MN1 and MP2 are two switching transistors whose gate control signals are from power supply VRF. When the VRF signal changes, MN1 and MP2 automatically turn on or off along with the change of the VRF signal. Therefore, the synchronous control function of the whole rectifying circuit along with the input signal is realized.

Drawings

FIG. 1 is a schematic diagram of a wireless power supply system;

FIG. 2 is an external threshold compensation technique in which a voltage is applied between the gates and sources of transistors, the gates and sources being connected in a cross-coupled configuration;

FIG. 3 is a schematic diagram of a switch modification;

FIG. 4 is a schematic diagram of a switch-controlled threshold voltage compensation configuration;

FIG. 5 is a graph of the prediction of the bias voltage waveform of the MN0 transistor;

FIG. 6 is output voltage prediction;

FIG. 7 is a diagram for expressing the output small ripple voltage of the synchronous rectification circuit, which is 0.26V higher than the output peak value before adding the switch;

FIG. 8 is a diagram for expressing the gate bias voltage V of MN0_G2[V_GS(MN0)]Controls MN0 turn-on and turn-off cycles;

FIG. 9 is a diagram for expressing the compensation voltage V_GS(MP0)Controls the on and off cycles of MP 0;

fig. 10 is a diagram showing reverse leakage current of the switching control type rectifier circuit.

Detailed Description

Example 1

Aiming at the problem that a diode-connected MOS tube has high threshold voltage and large power consumption, a unit structure shown in figure 2 is designed, namely a CMOS rectification circuit with a synchronous rectification function.

Of rectifying circuitsThe essence of the external threshold voltage compensation technique is to introduce a compensation voltage V between the gate and drain of the transistor_C. The principle is illustrated by NMOS: gate source voltage V of NMOS_gsDue to V_cnThe presence of (2) becomes more positive and the forward conduction current of the NMOS is greater.

Example 2

The external threshold compensation structure voltage provides precision, but the external input voltage makes the circuit structure troublesome, and the external input voltage causes power consumption to become large. The traditional self-threshold elimination rectifier intercepts voltage in the structure, and applies constant voltage to the grid electrodes of two active tubes to achieve the purpose of threshold compensation, and the mode can cause inevitable reverse leakage current when the input voltage is opposite in phase. The bridge rectifier provides compensation voltage for the MOS tube through dynamic bias, the problem of reverse leakage current is successfully solved, but the dynamic compensation voltage is not accurate enough and cannot be well compensated.

The present embodiment combines dynamic threshold control and self-threshold cancellation circuits to provide a switch-controlled threshold compensation rectifier. The polarity of the compensation voltage is periodically changed along with the input electric signal without considering the need of external voltage so as to ensure that the MOS tube is switched off more thoroughly, and the threshold compensation voltage is kept constant so as to achieve the dual purposes of inhibiting reverse leakage current and accurately compensating the threshold. As shown in fig. 3.

Since there are two diodes in the double voltage rectifier, it requires two self-threshold adjustment modules. Module one is obtained by adjusting R₁And MP1 parameters, generating a voltage V_G1For biasing the transistor MP 0. Selecting the MP1 to be the same size as the MP 0; similarly, module two is controlled by adjusting resistor R₂The parameters of the transistor MN2 can be generated_outProportional fixed voltage V_G2The voltage is similar to the threshold voltage V of the NMOS tube_thnApplied to the gate of transistor MN 0.

Considering a switching system added to the circuit, two switches are required due to the two self-threshold compensation modules. In order to synchronize the on and off states of the two diode-connected MOS transistors with the operation of the switching system, the switching transistors are driven by applying an input signal as a control voltage, rather than being biased with a constant voltage, to thereby control the states thereof more effectively, thereby effectively reducing reverse leakage current.

The working principle of the threshold compensation circuit after the switch is added is as follows: first, when the input source is in the negative half cycle, MN0 is required to be conductive and couple C₁Charging, MN0 needs to be threshold compensated to reduce voltage loss. The control circuit, which now gives the gate bias to MN0, should be on and S2 closed. Meanwhile, the MP0 tube should not be conducted when the input source is in the negative half-cycle, and in order to reduce the reverse leakage current that may exist in the MP0 tube at this time, the branch for biasing the MP0 is controlled to be closed, that is, the S1 is turned off. Thereafter, the input signal transitions to a positive half cycle, MP0 should be on, and charge is transferred to C₂，V_CDue to the characteristic of the capacitor maintaining voltage, when the capacitor jumps to obtain high voltage at the output terminal, the threshold compensation of MP0 is needed, S1 is closed, and S2 is opened.

Selecting an input signal V_RFAnd V_CTo control the gate voltage of the switching transistor, directly connected means that the gate voltage is in phase with the input signal, from which so-called synchronous rectification is derived. Synchronous rectification can reduce the power loss of devices to a great extent, and effectively prevents the cross conduction of rectifier tubes. The source of MN1, which is used for synchronous rectification, is connected to node A, and the source of MP2 is connected to node B, and the current flows in the opposite direction to the normal MOS current when both are conducted. The on-time for use in the circuit cannot be too long.

The specific connection circuit is shown in fig. 4. To reduce the input parasitic capacitance, the rectifier uses transistor MP0 as the upper diode and transistor MN0 as the lower diode. In addition, the NMOS transistor is selected as S1, and the PMOS transistor is selected as S2, so that a large output voltage can be ensured.

Due to the existence of the switch tubes MP1 and MN2, the compensation voltage V provided for the rectifier tube_G1And V_G2Will be the output form of the pulse. The two pulsed voltages should have waveforms similar to fig. 5.

In addition, the speed of the switching transistor is not fast enoughAt the edges of the rise and fall times of the pulse signal, non-negligible reverse leakage currents occur. To limit reverse leakage current, it is generally desirable to reduce V_G1And V_G2. However, R_onAnd V_GSAnd (4) correlating. The value of the output voltage depends on the on-resistance R of MN0 and MP0_on，R_onThe larger, V_outThe smaller. Therefore, M1 and M2 are required to be of a suitably large size, V_GSAnd is also suitably large. There is a need to solve the problem of the contradiction between the reverse leakage current and the output voltage while improving the fall time of MN0 and MP0 pulse signals to increase the PCE without affecting the output voltage.

When the MOS transistor is used as a switching transistor in a circuit, it is usually necessary to drive the PMOS transistor with a relatively high voltage and drive the NMOS transistor with a low voltage. Therefore, in order to meet this requirement, the gate of MN1 is connected to V in the case of satisfying the synchronous driving of the switching tubes MN1 and MP2_RFWhile the gate of MP2 is set at V_CAnd (5) driving.

Secondly, the influence of the body effect on the threshold voltage, V_THIs shown as V_TH0Fermi level phi_FAnd source voltage V_SBA function of where V_TH0、Φ_FThe value of gamma depends on the process, only V_SBCan be lowered by the circuit connection. For PMOS, the substrate is connected to a voltage higher than zero to adjust to lower V_THHere, V is selected_OUT. Similarly, for an NMOS, its substrate needs to be connected to the lowest voltage, namely GND.

V_RFIn the first period of the signal just starting, V_CThe value of (A) has not passed through the voltage doubling effect of the capacitor, and the value of (B) is output

V_C＝V_RF-V_DS(MN0)(1)

V_RFThe peak value is reached and then the voltage is reduced, but the output voltage is not changed because the voltage is clamped by the capacitor. With V_RFThe voltage decreases in the positive half period, and V is set after MP0 is turned on and during the negative period of the input signal_CJumping:

V_C＝2·V_RF-V_DS(MN0)(2)

a stable voltage output of

V_OUT＝2·V_RF-V_DS(MN0)-V_DS(MP0)(3)

The output voltage waveform of the synchronous rectification circuit should be similar to that of the chapter iii self-threshold rectification circuit, and is not a sine wave. Since the switch is turned off and on in time, the amount of charge delivered to the output terminal increases, and the peak value of the output voltage is inevitably higher than the latter. The output voltage waveform is estimated, see fig. 6.

The output voltage of the voltage doubler rectifier is first simulated. As shown in fig. 7, when the input signal amplitude is 1V, the final output terminal can obtain a dc voltage of 1.47V at most. The voltage ripple is only 163mV, which is greatly reduced compared with the traditional circuit.

The compensation voltage of the switching control trimming circuit is also a parameter that needs to be of great concern. Input signal V_CFor controlling the output V_G2Pulse on at V_CWhen changing to the minimum value, the bias voltage V_G2A peak of 0.486V was reached. MN0 can also present a better off state during the negative half cycle of the input signal, V_G2Only 0.15V, as shown in fig. 8. V_G2MN0 was controlled to be 19.7ns from off to on and 53.5ns from on to off. Due to the presence of the switch, the bias voltage is output in pulses rather than as a constant value.

Input signal V_RFFor controlling the output V_G1Pulse voltage, positive period V of input signal_RFWhen the input peak value is reached, the grid source voltage V of the PMOS pipe MP0_GS0This is the maximum value that the MP0 threshold compensation voltage can reach, as shown in fig. 9, at-0.57V. V_GS(MP0)The time from off to on for control MP0 is approximately 52ns, and the on to off transition time is 21.7 ns.

V_GS(MP0)＝V_G1-V_CWhen it is-0.496V, corresponding to V_G1＝V_D(MN1)＝949.5mV，V_RF＝812.4mV，

V_S(MN1)281.3 mV. When V is_D(MN1)＝V_G1When 949.5mV is reached and the equivalent charge-discharge capacitance is 1.4pF, the switching time t is obtained10ns, and has a fast switching speed. The switching speed of the switching transistor 10ns is much smaller than the switching period of the rectifying device, and it can be known that the reverse leakage current of the transistor can be reduced inevitably by the fast control of the switching control type threshold compensation rectifying circuit, and a simulation chart is shown in fig. 10.

The reverse leakage current peak value of MN0 is only 10.57 muA, the reverse leakage current of MP0 is only 7.087 muA, the value is greatly reduced compared with the leakage current of the traditional self-threshold compensation rectifier, and the conduction loss of the circuit is reduced.

Simulating an alternating current working point, and visually obtaining the power consumed by each device, wherein the load resistor R₃The power consumed is the output power of the rectifier. Specific power values are shown in table 1.

When the amplitude of the input voltage is 1V and the resistance of the load resistor is 80K omega, the output power is 26.22 muW, the total consumed power of the circuit is 47.63 muW, and the power transmission efficiency is

Compared with the traditional threshold value elimination circuit, the conversion efficiency is greatly improved.

TABLE 1 Power consumed by the respective devices

It can be seen that the main content of the present invention is to provide a voltage threshold elimination concept based on the voltage of the external threshold compensation structure, and by using the conventional self-threshold elimination rectifier to intercept the voltage inside the structure and apply a constant voltage to the gates of the two active transistors to achieve the purpose of threshold compensation, and solve the problem of unavoidable reverse leakage current caused by the manner when the input voltage is relatively inverted. In general, the threshold compensation circuit of the switch control combines the dynamic threshold control and the self-threshold elimination circuit, has higher output voltage and low reverse leakage current, has the power conversion efficiency of 55 percent, and has good rectification performance.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A rectification circuit comprises a power supply VRF, at least two resistors, transistors MP0, MN0, a capacitor C and switches S1 and S2, and is characterized in that the power supply VRF sends out a grid control signal, the grid control signal is transmitted to the at least two switch transistors, and the switch transistors are controlled to be opened and closed, so that the function of synchronously controlling the whole rectification circuit to follow an input signal is achieved.

2. A rectifier circuit according to claim 1, wherein a compensation voltage V is introduced between the gate and drain of the switching transistor_CAnd the grid source is connected into a cross-coupled structure.

3. The rectifier circuit according to claim 1, wherein a voltage-doubling rectifying circuit is adopted, and at least two diodes are arranged in the voltage-doubling rectifying circuit, and each diode corresponds to one self-threshold adjusting module.

4. The rectifier circuit according to claim 3, wherein the switch transistor comprises MP1 and MN2, and the self-threshold adjustment module comprises:

a first module: by adjusting the resistance R₁And parameters of MP1, generating voltage V_G1For biasing the transistor MP 0;

and a second module: by adjusting the resistance R₂Parameters of transistor MN2, generation and V_outProportional fixed voltage V_G2。

5. A rectifier circuit according to claim 4, wherein said MP1 and MP0 are the same size.

6. A rectifying circuit according to claim 4Characterized by a fixed voltage V_G2Tending to the threshold voltage V of the NMOS transistor_thnApplied to the gate of transistor MN 0.

7. A compensation method of a threshold compensation circuit, characterized in that the rectifier circuit of any one of claims 1-6 is applied, comprising the following processes: first, when the input source is in the negative half-cycle, MN0 conducts and couples capacitor C₁Charging, and carrying out threshold compensation on MN0 to reduce voltage loss; the control circuit, now giving the gate bias to MN0, is turned on and switch S2 is closed. Meanwhile, when the input source is in a negative half period, the MP0 tube is not conducted, the branch giving the MP0 bias is controlled to be closed, and the reverse leakage current possibly existing in the MP0 tube at the moment is reduced, namely S1 is disconnected; thereafter, the input signal transitions to a positive half cycle, MP0 conducts, and transfers charge to C₂，V_CThe capacitor maintains the characteristic of voltage and jumps to obtain high voltage at the output end when switching, so that the threshold value of MP0 is compensated, S1 is closed, and S2 is opened.

8. The method of claim 7, wherein the gate voltage is the same as the phase of the input signal.

9. The method as claimed in claim 7, wherein the sources of MN1 and MP2 are connected to two nodes, and the two nodes conduct current in a direction opposite to the normal MOS direction.

10. A rectifier, wherein the rectifier circuit of any one of claims 1 to 6, the compensation method of the threshold compensation circuit of any one of claims 7 to 9, and the transistor MP0 are used as the upper diode, and the transistor MN0 is used as the lower diode; selecting an NMOS transistor as S1 and a PMOS transistor as S2; compensation voltage V_G1And V_G2Outputting in a pulse form; under the condition of meeting the requirement of synchronously driving the switching tubes MN1 and MP2, the gate of MN1 is connected to V_RFWhile the gate of MP2 is set at V_CDriving; connecting the substrate of PMOS to a voltage higher than zero to adjust to reduce V_THThe substrate of the NMOS is connected to the lowest voltage, i.e., GND.

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