CN117872903A - Slope control circuit based on LIN bus signal control and control method thereof - Google Patents
Slope control circuit based on LIN bus signal control and control method thereof Download PDFInfo
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- CN117872903A CN117872903A CN202410067400.8A CN202410067400A CN117872903A CN 117872903 A CN117872903 A CN 117872903A CN 202410067400 A CN202410067400 A CN 202410067400A CN 117872903 A CN117872903 A CN 117872903A
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Abstract
The invention relates to a slope control circuit and a slope control method based on LIN bus signal control, and belongs to the technical field of LIN bus signal control. The slope control circuit based on LIN bus signal control comprises a voltage acquisition circuit, a feedback control circuit and a load circuit; the load circuit is connected with the input end of the voltage acquisition circuit through an LIN pin; the output end of the voltage acquisition circuit is connected with the input end of the feedback control circuit, the output end of the feedback control circuit is connected with the LIN pin, and the voltage acquisition circuit comprises a sample hold circuit S/H; according to the invention, through the sampling and holding circuit S/H and the cooperation of the voltage acquisition capacitor, the voltage change of the voltage on the LIN bus in the acquisition period can be taken out, and accurate response can be made based on the LIN signal change outside the LIN chip; the closed-loop feedback control circuit is used, so that the rising edge and the falling edge of the LIN bus voltage can be kept constant; in addition, the circuit of the invention is simple and has low cost.
Description
Technical Field
The invention belongs to the technical field of LIN bus signal control, and particularly relates to a slope control circuit based on LIN bus signal control and a control method thereof.
Background
The LIN (Local Interconnect Network local connection network) bus is a low cost serial communication protocol based on UART/SCI (Universal Asynchronous Receiver-Transmitter/SerialCommunication Interface universal asynchronous receiver/serial communication interface). Compared with a CAN bus, the LIN bus protocol is simpler, the requirements on a singlechip are not high, and a basic window CAN be realized. As an auxiliary bus of the CAN bus, the LIN bus is widely used in the vehicle body control field such as vehicle doors, vehicle windows, vehicle lamps, central control locks and the like.
Typically, a LIN chip will be mounted on the LIN bus for monitoring LIN bus signal changes. The LIN pin port of the LIN chip draws current from the LIN bus to produce a variation in the LIN bus voltage.
Most of LIN bus voltage control circuits in the market at present are designed based on the open loop control principle, which is essentially predictive control, and cannot respond accurately to the grid voltage of an NMOS tube based on LIN signal change outside the LIN chip, so that unstable rates of the rising edge and the falling edge of the LIN bus voltage can occur.
Disclosure of Invention
The invention aims to provide a slope control circuit and a slope control method based on LIN bus signal control, which can accurately respond based on LIN signal change outside a LIN chip and can keep the rising edge and the falling edge of LIN bus voltage constant.
In order to achieve the above purpose, the slope control circuit based on LIN bus signal control of the invention comprises a voltage acquisition circuit, a feedback control circuit and a load circuit, wherein the load circuit is connected with the input end of the voltage acquisition circuit through an LIN pin, and the voltage acquisition circuit is used for acquiring the voltage when the LIN bus voltage drops or the LIN bus voltage rises; the output end of the voltage acquisition circuit is connected with the input end of the feedback control circuit, and the output end of the feedback control circuit is connected with the LIN pin; the feedback control circuit is used to control the LIN bus voltage to maintain a constant rate as it decreases or increases.
As a further scheme of the invention: when the LIN bus voltage drops, the voltage acquisition circuit comprises a sampling and holding circuit S/HI, a sampling and holding circuit S/HII, a voltage follower VFI and a voltage follower VFII; the positive input end of the voltage follower VFI is connected with one end of the sampling and holding circuit S/HI, and the other end of the sampling and holding circuit S/HI is connected with the LIN pin; the sampling and holding circuit S/HI is connected with the sampling and holding circuit S/HII in parallel, and the output end of the sampling and holding circuit S/HII is connected with the positive input end of the voltage follower VFII; output end of voltage follower VFI and switch S 1 Is connected with one end of the connecting rod; output end of voltage follower VFII and switch S 2 Is connected with one end of the connecting rod; switch S 1 The other end of (C) is respectively connected with the voltage acquisition capacitor C 1 Upper pole plate of (S) switch (S) 4 Is connected with one end of the connecting rod; voltage acquisition capacitor C 1 The lower polar plate of (C) is respectively connected with a switch S 3 One end of switch S 2 Is connected to the other end of switch S 3 The other end of the first electrode is grounded; switch S 4 The other end of the (B) is connected with the positive input end of an operational amplifier OPAI in the feedback control circuit;
the feedback control circuit comprises an operational amplifier OPAI, wherein the negative input end of the operational amplifier OPAI is connected with a reference voltage Ref_voltagei, and the output end of the operational amplifier OPAI and a variable current source I 1 Connected to a variable current source I 1 Respectively with the capacitor C 2 Upper plate of (C), micro current source I 2 Is connected with the output end of the capacitor C 2 The lower polar plate of (2) is grounded, and the micro current source I 2 Through resistor R 1 Respectively with the capacitor C 3 Upper pole of (2)The grid of the NMOS tube MI is connected with the capacitor C 3 The lower electrode plate of the NMOS tube MI is grounded, and the source electrode of the NMOS tube MI is grounded.
As a further scheme of the invention: the gate voltage of the NMOS tube MI is GND, and the LIN bus voltage is highest.
As a further scheme of the invention: variable current source I 1 Micro current source I 2 Is a very small current source, ensures the capacitance C 3 The upper voltage is always rising.
As a further scheme of the invention: when the LIN bus voltage rises, the voltage acquisition circuit comprises a sampling and holding circuit S/HIII, a sampling and holding circuit S/HIV, a voltage follower VFIII and a voltage follower VFIV; the positive input end of the voltage follower VFIII is connected with one end of the sampling and holding circuit S/HIII, and the other end of the sampling and holding circuit S/HIII is connected with the LIN pin; the sampling and holding circuit S/HIII is connected with the sampling and holding circuit S/HIV in parallel, and the output end of the sampling and holding circuit S/HIV is connected with the positive input end of the voltage follower VFIV; output end of voltage follower VFIII and switch S 5 Is connected with one end of the connecting rod; output end of voltage follower VFIV and switch S 6 Is connected with one end of the connecting rod; switch S 5 The other end of (C) is respectively connected with the voltage acquisition capacitor C 4 Upper pole plate of (S) switch (S) 7 Is connected with one end of the connecting rod; voltage acquisition capacitor C 4 The lower polar plate of (C) is respectively connected with a switch S 8 One end of switch S 6 Is connected to the other end of switch S 8 The other end of the first electrode is grounded; switch S 7 The other end of the first filter is connected with the positive input end of an operational amplifier OPAII in the feedback control circuit;
the feedback control circuit comprises an operational amplifier OPAII, an output end of the operational amplifier OPAII and a variable current source I 3 Connected to a variable current source I 3 And micro current source I 4 Capacitance C 5 Parallel series resistor R 2 Resistance R 2 One way through the other end of the capacitor C 6 One path of the NMOS transistor MII is grounded, the source electrode of the NMOS transistor MII is grounded, and the drain electrode of the NMOS transistor MII is connected between the LIN pin and the voltage acquisition circuit; capacitor C 5 The lower electrode plate of the capacitor is grounded.
As a further scheme of the invention: the gate voltage of the NMOS transistor MII is VDD, and the LIN bus voltage is the lowest.
As a further scheme of the invention: variable current source I 3 Micro current source I 4 Is a very small current source, ensures the capacitance C 6 The upper voltage is pulled down all the time.
As a further scheme of the invention: the load circuit comprises a load resistor R load Load resistor R load And load capacitance C load After being connected in series, the LIN pin is connected with a load resistor R load And load capacitance C load Between them.
A slope control method based on LIN bus signal control comprises the following steps:
step1: the voltage acquisition circuit respectively acquires the voltages on the upper polar plate and the lower polar plate through closing and closing control voltage acquisition capacitors of different switches, so that the voltage difference of LIN bus voltage is obtained;
step2: the feedback control circuit compares the voltage difference with a reference voltage, and controls the pull-down current capacity of the NMOS tube according to a comparison result;
step3: and repeating Step1 and Step2 for a plurality of times, wherein the beat is determined by an on-chip clock, the acquisition times are according to the frequency of the LIN on-chip clock, and if the frequency of the clock is high, more acquisition can be realized.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, through the sample hold circuit S/H and the voltage acquisition capacitor, the voltage change of the voltage on the LIN bus in the acquisition period can be taken out, accurate response can be made based on the LIN signal change outside the LIN chip, and if the acquisition period is shorter, the LIN bus voltage can be approximately considered to be subjected to differential operation; the closed-loop feedback control circuit is used, so that the rising edge and the falling edge of the LIN bus voltage can be kept constant; in addition, the circuit of the invention is simple and has low cost.
Drawings
Fig. 1 is a block diagram of a slope control circuit based on LIN bus signal control in accordance with the present invention.
Fig. 2 is a circuit diagram of the present invention when the LIN bus voltage drops.
Fig. 3 is a circuit diagram of the present invention when the LIN bus voltage rises.
Fig. 4 is a flow chart of a slope control method based on LIN bus signal control of the present invention.
In the figure: 1. the device comprises a voltage acquisition circuit, a load circuit, a feedback control circuit and a feedback control circuit.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, a slope control circuit based on LIN bus signal control includes a voltage acquisition circuit 1, a feedback control circuit 2, and a load circuit 3, where the load circuit 2 is connected to the voltage acquisition circuit 1 through a LIN pin, and the voltage acquisition circuit 1 is used to acquire a voltage when a LIN bus falls or a LIN bus voltage rises; the output end of the voltage acquisition circuit 1 is connected with the input end of the feedback control circuit 2, and the output end of the feedback control circuit 2 is connected with the LIN pin; the feedback control circuit 2 is used to control the LIN bus voltage to maintain a constant rate as it drops or rises.
As shown in fig. 2, the default precondition is that the LIN bus voltage is pulled to the highest last time, and the gate voltage of the NMOS tube MI is correspondingly pulled to the lowest, i.e., GND. If the LIN bus voltage is reduced on this basis, the gate voltage of the NMOS transistor MI needs to be gradually pulled up.
The voltage acquisition circuit 1 comprises a sample-and-hold circuit S/HI, a sample-and-hold circuit S/HII, a voltage follower VFI and a voltage follower VFII; the positive input end of the voltage follower VFI is connected with one end of the sampling and holding circuit S/HI, and the other end of the sampling and holding circuit S/HI is connected with the LIN pin; the sampling and holding circuit S/HI is connected with the sampling and holding circuit S/HII in parallel, and the output end of the sampling and holding circuit S/HII is connected with the positive input end of the voltage follower VFII; output end of voltage follower VFI and switch S 1 Is connected with one end of the connecting rod; output end of voltage follower VFII and switch S 2 Is connected with one end of the connecting rod; switch S 1 The other end of (C) is respectively connected with the voltage acquisition capacitor C 1 Upper pole plate of (S) switch (S) 4 Is connected with one end of the connecting rod; voltage acquisition capacitor C 1 Lower plate of (2)Respectively with switch S 3 One end of switch S 2 Is connected to the other end of switch S 3 The other end of the first electrode is grounded; switch S 4 The other end of the (B) is connected with the positive input end of an operational amplifier OPAI in the feedback control circuit;
the feedback control circuit 3 comprises an operational amplifier OPAI, the negative input end of which is connected with a reference voltage Ref_voltagei, the output end of which is connected with a variable current source I 1 Connected to a variable current source I 1 Respectively with the capacitor C 2 Upper plate of (C), micro current source I 2 Is connected with the output end of the capacitor C 2 The lower polar plate of (2) is grounded, and the micro current source I 2 Through resistor R 1 Respectively with the capacitor C 3 The upper polar plate of the NMOS tube MI is connected with the grid electrode of the NMOS tube MI, and the capacitor C 3 The lower electrode plate of the NMOS tube MI is grounded, and the source electrode of the NMOS tube MI is grounded.
The control method for the LIN bus voltage drop comprises the following steps:
digital logic control switch S 1 Switch S 2 Switch S 3 Switch S 4 Is provided for the opening and closing of the door.
Step1: switch S 1 、S 3 Closing, switch S 2 、S 4 Disconnection, voltage acquisition capacitor C 1 Collecting LIN bus voltage U by upper polar plate of (C) 1 ；
Step2: switch S 1 、S 2 Closing, switch S 3 、S 4 Disconnection, voltage acquisition capacitor C 1 Collecting LIN bus voltage U by lower polar plate 2 ；
Step3: switch S 1 、S 2 Disconnection, S 3 、S 4 Closing. Voltage acquisition capacitor C 1 The upper polar plate is LIN bus voltage difference delta U acquired twice 1 Wherein DeltaU 1 ＝U 1 -U 2 The voltage difference DeltaU 1 Is read in.
Step4: voltage difference DeltaU 1 Compared with reference voltage Ref_voltage I, if the voltage is higher than reference voltage Ref_voltage I, the variable current source I 1 Is reduced; if it is lower than the reference voltage Ref_voltagei, it canCurrent source I 1 The current of the NMOS tube MI pull-down tube is increased, and the pull-down current capability of the NMOS tube MI pull-down tube is controlled.
By such feedback control, a constant rate of the LIN bus drop voltage is achieved.
In the LIN bus voltage dropping process, the process is repeated for a plurality of times, the beat is given by an on-chip clock, the acquisition times are based on the clock frequency in the LIN chip, and if the clock frequency is high, more acquisition can be realized.
Variable current source I in FIG. 2 1 Micro current source I 2 Is a very small current source, ensures the capacitance C 3 The upper voltage is always rising.
As shown in fig. 3, the default condition of the circuit diagram when the LIN bus voltage rises is that the gate voltage of the NMOS transistor MII is VDD, VDD is the highest on-chip voltage, and the LIN bus voltage is the lowest.
The voltage acquisition circuit 1 comprises a sample and hold circuit S/HIII, a sample and hold circuit S/HIV, a voltage follower VFIII and a voltage follower VFIV; the positive input end of the voltage follower VFIII is connected with one end of the sampling and holding circuit S/HIII, and the other end of the sampling and holding circuit S/HIII is connected with the LIN pin; the sampling and holding circuit S/HIII is connected with the sampling and holding circuit S/HIV in parallel, and the output end of the sampling and holding circuit S/HIV is connected with the positive input end of the voltage follower VFIV; output end of voltage follower VFIII and switch S 5 Is connected with one end of the connecting rod; output end of voltage follower VFIV and switch S 6 Is connected with one end of the connecting rod; switch S 5 The other end of (C) is respectively connected with the voltage acquisition capacitor C 4 Upper pole plate of (S) switch (S) 7 Is connected with one end of the connecting rod; voltage acquisition capacitor C 4 The lower polar plate of (C) is respectively connected with a switch S 8 One end of switch S 6 Is connected to the other end of switch S 8 The other end of the first electrode is grounded; switch S 7 The other end of the (a) is connected with the positive input end of an operational amplifier OPAII in the feedback control circuit 3;
the feedback control circuit 3 includes an operational amplifier opai, an output terminal of the operational amplifier opai and a variable current source I 3 Connected to a variable current source I 3 And micro current source I 4 Capacitance C 5 Parallel series resistor R 2 Resistance R 2 One way through the other end of the capacitor C 6 One path of the NMOS transistor MII is grounded, the source electrode of the NMOS transistor MII is grounded, and the drain electrode of the NMOS transistor MII is connected between the LIN pin and the voltage acquisition circuit; capacitor C 5 The lower polar plate of the capacitor is grounded;
the load circuit 2 is located outside the LIN chip and, as shown in fig. 2 or 3, comprises a load resistor R load Load resistor R load And load capacitance C load After being connected in series, the LIN pin is connected with a load resistor R load And load capacitance C load Between them.
When the LIN bus voltage rises, the default condition is that the grid electrode of the NMOS tube MII is up to VDD, and VDD is the highest voltage in the chip, and the control method comprises the following steps:
digital logic control switch S 5 、S 6 、S 7 、S 8 Is provided for the opening and closing of the door.
Step1: switch S 6 Closing, switch S 5 、S 7 、S 8 Disconnection, voltage acquisition capacitor C 4 Collecting LIN bus voltage u by lower polar plate 1 ；
Step2: switch S 5 、S 6 Closing, switch S 7 、S 8 Disconnection, voltage acquisition capacitor C 4 Collecting LIN bus voltage u by upper polar plate of (C) 2 ；
Step3: switch S 7 、S 8 Closing, switch S 5 、S 6 Disconnection, voltage acquisition capacitor C 4 The upper polar plate is LIN line voltage difference delta u acquired twice 1 I.e. Deltau 1 ＝u 1 -u 2 The voltage difference Deltau 1 Is read in, voltage difference Deltau 1 Comparing with reference voltage Ref_VoltageII, if the reference voltage is exceeded, the pull-down current of the variable current source is reduced; if lower than the reference voltage, a variable current source I 3 The current of the NMOS transistor MII is increased, and the pull-down current capability of the pull-down transistor of the NMOS transistor MII is controlled.
By such feedback control, a constant rate of the rising edge of the LIN bus voltage is achieved.
In the LIN bus voltage rising process, the process can be repeated for a plurality of times, the beat is given by an on-chip clock, the collection times are according to the clock frequency in the LIN chip, and if the clock frequency is high, more collection can be realized.
Variable current source I 3 Micro current source I 4 Is a very small current source, ensures the capacitance C 6 The upper voltage is pulled down all the time.
According to the invention, through the sample hold circuit S/H and the voltage acquisition capacitor, the voltage change of the voltage on the LIN bus in the acquisition period can be taken out, accurate response can be made based on the LIN signal change outside the LIN chip, and if the acquisition period is shorter, the LIN bus voltage can be approximately considered to be subjected to differential operation; the closed-loop feedback control circuit is used, so that the rising edge and the falling edge of the LIN bus voltage can be kept constant; in addition, the circuit of the invention is simple and has low cost.
Claims (9)
1. The slope control circuit based on LIN bus signal control is characterized by comprising a voltage acquisition circuit (1), a feedback control circuit (3) and a load circuit (2); the load circuit (2) is connected with the input end of the voltage acquisition circuit (1) through an LIN pin, and the voltage acquisition circuit (1) is used for acquiring the voltage when the LIN bus voltage drops or the LIN bus voltage rises; the output end of the voltage acquisition circuit (1) is connected with the input end of the feedback control circuit (3), the output end of the feedback control circuit (3) is connected with the LIN pin, and the feedback control circuit (3) is used for controlling the LIN bus voltage to drop or rise and keeping constant speed.
2. Slope control circuit based on LIN bus signal control according to claim 1, characterized in that the voltage acquisition circuit (1) comprises a sample-and-hold circuit S/HI, a sample-and-hold circuit S/HII, a voltage follower VFI, a voltage follower VFII when the LIN bus voltage drops; the positive input end of the voltage follower VFI is connected with one end of the sampling and holding circuit S/HI, and the other end of the sampling and holding circuit S/HI is connected with the LIN pin; the sampling hold circuit S/HI is connected in parallel with the sampling hold circuit S/HII, and the output end of the sampling hold circuit S/HII is connected with the voltage follower VFIIThe positive input end is connected; output end of voltage follower VFI and switch S 1 Is connected with one end of the connecting rod; output end of voltage follower VFII and switch S 2 Is connected with one end of the connecting rod; switch S 1 The other end of (C) is respectively connected with the voltage acquisition capacitor C 1 Upper pole plate of (S) switch (S) 4 Is connected with one end of the connecting rod; voltage acquisition capacitor C 1 The lower polar plate of (C) is respectively connected with a switch S 3 One end of switch S 2 Is connected to the other end of switch S 3 The other end of the first electrode is grounded; switch S 4 The other end of the feedback control circuit (3) is connected with the positive input end of the operational amplifier OPAI;
the feedback control circuit (3) comprises an operational amplifier OPAI, the negative input end of the operational amplifier OPAI is connected with a reference voltage Ref_voltage I, the output end of the operational amplifier OPAI and a variable current source I 1 Connected to a variable current source I 1 Respectively with the capacitor C 2 Upper plate of (C), micro current source I 2 Is connected with the output end of the capacitor C 2 The lower polar plate of (2) is grounded, and the micro current source I 2 Through resistor R 1 Respectively with the capacitor C 3 The upper polar plate of the NMOS tube MI is connected with the grid electrode of the NMOS tube MI, and the capacitor C 3 The lower electrode plate of the NMOS tube MI is grounded, and the source electrode of the NMOS tube MI is grounded.
3. The slope control circuit according to claim 1 or 2, wherein the gate voltage of the NMOS MI is GND and the LIN bus voltage is highest.
4. Slope control circuit based on LIN bus signal control according to claim 1 or 2, characterized in that the variable current source I 1 Micro current source I 2 Is a very small current source, ensures the capacitance C 3 The upper voltage is always rising.
5. Slope control circuit based on LIN bus signal control according to claim 1, characterized in that the voltage acquisition circuit (1) comprises a sample-and-hold circuit S/HIII, a sample-and-hold circuit S/HIV when the LIN bus voltage risesA voltage follower VFIII, a voltage follower VFIV; the positive input end of the voltage follower VFIII is connected with one end of the sampling and holding circuit S/HIII, and the other end of the sampling and holding circuit S/HIII is connected with the LIN pin; the sampling and holding circuit S/HIII is connected with the sampling and holding circuit S/HIV in parallel, and the output end of the sampling and holding circuit S/HIV is connected with the positive input end of the voltage follower VFIV; output end of voltage follower VFIII and switch S 5 Is connected with one end of the connecting rod; output end of voltage follower VFIV and switch S 6 Is connected with one end of the connecting rod; switch S 5 The other end of (C) is respectively connected with the voltage acquisition capacitor C 4 Upper pole plate of (S) switch (S) 7 Is connected with one end of the connecting rod; voltage acquisition capacitor C 4 The lower polar plate of (C) is respectively connected with a switch S 8 One end of switch S 6 Is connected to the other end of switch S 8 The other end of the first electrode is grounded; switch S 7 The other end of the feedback control circuit (3) is connected with the positive input end of an operational amplifier OPAII;
the feedback control circuit (3) comprises an operational amplifier OPAII, an output end of the operational amplifier OPAII and a variable current source I 3 Connected to a variable current source I 3 And micro current source I 4 Capacitance C 5 Parallel series resistor R 2 Resistance R 2 One way through the other end of the capacitor C 6 One path of the NMOS transistor MII is grounded, the source electrode of the NMOS transistor MII is grounded, and the drain electrode of the NMOS transistor MII is connected between the LIN pin and the voltage acquisition circuit; capacitor C 5 The lower electrode plate of the capacitor is grounded.
6. The slope control circuit of claim 5, wherein the gate voltage of the NMOS transistor MII is VDD and the LIN bus voltage is the lowest.
7. A slope control circuit based on LIN bus signal control according to claim 5 or 6, characterized in that the variable current source I 3 Micro current source I 4 Is a very small current source, ensures the capacitance C 6 The upper voltage is pulled down all the time.
8. Slope control circuit based on LIN bus signal control according to claim 1, characterized in that the load circuit (2) comprises a load resistor R load Load resistor R load And load capacitance C load After being connected in series, the LIN pin is connected with a load resistor R load And load capacitance C load Between them.
9. The control method of a slope control circuit based on LIN bus signal control according to claim 1, comprising the steps of:
step1: the voltage acquisition circuit respectively acquires the voltages on the upper polar plate and the lower polar plate through closing and closing control voltage acquisition capacitors of different switches, so that the voltage difference of LIN bus voltage is obtained;
step2: the feedback control circuit compares the voltage difference in Step1 with a reference voltage, and controls the pull-down current capability of the NMOS tube according to the comparison result;
step3: step1 and Step2 are repeated for a plurality of times, the beat is determined by an on-chip clock, and the acquisition times are based on the frequency of the LIN on-chip clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410067400.8A CN117872903A (en) | 2024-01-17 | 2024-01-17 | Slope control circuit based on LIN bus signal control and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410067400.8A CN117872903A (en) | 2024-01-17 | 2024-01-17 | Slope control circuit based on LIN bus signal control and control method thereof |
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| CN117872903A true CN117872903A (en) | 2024-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410067400.8A Pending CN117872903A (en) | 2024-01-17 | 2024-01-17 | Slope control circuit based on LIN bus signal control and control method thereof |
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| CN101512995A (en) * | 2006-08-30 | 2009-08-19 | Nxp股份有限公司 | Circuit arrangement, local interconnect network (lin) comprising such circuit arrangement as well as method for processing input signals of the lin |
| US20100166085A1 (en) * | 2006-05-24 | 2010-07-01 | Citibank N.A. | Lin network, integrated circuit and method therefor |
| CN202486528U (en) * | 2011-12-30 | 2012-10-10 | 意法半导体研发（上海）有限公司 | Driver circuit |
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| CN113474998A (en) * | 2018-12-28 | 2021-10-01 | 索菲克斯公司 | Driver for a shared bus, in particular a LIN bus |
| CN113839844A (en) * | 2020-06-24 | 2021-12-24 | 赛普拉斯半导体公司 | Local Interconnect Network (LIN) driver circuit |
| CN116032684A (en) * | 2022-12-22 | 2023-04-28 | 上海川土微电子有限公司 | LIN bus driving circuit and device |
| CN116028400A (en) * | 2022-12-30 | 2023-04-28 | 思瑞浦微电子科技（苏州）股份有限公司 | Signal output control circuit and LIN transceiver |
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2024
- 2024-01-17 CN CN202410067400.8A patent/CN117872903A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028451A (en) * | 1997-12-31 | 2000-02-22 | Intel Corporation | Method and apparatus for topology dependent slew rate control |
| US20100166085A1 (en) * | 2006-05-24 | 2010-07-01 | Citibank N.A. | Lin network, integrated circuit and method therefor |
| CN101512995A (en) * | 2006-08-30 | 2009-08-19 | Nxp股份有限公司 | Circuit arrangement, local interconnect network (lin) comprising such circuit arrangement as well as method for processing input signals of the lin |
| CN202486528U (en) * | 2011-12-30 | 2012-10-10 | 意法半导体研发（上海）有限公司 | Driver circuit |
| CN110224951A (en) * | 2018-03-01 | 2019-09-10 | 英飞凌科技股份有限公司 | Circuit bus driver |
| CN113474998A (en) * | 2018-12-28 | 2021-10-01 | 索菲克斯公司 | Driver for a shared bus, in particular a LIN bus |
| CN113839844A (en) * | 2020-06-24 | 2021-12-24 | 赛普拉斯半导体公司 | Local Interconnect Network (LIN) driver circuit |
| CN116032684A (en) * | 2022-12-22 | 2023-04-28 | 上海川土微电子有限公司 | LIN bus driving circuit and device |
| CN116028400A (en) * | 2022-12-30 | 2023-04-28 | 思瑞浦微电子科技（苏州）股份有限公司 | Signal output control circuit and LIN transceiver |
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