CN101546205B - Power management circuit and frequency compensation method thereof - Google Patents
Power management circuit and frequency compensation method thereof Download PDFInfo
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- CN101546205B CN101546205B CN2008100888224A CN200810088822A CN101546205B CN 101546205 B CN101546205 B CN 101546205B CN 2008100888224 A CN2008100888224 A CN 2008100888224A CN 200810088822 A CN200810088822 A CN 200810088822A CN 101546205 B CN101546205 B CN 101546205B
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- 238000005070 sampling Methods 0.000 claims description 8
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Abstract
The invention discloses a power management circuit, which comprises a voltage stabilizing circuit, a first frequency compensation circuit, a first switching circuit and a sensing circuit, wherein the voltage stabilizing circuit comprises a signal output end. The first switching circuit responds to an actuating first control signal to conduct so as to couple the first frequency compensation circuit to the voltage stabilizing circuit. The sensing circuit is used for judging whether an output capacitor is coupled to the signal output end, and producing the actuating first control signal to conduct the first switching circuit when the output capacitor is not coupled to the signal output end so as to connect the first frequency compensation circuit to the voltage stabilizing circuit, thereby performing the operation of frequency compensation on the voltage stabilizing circuit.
Description
Technical field
The present invention relates to a kind of voltage regulator circuit, and be particularly related to a kind of voltage regulator circuit that is applied in the power-supply management system.
Background technology
Traditionally, (Low Dropout Voltage, LDO) mu balanced circuit is used in the various power-supply management systems low pressure reduction, for example the battery system of portable electric device.For instance, referring to Fig. 1, it has described the circuit diagram of conventional low difference voltage stabilizer.LDO voltage stabilizer 10 comprises error amplifier (Error Operational Amplifier) OP1, transistor T 1, resistance R 1 and R2, and wherein the negative input end of error amplifier OP1 receives reference voltage Vrf.Transistor T 1, resistance R 1 and R2 form feedback loop, are used for the output voltage V x of difference amplifier OP1 is feedback to the positive input terminal of difference amplifier OP1, and the feedback voltage accurate close in fact with the position of reference voltage Vrf is provided thus.
Traditionally, (Equivalent Series Resistor, ESR) RL is so that 10 stable operations of LDO voltage stabilizer for the load capacitance CL that needs at output terminal design high capacity of LDO voltage stabilizer 10 and equivalent series resistance.Yet load capacitance CL uses bigger integrated circuit area or discrete component to realize.So, reach the higher shortcoming of manufacturing cost more greatly with making traditional LDO voltage stabilizer 10 have circuit area.And if save load capacitance CL, will cause the LDO voltage stabilizer 10 can't stable operation again.
Summary of the invention
The present invention relates to a kind of electric power management circuit, it can save operation stably under the situation of load capacitance.So, poor (Low Dropout Voltage, LDO) voltage stabilizer, the electric power management circuit of present embodiment have that operational stability is higher, area is less, cost is lower and circuit design degree of freedom advantage of higher than conventional low.
A kind of electric power management circuit that proposes according to the present invention comprises mu balanced circuit, first frequency compensating circuit, first on-off circuit and circuit for detecting, and mu balanced circuit comprises signal output part.First on-off circuit is in response to the first control signal conducting of activation, to couple the first frequency compensating circuit to mu balanced circuit.Circuit for detecting is used for judging whether output capacitance is coupled to signal output part, and when output capacitance is not coupled to signal output part, produce the first control signal conducting, first on-off circuit of activation, to connect the first frequency compensating circuit to mu balanced circuit, thus, mu balanced circuit is carried out the frequency compensation operation.
According to electric power management circuit of the present invention, wherein this circuit for detecting comprises: input buffer (Buffer), comprise input end and output terminal, receive charge frequency (Clock) signal respectively and be coupled to signal output part that this input buffer provides this charge frequency signal to signal output part; First flip-flop (Flip Flop) is used in response to the sampling frequency signal signal on the signal output part being taken a sample, to produce first sampled signal; Second flip-flop is used in response to the sampling frequency signal, this first sampled signal is taken a sample, to produce second sampled signal; And logical circuit, be used for having different positions in fact on time at first and second sampled signal, judge that output capacitance is not coupled to described signal output part, and produce first control signal of activation.
According to electric power management circuit of the present invention, wherein logical circuit is used for having identical in fact position on time at first and second sampled signal, judges that output capacitance is coupled to described signal output part.
According to electric power management circuit of the present invention, wherein mu balanced circuit comprises: error amplifier, and negative input end receives reference voltage; And feedback loop, be used for the output signal of this error amplifier is feedback to the positive input terminal of error amplifier.
According to electric power management circuit of the present invention, wherein feedback loop comprises: transistor (Transistor), source electrode (Source) reception first voltage, grid (Gate) are coupled to the output terminal of error amplifier, and drain electrode (Drain) is coupled to signal output part; And first resistance and second resistance, the two ends of this first resistance are coupled to the positive input terminal of error amplifier respectively and receive second voltage, and the two ends of second resistance couple with the positive input terminal and the signal output part of error amplifier respectively.
According to electric power management circuit of the present invention, wherein first and second voltage is respectively circuit high voltage and ground voltage, and described transistor is P type metal-oxide semiconductor (Metal OxideSemiconductor, MOS) transistor.
According to electric power management circuit of the present invention, wherein first and second voltage is respectively ground voltage and circuit high voltage, and described transistor is a N type MOS transistor.
According to electric power management circuit of the present invention, wherein first on-off circuit is used for when conducting, makes first end of first frequency compensating circuit and output terminal and the described transistor drain that second end is coupled to error amplifier respectively.
According to electric power management circuit of the present invention, wherein the second switch circuit also is used for when conducting, makes the second frequency compensating circuit be coupled to the output terminal of error amplifier.
According to electric power management circuit of the present invention, wherein also comprise: the second frequency compensating circuit; And the second switch circuit, in response to the second control signal conducting of activation, to couple the second frequency compensating circuit to mu balanced circuit; Wherein, this circuit for detecting also is used for when output capacitance is coupled to signal output part, produces the second control signal conducting second switch of activation, to connect second frequency compensating circuit and mu balanced circuit, thus, mu balanced circuit is carried out the frequency compensation operation.
According to electric power management circuit of the present invention, wherein the second frequency compensating circuit comprises resistor-capacitor series circuit, and a termination of described resistor-capacitor series circuit is received specific voltage, and the other end is coupled to the second switch circuit.
According to electric power management circuit of the present invention, wherein the first frequency compensating circuit comprises resistor-capacitor series circuit, and an end of described resistor-capacitor series circuit is coupled to first on-off circuit, and the other end is coupled to signal output part.
According to electric power management circuit of the present invention, wherein mu balanced circuit is low pressure reduction mu balanced circuit.
A kind of frequency compensation method that proposes according to the present invention is used for mu balanced circuit is carried out the frequency compensation operation, and mu balanced circuit comprises signal output part.Frequency compensation method comprises the following steps: at first, judges whether output capacitance is coupled to signal output part; And when output capacitance is not coupled to signal output part, connect the first frequency compensating circuit to mu balanced circuit, mu balanced circuit is carried out the frequency compensation operation.
According to frequency compensation method of the present invention, be used for mu balanced circuit is carried out frequency compensation operation, this mu balanced circuit comprises signal output part, this frequency compensation method comprises: whether the capacitance of equivalent capacity of judging signal output part is less than predetermined value; And, provide the first frequency compensating frequency to mu balanced circuit when the capacitance of equivalent capacity during less than this predetermined value, mu balanced circuit is carried out the frequency compensation operation.
According to frequency compensation method of the present invention, further comprise: when the capacitance of equivalent capacity during, connect the second frequency compensating circuit, mu balanced circuit is carried out frequency compensation to mu balanced circuit greater than this predetermined value.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below:
Description of drawings
Fig. 1 has described the circuit diagram of conventional low difference voltage stabilizer.
Fig. 2 has described the block scheme according to the electric power management circuit of the embodiment of the invention.
Fig. 3 has described the detailed circuit diagram of the circuit for detecting 28 of Fig. 2.
Fig. 4 has described the part detailed circuit diagram of the electric power management circuit of Fig. 2.
Fig. 5 A and 5B have described the gain and the phase place Bode diagram of the loop gain of mu balanced circuit 22 when not compensating respectively.
Fig. 6 A and 6B have described the gain and the phase place Bode diagram of the loop gain of mu balanced circuit 22 after the frequency compensation respectively.
Fig. 7 has described the opposing party's block diagram according to the electric power management circuit of the embodiment of the invention.
Fig. 8 has described the another block scheme according to the electric power management circuit of the embodiment of the invention.
Fig. 9 A and 9B have described the gain and the phase place Bode diagram of the loop gain of mu balanced circuit 42 when not carrying out frequency compensation respectively.
Figure 10 A and 10B have described the gain and the phase place Bode diagram of the loop gain of mu balanced circuit 42 after the frequency compensation respectively.
Embodiment
The electric power management circuit of present embodiment is provided with circuit for detecting and judges whether the output capacitance of high capacity and the output terminal that equivalent series resistance is coupled to electric power management circuit, and selects corresponding frequency compensated circuit to come the mu balanced circuit in the electric power management circuit is carried out frequency compensation in view of the above.
With reference to figure 2, it has described the block scheme according to the electric power management circuit of the embodiment of the invention.Electric power management circuit 20 comprises mu balanced circuit 22, frequency compensated circuit 24, on-off circuit 26 and circuit for detecting 28.On-off circuit 26 has first and second output terminal, is coupled to mu balanced circuit 22 and frequency compensated circuit 24 respectively, and on-off circuit 26 is used in response to control signal Sctr conducting, thereby frequency compensated circuit 24 is coupled to mu balanced circuit 22.
Mu balanced circuit 22 has signal output part NDo, is used to provide output voltage V o.Circuit for detecting 28 is used for judging whether that the output capacitance of high capacity and ESR are coupled to signal output part NDo, and be used for when the output capacitance that does not have high capacity and ESR are coupled to signal output part NDo, produce the control signal Sctr actuating switch circuit 26 of activation, to connect frequency compensated circuit 26, thus mu balanced circuit 22 is carried out frequency compensation to mu balanced circuit 22.For instance, the output capacitance of high capacity is the output capacitance of capacitance more than or equal to 1 microfarad (Micro Farad, μ F).
With reference to figure 3, it has described the detailed circuit diagram of the circuit for detecting 28 of Fig. 2.In more detail, circuit for detecting 28 comprises input buffer (Buffer) 28a, flip- flop 28b, 28c and logical block 28d.Input buffer 28a comprises input end and output terminal, and it receives charge frequency signal clk_c respectively and is coupled to signal output part NDo.Input buffer 28a is used for charge frequency signal clk_c is provided to signal output part NDo, so that the electric capacity on the signal output part NDo is charged.
Wherein, when the output capacitance that does not have high capacity and ESR were coupled to signal output part NDo, the numerical value of the equivalent capacity of seeing on the signal output part NDo was lower.At this moment, the signal level on the signal output part NDo is switched between high levels and low the aligning along with the change of charge frequency signal clk_c in fact.When the output capacitance of high capacity and ESR were coupled to signal output part NDo, the numerical value of the equivalent capacity of seeing on the signal output part NDo was higher.At this moment, the change of the signal level on signal output part NDo speed is slower.
Flip-flop 28b is used in response to sampling frequency signal clk_s the signal on the signal output part NDo being taken a sample, to produce sampled signal Ss1.Flip-flop 28c is used in response to sampling frequency signal clk_s, and Ss1 takes a sample to sampled signal, to produce sampled signal Ss2.Wherein, when the output capacitance that does not have high capacity and ESR are coupled to signal output part NDo, signal on the signal output part NDo switches between high levels and low level, and so, sampled signal Ss1 and Ss2 that flip- flop 28b and 28c sampling obtain have different numerical value.For instance, in same time point, sampled signal Ss1 and Ss2 equal numerical value 1 and numerical value 0 respectively.When the output capacitance of high capacity and ESR were coupled to signal output part NDo, the signal on the signal output part NDo was all near low level, and so, sampled signal Ss1 and Ss2 that flip- flop 28b and 28c sampling obtain have identical numerical value.For instance, in same time point, sampled signal Ss1 and Ss2 are equal to numerical value 0.
Mu balanced circuit 22 to present embodiment is further detailed for example.With reference to figure 4, it has described the part detailed circuit diagram of the electric power management circuit of Fig. 2.Mu balanced circuit 22 is a low-dropout regulator, comprising error amplifier OP2 and feedback loop 22a.The negative input end of error amplifier OP2 receives reference voltage Vrf, and positive input terminal and output terminal are coupled to the two ends of feedback loop 22a respectively.Error amplifier OP2 is used for more respectively through positive input terminal and the signal of importing through negative input end, to produce output voltage V c accordingly.
Transistor T 2 is for example biased to be common source (Common Source) amplifier, thereby computing obtains output voltage V o according to comparative voltage Vc.Resistance R 3 for example forms the bias resistance string with R4, is used for output voltage V o is carried out dividing potential drop, so that branch pressure voltage is provided to the positive input terminal of error amplifier OP2.So, thus output voltage V o is feedback to the positive input terminal of error amplifier OP2.
In general, when the output capacitance that does not have high capacity and ESR are coupled to signal output part NDo, mu balanced circuit 22 has limit (Pole) P1 and P2, wherein limit P2 and P1 are respectively the frequency response limits that forms at the equivalent capacity inductance that the output terminal of the output terminal of error amplifier OP2 and mu balanced circuit 22 is seen, and P2 is main limit, P1 is less important limit, shown in Fig. 5 A and Fig. 5 B, Fig. 5 A has described the gain Bode diagram (Bode Plot) of the loop gain (Loop Gain) of mu balanced circuit 22 when not carrying out frequency compensation, and Fig. 5 B has described the phase place Bode diagram of the loop gain of mu balanced circuit 22 when not carrying out frequency compensation.According to Fig. 5 A and Fig. 5 B as can be known, equal corresponding approaching-180 degree of phase place of frequency of unity gain (Unit Gain) (being that loop gain equals 0dB), so will cause mu balanced circuit 22 to produce vibration with the loop gain of mu balanced circuit 22.
Produce vibration for fear of mu balanced circuit 22, when circuit for detecting 28 detects the output capacitance that do not have high capacity and ESR when being coupled to signal and exporting single NDo, it couples frequency compensated circuit 24 to mu balanced circuit 22 by actuating switch 26, and mu balanced circuit 22 is carried out frequency compensation.Frequency compensated circuit 24 comprises resistance R c1 and capacitor C c1 in the present embodiment.Resistance R c1, capacitor C c1 and switch 26 are connected in series between error amplifier OP2 and signal output part NDo.When switch 26 was conducting, frequency compensated circuit 24 and mu balanced circuit 22 formed loops, make frequency response circuit 24 to carry out frequency compensation to mu balanced circuit 22.
For instance, the gain of the loop gain of the mu balanced circuit after the compensation 22 and phase place Bode diagram are for example respectively shown in Fig. 6 A and Fig. 6 B.Wherein, for the operation that makes that mu balanced circuit 22 can be stable, the technology of separating (Pole Splitting) by limit comes mu balanced circuit 22 compensated that limit P1 and P2 are changed respectively is P1 ' and P2 ' in the present embodiment.So, can guarantee that mu balanced circuit 22 has higher phase margin (PhaseMargin), and stably operable.
In the present embodiment, though be that the situation of P type MOS transistor is that example explains only with the transistor T in the mu balanced circuit 22 2, the mu balanced circuit 22 of present embodiment is not limited to realize with P type MOS transistor.For instance, another mu balanced circuit 32 of present embodiment also can realize by N type MOS transistor T2 ', as shown in Figure 7.
In the present embodiment, though only with in electric power management circuit 20, a frequency compensated circuit 24 only is set, with when the output capacitance that does not have high capacity and ESR are coupled to signal output part NDo to mu balanced circuit 22 carry out frequency compensated situation be example as an illustration, yet the electric power management circuit 20 of present embodiment is not limited to only comprise a frequency compensated circuit.For instance, another electric power management circuit 40 of present embodiment comprise two frequency compensated circuits 44 and 44 ', be used for respectively being coupled to signal output part NDo and the output capacitance of high capacity being arranged and ESR when being coupled to signal output part NDo at the output capacitance that does not have high capacity and ESR, by actuating switch 46 and 46 ' be coupled to mu balanced circuit 22, so that it is carried out frequency compensation, as shown in Figure 8.
Wherein, frequency compensated circuit 44 and 24 has close structure frequency response compensating circuit 44 ' comprise resistance R c2 and capacitor C c2, and the one end interconnects, the other end respectively receiving circuit high voltage VDD and be coupled to switch 46 '.Circuit for detecting 48 is used for producing the control signal Sctr_1 and the Sctr_2 of activation respectively when not having and having the output capacitance of high capacity and ESR to be coupled to signal output part NDo.In an example, control signal Sctr_1 equals the control signal Sctr that circuit for detecting 28 produces, and control signal Sctr_2 is the inversion signal of control signal Sctr.
For example to frequency compensated circuit 44 ' operation describe.With reference to figure 9A and Fig. 9 B, Fig. 9 A has described the gain Bode diagram of the loop gain of mu balanced circuit 42 when not carrying out frequency compensation, and Fig. 9 B has described the phase place Bode diagram of the loop gain of mu balanced circuit 42 when not carrying out frequency compensation.In general, when the output capacitance Co of high capacity and ESR Ro are coupled to signal output part NDo, voltage of voltage regulation 42 has limit P3 and P4, wherein limit P4 and P3 are respectively the frequency response limits that forms at the equivalent capacity inductance that the output terminal of the output terminal of error amplifier OP2 and mu balanced circuit 42 is seen, and because the output capacitance Co of high capacity makes that P3 is main limit, P4 is less important limit.According to Fig. 9 A and Fig. 9 B as can be known, equal corresponding approaching-180 degree of phase place of frequency of unity gain, so will cause mu balanced circuit 42 to produce vibration with the loop gain of mu balanced circuit 42.
Produce vibration for fear of mu balanced circuit 42, when circuit for detecting 48 detects the output capacitance Co of high capacity and ESR Ro when being coupled to signal and exporting single NDo, it is by actuating switch 46 ' couple frequency compensated circuit 44 ' to mu balanced circuit 42, mu balanced circuit 42 is carried out frequency compensation.For instance, the loop gain of the mu balanced circuit after the compensation 22 and phase place Bode diagram are for example respectively shown in Figure 10 A and Figure 10 B.Wherein, for the operation that makes that mu balanced circuit 42 can be stable, come mu balanced circuit 42 is compensated by the skill of limit cancellation at zero point (Pole-zeroCancellation) in the present embodiment.So, can guarantee that mu balanced circuit 42 has higher phase margin, and stably operable.
The electric power management circuit of present embodiment is provided with circuit for detecting and judges whether the output capacitance of high capacity and the output terminal that ESR is coupled to electric power management circuit, and selects corresponding frequency compensated circuit to come the mu balanced circuit in the electric power management circuit is carried out frequency compensation in view of the above.So, the electric power management circuit of present embodiment can save operation stably under the situation of load capacitance.So, than conventional low difference voltage stabilizer, the electric power management circuit of present embodiment has that operational stability is higher, area is less, cost is lower and circuit design degree of freedom advantage of higher.
In addition, the electric power management circuit of present embodiment also can comprise two groups or more frequency compensated circuit, is used for respectively being coupled to the output terminal of electric power management circuit and not having the output capacitance of high capacity and mu balanced circuit is carried out frequency compensation during output terminal that ESR is coupled to electric power management circuit at the output capacitance that high capacity is arranged and ESR.So, the electric power management circuit of present embodiment has frequency response characteristic preferably.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The technical staff in the technical field of the invention without departing from the spirit and scope of the present invention, can do various changes and modification.Therefore, protection scope of the present invention is when looking appended being as the criterion that claim defined.
The primary clustering symbol description
10 low-dropout regulator OP1, OP2 difference amplifier
T1, T2, T2 ' transistor
R1, R2, R3, R4, Rc1, Rc2 resistance
CL load capacitance RL equivalent series resistance
20,40 electric power management circuits 22,32,42 mu balanced circuits
24,44,44 ' frequency compensated circuit 26,46,46 ' switch
28,48 circuit for detecting 28a input buffers
28b, 28c flip-flop 28d logic circuit
Ndo signal output part Cc1, Cc2: electric capacity
Co: the output capacitance Ro of high capacity: equivalent series resistance.
Claims (14)
1. electric power management circuit comprises:
Mu balanced circuit comprises signal output part;
The first frequency compensating circuit;
First on-off circuit is electrically connected between described mu balanced circuit and the described first frequency compensating circuit; And
Circuit for detecting, be used for judging whether output capacitance is coupled to described signal output part, when judging that described output capacitance is not coupled to described signal output part, produce first of activation and control signal to described first on-off circuit, make the described first on-off circuit conducting, make described first frequency compensating circuit be electrically connected to described mu balanced circuit, thus, described mu balanced circuit is carried out the frequency compensation operation
Wherein said circuit for detecting comprises:
Input buffer comprises input end and output terminal, receives the charge frequency signal respectively and is coupled to described signal output part, and described input buffer provides described charge frequency signal to described signal output part;
First flip-flop is used in response to the sampling frequency signal signal on the described signal output part being taken a sample, to produce first sampled signal;
Second flip-flop is used in response to described sampling frequency signal described first sampled signal being taken a sample, to produce second sampled signal; And
Logical circuit, be used for described first and described second sampled signal to have different positions in fact punctual, judge that described output capacitance is not coupled to described signal output part, and produce described first control signal of activation.
2. electric power management circuit according to claim 1, wherein said logical circuit be used for described first and described second sampled signal to have an identical in fact position punctual, judge that described output capacitance is coupled to described signal output part.
3. electric power management circuit according to claim 1, wherein said mu balanced circuit comprises:
Error amplifier, negative input end receives reference voltage; And
Feedback loop is used for the output signal of described error amplifier is feedback to the positive input terminal of described error amplifier.
4. electric power management circuit according to claim 3, wherein said feedback loop comprises:
Transistor, source electrode receive first voltage, and grid is coupled to the output terminal of described error amplifier, and drain electrode is coupled to described signal output part; And
First resistance and second resistance, the two ends of described first resistance are coupled to the positive input terminal of described error amplifier respectively and receive second voltage, and the two ends of described second resistance couple with the positive input terminal and the described signal output part of described error amplifier respectively.
5. electric power management circuit according to claim 4, wherein said first and described second voltage be respectively circuit high voltage and ground voltage, described transistor is a P type metal-oxide semiconductor transistor.
6. electric power management circuit according to claim 4, wherein said first and described second voltage be respectively ground voltage and circuit high voltage, described transistor is a N type MOS transistor.
7. electric power management circuit according to claim 4, wherein said first on-off circuit is used for when conducting, makes first end of described first frequency compensating circuit and output terminal and the described transistor drain that second end is coupled to described error amplifier respectively.
8. electric power management circuit according to claim 3 wherein further comprises:
The second frequency compensating circuit; And
The second switch circuit is in response to the second control signal conducting of activation, to couple described second frequency compensating circuit to described mu balanced circuit;
Wherein, described circuit for detecting also is used for when described output capacitance is coupled to described signal output part, produce the described second switch circuit of the described second control signal conducting of activation, to connect described second frequency compensating circuit and described mu balanced circuit, thus, described mu balanced circuit is carried out the frequency compensation operation.
9. electric power management circuit according to claim 8, wherein said second switch circuit also is used for when conducting, makes described second frequency compensating circuit be coupled to the output terminal of described error amplifier.
10. electric power management circuit according to claim 1 wherein also comprises:
The second frequency compensating circuit; And
The second switch circuit is in response to the second control signal conducting of activation, to couple described second frequency compensating circuit to described mu balanced circuit;
Wherein, described circuit for detecting also is used for when described output capacitance is coupled to described signal output part, produce the described second switch circuit of the described second control signal conducting of activation, to connect described second frequency compensating circuit and described mu balanced circuit, thus, described mu balanced circuit is carried out the frequency compensation operation.
11. electric power management circuit according to claim 10, wherein said second frequency compensating circuit comprises resistor-capacitor series circuit, and a termination of described resistor-capacitor series circuit is received specific voltage, and the other end is coupled to described second switch circuit.
12. electric power management circuit according to claim 1, wherein said first frequency compensating circuit comprises resistor-capacitor series circuit, and an end of described resistor-capacitor series circuit is coupled to described first on-off circuit, and the other end is coupled to described signal output part.
13. electric power management circuit according to claim 1, wherein said mu balanced circuit is low pressure reduction mu balanced circuit.
14. one kind according to Claim 8 or the frequency compensation method of 10 described electric power management circuits, the frequency of utilization compensating circuit comes mu balanced circuit is carried out the frequency compensation operation, described frequency compensated circuit comprises resistor-capacitor series circuit, described mu balanced circuit comprises signal output part, and described frequency compensation method comprises:
Whether the capacitance of equivalent capacity of judging described signal output part is less than predetermined value;
When the capacitance of described equivalent capacity during less than described predetermined value, provide the first frequency compensating frequency to described mu balanced circuit, described mu balanced circuit is carried out the frequency compensation operation; And
When the capacitance of described equivalent capacity during greater than described predetermined value, connect the second frequency compensating circuit to described mu balanced circuit, described mu balanced circuit is carried out frequency compensation.
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| CN2008100888224A CN101546205B (en) | 2008-03-28 | 2008-03-28 | Power management circuit and frequency compensation method thereof |
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| CN2008100888224A CN101546205B (en) | 2008-03-28 | 2008-03-28 | Power management circuit and frequency compensation method thereof |
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| CN101546205B true CN101546205B (en) | 2011-05-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2579120A1 (en) * | 2011-10-06 | 2013-04-10 | ST-Ericsson SA | LDO regulator |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7121637B2 (en) * | 2018-11-12 | 2022-08-18 | 日立Astemo株式会社 | electronic device |
| US11012074B1 (en) * | 2020-01-08 | 2021-05-18 | Nanya Technology Corporation | Off chip driving circuit and signal compensation method |
| CN112770454B (en) * | 2021-02-19 | 2023-08-01 | 杭州优特电源有限公司 | Variable-frequency multipath constant-current output power supply and application thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6765374B1 (en) * | 2003-07-10 | 2004-07-20 | System General Corp. | Low drop-out regulator and an pole-zero cancellation method for the same |
| CN1623232A (en) * | 2002-01-24 | 2005-06-01 | 皇家飞利浦电子股份有限公司 | RF amplifier |
| CN101126937A (en) * | 2006-07-10 | 2008-02-20 | 麦奎尔有限公司 | Frequency compensation circuit and method for a switching regulator using external zero |
-
2008
- 2008-03-28 CN CN2008100888224A patent/CN101546205B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1623232A (en) * | 2002-01-24 | 2005-06-01 | 皇家飞利浦电子股份有限公司 | RF amplifier |
| US6765374B1 (en) * | 2003-07-10 | 2004-07-20 | System General Corp. | Low drop-out regulator and an pole-zero cancellation method for the same |
| CN101126937A (en) * | 2006-07-10 | 2008-02-20 | 麦奎尔有限公司 | Frequency compensation circuit and method for a switching regulator using external zero |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2579120A1 (en) * | 2011-10-06 | 2013-04-10 | ST-Ericsson SA | LDO regulator |
| WO2013050291A1 (en) * | 2011-10-06 | 2013-04-11 | St-Ericsson Sa | Ldo regulator |
| US9423809B2 (en) | 2011-10-06 | 2016-08-23 | St-Ericsson Sa | LDO regulator having variable gain depending on automatically detected output capacitance |
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| CN101546205A (en) | 2009-09-30 |
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