CN117833885A - Reset circuit for logic chip and logic chip - Google Patents

Abstract

The application discloses a reset circuit for a logic chip and the logic chip. The reset circuit comprises a hysteresis comparison module and a logic module, wherein the hysteresis comparison module is used for obtaining a first voltage signal according to an external reset signal and comparing the first voltage signal with a set threshold voltage to generate a second voltage signal, and the logic module is connected with a parasitic capacitor at an internal reset node and used for charging and discharging the parasitic capacitor according to the logic operation result of the external reset signal and the second voltage signal to generate an internal reset signal. The reset circuit of the invention reduces the time sequence requirement of the reset of the internal circuit of the chip by expanding the external reset signal with smaller pulse width into the internal reset signal with larger pulse width, so that the internal reset signal can reach the level required by effective reset, thereby effectively resetting the chip on the premise of not increasing the dynamic power consumption of the circuit.

Description

Reset circuit for logic chip and logic chip

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a reset circuit for a logic chip and a logic chip.

Background

When an electronic device is logically malfunctioning or disturbed, it needs to be reset to a valid initial state. Accordingly, a reset circuit needs to be provided in various electronic devices. When the electronic equipment needs to be reset, an external reset signal is input to the reset circuit through a reset pin, and the reset circuit generates an internal reset signal for controlling other modules in the electronic equipment according to the external reset signal. In general, the reset pins of the chip are divided into two types of active high level and active low level, and for the active high level, when the pins are pulled up, the chip performs a reset operation; for the active low version, the chip will perform a reset operation when the pin is pulled low. The external reset may be accomplished in a number of ways, such as by a key or circuit power down.

Fig. 1 is a schematic structural diagram of a logic chip with a reset function in the prior art. As shown in fig. 1, the logic chip 100 of the prior art generally has a Reset pin and a Reset circuit 110, and the Reset circuit 110 is configured to generate an internal Reset signal Reset for controlling the Reset of n D flip-flops dff_1 to dff_n (n is an integer greater than or equal to 1) in the logic chip 100 according to an external Reset signal reset_ext applied by the Reset pin. Taking a logic chip with an active high external Reset signal as an example, when the external Reset signal reset_ext is pulled high, the internal n D flip-flops dff_1 to dff_n are all Reset. n D flip-flops dff_1 to dff_n are connected to an internal Reset node, and when the number of internal D flip-flops is large, for example, n=128 or more, the parasitic capacitance Cpar of the Reset node is relatively large, and the Reset signal takes a long time to change from low level to high level. When the external Reset signal reset_ext is a pulse signal and the pulse width is small, as shown in fig. 2a, the pulse width tw=2ns of the external Reset signal reset_ext in fig. 2, and the internal Reset signal Reset is likely to be unable to be charged to a high level for effective Reset within 2ns time, as shown in fig. 2b, may cause the chip to fail to perform a correct Reset operation.

In order to improve the driving capability of the internal Reset signal Reset, the Reset circuit 110 of the related art is generally implemented by n buffers B1 to Bn, so that the internal Reset signal Reset can be charged to a high level for effective Reset in a short time. However, this method increases the dynamic power consumption of the internal Reset signal Reset during the inversion process, which may affect the integrity of the power supply, and for a Reset signal with a smaller pulse width, the greater the dynamic power consumption of the Reset circuit, the greater its impact on the integrity of the power supply.

Therefore, there is a need for an improvement in the reset circuit of the prior art that can reduce the impact on the dynamic power consumption of the circuit while meeting the reset requirements of the logic chip.

Disclosure of Invention

In view of the foregoing, an object of the present invention is to provide a reset circuit for a logic chip and a logic chip, which can widen a pulse width of an external reset signal, thereby reducing an influence on dynamic power consumption of the circuit while satisfying a reset requirement of the logic chip.

According to an aspect of the present invention, there is provided a reset circuit for a logic chip for converting an external reset signal into an internal reset signal, including: the hysteresis comparison module is used for obtaining a first voltage signal according to the external reset signal and comparing the first voltage signal with a set threshold voltage to generate a second voltage signal; and a logic module connected with the parasitic capacitance at the internal reset node, and configured to charge and discharge the parasitic capacitance according to a logic operation result of the external reset signal and the second voltage signal, so as to generate the internal reset signal, where the external reset signal has a first pulse width, and the internal reset signal has a second pulse width that is greater than the first pulse width.

Optionally, when the external reset signal changes from an active level to an inactive level, the second voltage signal changes to an inactive level after a set delay time, and the logic module is configured to charge or discharge the parasitic capacitance when the external reset signal is at an active level, and to discharge or charge the parasitic capacitance when both the external reset signal and the second voltage signal are at inactive levels, wherein the delay time is greater than a time required for the logic module to charge or discharge the parasitic capacitance to a high level or a low level such that the internal reset signal reaches an active reset.

Optionally, the hysteresis comparison module includes: a signal conversion unit for converting the external reset signal into an intermediate reset signal; the charge-discharge unit is connected with the first node and is used for charging and discharging the first node according to the intermediate reset signal so as to generate the first voltage signal; and a hysteresis comparator for comparing the first voltage signal with the threshold voltage and generating the second voltage signal according to a comparison result.

Optionally, when the external reset signal changes from an active level to an inactive level, the charge-discharge unit discharges the first node, and when the first voltage signal decreases to a negative threshold voltage of the hysteresis comparator, the second voltage signal changes to an inactive level, wherein the set delay time is equal to a period between when the charge-discharge unit starts discharging the first node to when the first voltage signal decreases to the negative threshold voltage.

Optionally, the charge and discharge unit includes: the first end of the PMOS tube is connected with the power supply voltage, the second end of the PMOS tube is connected with the first node, and the control end of the PMOS tube is connected with the intermediate reset signal; a resistor, a first end of which is connected with the first node; the first end of the NMOS tube is connected with the second end of the resistor, the second end of the NMOS tube is connected with the ground, and the control end of the NMOS tube is connected with the intermediate reset signal; and a capacitor having a first end connected to the power supply voltage and a second end connected to the first node.

Optionally, the active level of the external reset signal is a high level, the signal conversion unit includes a first inverter, and the intermediate reset signal and the external reset signal are mutually inverted signals.

Optionally, the logic module includes an or circuit for performing an or logic operation on the second voltage signal and the external reset signal.

Optionally, the effective level of the external reset signal is a low level, the signal conversion unit includes a buffer, the intermediate reset signal and the external reset signal are in-phase signals, the hysteresis comparison module further includes a second inverter, an input of the second inverter is connected with an output of the hysteresis comparator, and the second inverter is used for obtaining the second voltage signal according to the output of the hysteresis comparator, where the logic module includes an and circuit, and the and circuit is used for performing an and logic operation on the second voltage signal and the external reset signal.

Optionally, the hysteresis comparator is implemented by a schmitt trigger.

According to another aspect of the present invention, there is provided a logic chip, including the above-mentioned reset circuit, wherein the reset circuit is configured to generate an internal reset signal according to an external reset signal applied by a reset pin of the logic chip.

In summary, the embodiment of the invention provides a reset circuit for a logic chip, which includes a hysteresis comparison module and a logic module, wherein the hysteresis comparison module is used for obtaining a first voltage signal according to an external reset signal and comparing the first voltage signal with a set threshold voltage to generate a second voltage signal, and the logic module is connected with a parasitic capacitor at an internal reset node and is used for charging and discharging the parasitic capacitor according to the logic operation results of the external reset signal and the second voltage signal to generate an internal reset signal. The reset circuit of the invention reduces the time sequence requirement of the reset of the internal circuit of the chip by expanding the external reset signal with smaller pulse width into the internal reset signal with larger pulse width, so that the internal reset signal can reach the level required by effective reset, thereby effectively resetting the chip on the premise of not increasing the dynamic power consumption of the circuit.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a schematic structural diagram of a logic chip with a reset function in the prior art.

Fig. 2a and 2b show waveforms of an external reset signal and an internal reset signal, respectively, according to the prior art.

Fig. 3 is a schematic diagram showing a logic chip with a reset function according to an embodiment of the present invention.

Fig. 4 shows a circuit schematic of a reset circuit according to a first embodiment of the invention.

Fig. 5a to 5c are schematic waveforms of an external reset signal, a first voltage signal and an internal reset signal, respectively, according to an embodiment of the present invention.

Fig. 6 shows a circuit schematic of a reset circuit according to a second embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

The invention will be further described with reference to the drawings and examples.

Fig. 3 is a schematic diagram showing a logic chip with a reset function according to an embodiment of the present invention. As shown in fig. 3, the logic chip 200 includes a reset pin 201, a reset circuit 210, and n D flip-flops dff_1 to dff_n (n is an integer greater than or equal to 1). Wherein the Reset circuit 210 is configured to generate an internal Reset signal Reset for controlling a Reset operation of the n D flip-flops dff_1 to dff_n from an external Reset signal reset_ext applied by the Reset pin 201, each of the n D flip-flops dff_1 to dff_n having a data terminal for receiving a data signal Dx (x=1, 2, … …, n), a clock terminal for receiving a clock signal Clk, and a Reset terminal for receiving the internal Reset signal Reset, respectively. Taking a logic chip with an active high external Reset signal as an example, when the external Reset signal reset_ext is pulled high, the internal n D flip-flops dff_1 to dff_n are all Reset. The reset terminals of the n D flip-flops dff_1 to dff_n are connected to the internal reset node, and thus the internal reset node has a parasitic capacitance (not shown) thereon, the magnitude of which is related to the number of D flip-flops inside the chip.

In this embodiment, the external Reset signal reset_ext has a first pulse width, for example, a pulse width tw=2ns of the external Reset signal reset_ext, and the internal Reset signal Reset has a second pulse width greater than the first pulse width. The Reset circuit 210 of the present invention reduces the timing requirement of the Reset of the internal circuit of the chip by expanding the external Reset signal reset_ext with smaller pulse width into the internal Reset signal Reset with larger pulse width, thereby effectively resetting the chip without increasing the dynamic power consumption of the circuit.

Fig. 4 shows a circuit schematic of a reset circuit according to a first embodiment of the invention. In an exemplary embodiment, the active level of the external Reset signal reset_ext is high, and as shown in fig. 4, the Reset circuit 210 of this embodiment includes a hysteresis comparison module 211 and a logic module 212. The hysteresis comparison module 211 is configured to obtain a first voltage signal Va according to an external Reset signal reset_ext, and compare the first voltage signal Va with a set threshold voltage to generate a second voltage signal Vb. The logic module 212 is connected to a parasitic capacitor Cpar at an internal Reset node of the chip, and is configured to charge and discharge the parasitic capacitor Cpar according to a logic operation result of the external Reset signal reset_ext and the second voltage signal Vb, so as to generate the internal Reset signal Reset.

Further, the hysteresis comparison module 211 includes a signal conversion unit 2101, a charge-discharge unit 2102 and a hysteresis comparator 2103. Wherein the signal conversion unit 2101 is configured to convert the external Reset signal reset_ext into an intermediate Reset signal. The charge-discharge unit 2102 is connected to a node a, and is configured to charge and discharge the node a according to the intermediate reset signal, so as to generate the first voltage signal Va. The hysteresis comparator 2103 has a hysteresis characteristic of a threshold voltage, and the hysteresis comparator 2103 is configured to compare the first voltage signal Va with an internal threshold voltage and generate the second voltage signal Vb according to a comparison result.

For example, the signal conversion unit 2101 includes an inverter INV1, and the intermediate Reset signal and the external Reset signal reset_ext are mutually inverted signals.

For example, the charge-discharge unit 2102 includes an NMOS transistor Mn1, a PMOS transistor Mp1, a resistor R1, and a capacitor C1. The source of the PMOS transistor Mp1 is connected to the power supply voltage VDD, the gate of the PMOS transistor Mp1 is connected to the output of the inverter INV1, and the drain of the PMOS transistor Mp1 is connected to the node a. The first end of the resistor R1 is connected with the node A, the second end of the resistor R1 is connected with the drain electrode of the NMOS tube Mn1, the grid electrode of the NMOS tube Mn1 is connected with the output of the inverter INV1, and the source electrode of the NMOS tube Mn1 is connected with the ground. The first terminal of the capacitor C1 is connected to the power supply voltage VDD, and the second terminal of the capacitor C1 is connected to the node a.

The hysteresis comparator 2103 is implemented by a schmitt trigger SMIT1, for example, having a positive threshold voltage and a negative threshold voltage with a hysteresis interval therebetween.

Further, the logic module 212 includes an OR circuit OR1, one input terminal of the OR circuit OR1 is configured to receive the second voltage signal Vb, the other input terminal of the OR circuit OR1 is configured to receive the external Reset signal reset_ext, the OR circuit OR1 is configured to perform an OR logic operation on the second voltage signal Vb and the external Reset signal reset_ext, and charge and discharge the parasitic capacitor Cpar according to an operation result, so as to generate the internal Reset signal Reset.

Fig. 5a to 5c are schematic waveforms of an external reset signal, a first voltage signal and an internal reset signal, respectively, according to an embodiment of the present invention. As shown in fig. 5a to 5c, when the external Reset signal reset_ext changes from a low level to a high level, the OR circuit OR1 inverts to charge the parasitic capacitance Cpar. Meanwhile, the output of the inverter INV1 is changed into low level, the PMOS tube MP1 is turned on, and the NMOS tube Mn1 is turned off. In this embodiment, by setting the width-to-length ratio of the PMOS transistor Mp1 to be relatively large, the node a can be quickly pulled up to a high level by the PMOS transistor Mp1, and when the first voltage signal Va at the node a is higher than the forward threshold voltage of the schmitt trigger SMIT1, the output of the schmitt trigger SMIT1, that is, the second voltage signal Vb becomes a high level, so as to maintain the state of charging the parasitic capacitor Cpar.

After the pulse of the external Reset signal reset_ext is ended, the external Reset signal reset_ext is changed from high level to low level, the output of the inverter INV1 is changed to high level, the PMOS transistor Mp1 is turned off, the NMOS transistor Mn1 is turned on, and the node a is discharged through the series connection of the resistor R1 and the impedance of the NMOS transistor Mn 1. The resistance value of the resistor R1 is far greater than the impedance of the NMOS transistor Mn1, and the discharge time constant of the node a is approximately R1×c1. When the voltage of the node a decreases to the negative threshold voltage of the schmitt trigger SMIT1, as shown in fig. 5b, the output of the schmitt trigger SMIT1 is inverted, i.e., the second voltage signal Vb becomes a low level, and the output of the OR circuit OR1 is inverted to discharge the parasitic capacitance Cpar.

In the present embodiment, the hysteresis characteristic of the schmitt trigger SMIT1 has an advantage in the case where the voltage at the node a fluctuates greatly, which can prevent the output signal from being frequently switched due to a minute change in the input signal, thereby improving the stability and reliability of the system.

Assuming that the time required for the node a to be discharged to the negative threshold voltage of the schmitt trigger SMIT1 is td (the time td is proportional to the discharge time constant R1 of the charge-discharge unit 2102, C1), and the time required for the OR circuit OR1 to charge the parasitic capacitor Cpar to the high level at which the internal Reset signal Reset can be effectively Reset is trst, the high level at which the internal Reset signal Reset can be effectively Reset can be ensured by only adjusting the resistance value of the resistor R1 so that the time td is greater than the time trst, and thus the chip can be effectively Reset.

It should be noted that, the time td is not changed by adjusting the capacitance value of the capacitor C1 in the above process because: when the PMOS transistor Mp1 is turned on, the voltage at the node a needs to be pulled up to the forward threshold voltage of the schmitt trigger SMIT1 within the effective pulse time (e.g., 2 ns) of the external Reset signal reset_ext, and if the capacitance value of the capacitor C1 is too large, this time becomes long, and even the voltage at the node a may not be pulled up to the forward threshold voltage of the schmitt trigger SMIT1 within a specified time, so the capacitance value of the capacitor C1 is not too large.

Fig. 5a and 5c show waveforms of the external Reset signal reset_ext and the internal Reset signal Reset, respectively, according to an embodiment of the invention. In fig. 5c, the solid line represents the waveform of the internal Reset signal Reset when the parasitic capacitance Cpar is small, and the broken line represents the waveform of the internal Reset signal Reset when the parasitic capacitance Cpar is large. As shown in fig. 5c, when the external Reset signal reset_ext with a pulse width time of 2ns as shown in fig. 5a is applied to the Reset pin of the chip, the charging time of the internal Reset signal Reset is equal to the sum of time tw and time td, and the highest voltage of the internal Reset signal Reset can exceed the high level of the chip effective Reset, that is, the chip can be effectively Reset, no matter the parasitic capacitance Cpar is larger or smaller.

In addition, in the embodiment, since the series impedance of the NMOS Mn1 and the resistor R1 is larger, and the schmitt trigger SMIT1 can be of a minimum size, the circuit does not increase the dynamic power consumption of the circuit, and the integrity of the power supply is not affected.

Fig. 6 shows a circuit schematic of a reset circuit according to a second embodiment of the invention. In another exemplary embodiment, the active level of the external Reset signal reset_ext is low, and as shown in fig. 6, the Reset circuit 310 of this embodiment also includes a hysteresis comparison module 311 and a logic module 312. The hysteresis comparison module 311 is configured to obtain a first voltage signal Va according to an external Reset signal reset_ext, and compare the first voltage signal Va with a set threshold voltage to generate a second voltage signal Vb. The logic module 312 is connected to a parasitic capacitor Cpar at an internal Reset node of the chip, and is configured to charge and discharge the parasitic capacitor Cpar according to a logic operation result of the external Reset signal reset_ext and the second voltage signal Vb, so as to generate the internal Reset signal Reset.

Further, the hysteresis comparison module 311 includes a signal conversion unit 3101, a charge-discharge unit 3102, a hysteresis comparator 3103, and an inverter INV2. Wherein the signal conversion unit 3101 is configured to convert the external Reset signal reset_ext into an intermediate Reset signal. The charge and discharge unit 3102 is connected to a node a, and is configured to charge and discharge the node a according to the intermediate reset signal, so as to generate the first voltage signal Va. The hysteresis comparator 3103 has a hysteresis characteristic of a threshold voltage, and the hysteresis comparator 3103 is configured to compare the first voltage signal Va with an internal threshold voltage. An input of the inverter INV2 is connected to an output of the hysteresis comparator 3103 for generating the second voltage signal Vb from an output of the hysteresis comparator 3103.

For example, the signal converting unit 3101 includes a buffer B1, and the intermediate Reset signal and the external Reset signal reset_ext are in-phase signals.

For example, the charge-discharge unit 3102 includes an NMOS transistor Mn1, a PMOS transistor Mp1, a resistor R1, and a capacitor C1. The source of the PMOS tube Mp1 is connected with the power supply voltage VDD, the grid of the PMOS tube Mp1 is connected with the output of the buffer B1, and the drain of the PMOS tube Mp1 is connected with the node A. The first end of the resistor R1 is connected with the node A, the second end of the resistor R1 is connected with the drain electrode of the NMOS tube Mn1, the grid electrode of the NMOS tube Mn1 is connected with the output of the buffer B1, and the source electrode of the NMOS tube Mn1 is connected with the ground. The first terminal of the capacitor C1 is connected to the power supply voltage VDD, and the second terminal of the capacitor C1 is connected to the node a.

The hysteresis comparator 3103 is implemented by a schmitt trigger SMIT2, for example, having a positive threshold voltage and a negative threshold voltage with a hysteresis interval therebetween.

Further, the logic block 312 includes an AND circuit AND1, one input terminal of the AND circuit AND1 is configured to receive the second voltage signal Vb, the other input terminal of the AND circuit AND1 is configured to receive the external Reset signal reset_ext, the AND circuit AND1 is configured to perform an AND logic operation on the second voltage signal Vb AND the external Reset signal reset_ext, AND charge AND discharge the parasitic capacitor Cpar according to an operation result, so as to generate the internal Reset signal Reset.

In the present embodiment, when the external Reset signal reset_ext changes from the high level to the low level, the AND circuit AND1 inverts to discharge the parasitic capacitance Cpar. Meanwhile, the output of the buffer B1 is changed into a low level, the PMOS tube MP1 is turned on, and the NMOS tube Mn1 is turned off. In this embodiment, by setting the width-to-length ratio of the PMOS transistor Mp1 to be relatively large, the node a can be quickly pulled up to a high level by the PMOS transistor Mp1, when the first voltage signal Va at the node a is higher than the forward threshold voltage of the schmitt trigger SMIT2, the output of the schmitt trigger SMIT2 becomes a high level, and then the second voltage signal Vb becomes a low level through the inversion of the inverter INV2, so as to maintain the state of discharging the parasitic capacitance Cpar.

After the pulse of the external Reset signal reset_ext is ended, the external Reset signal reset_ext is changed from low level to high level, the output of the buffer B1 is changed to high level, the PMOS transistor Mp1 is turned off, the NMOS transistor Mn1 is turned on, and the node a discharges in series through the impedance of the resistor R1 and the NMOS transistor Mn 1. The resistance value of the resistor R1 is far greater than the impedance of the NMOS transistor Mn1, and the discharge time constant of the node a is approximately R1×c1. When the voltage of the node a decreases to the negative threshold voltage of the schmitt trigger SMIT2, the output of the schmitt trigger SMIT2 is inverted to a low level, the second voltage signal Vb becomes a high level through the inversion of the inverter INV2, AND the AND circuit AND1 charges the parasitic capacitance Cpar according to the external Reset signal reset_ext of the high level AND the second voltage signal Vb.

Also, the hysteresis characteristic of the schmitt trigger SMIT2 has an advantage in the case that the voltage at the node a fluctuates greatly, which can prevent the output signal from being frequently switched due to a minute change in the input signal, thereby improving the stability and reliability of the system.

As described above, by adjusting the resistance value of the resistor R1 in the charge-discharge unit 3102, the time td required for the node a to be discharged to the negative threshold voltage of the schmitt trigger SMIT2 can be made longer than the time trst required for the AND circuit AND1 to discharge the parasitic capacitance Cpar to the low level at which the internal Reset signal Reset can be effectively Reset, the internal Reset signal Reset can be ensured to reach the low level at which the effective Reset can be performed, AND the chip can be effectively Reset.

Therefore, the reset circuit provided by the embodiment of the invention is effective not only when aiming at the external reset signal with high level, but also when aiming at the external reset signal with low level, the chip can be effectively reset, and the dynamic power consumption of the circuit is not increased.

In summary, the embodiment of the invention provides a reset circuit for a logic chip, which includes a hysteresis comparison module and a logic module, wherein the hysteresis comparison module is used for obtaining a first voltage signal according to an external reset signal and comparing the first voltage signal with a set threshold voltage to generate a second voltage signal, and the logic module is connected with a parasitic capacitor at an internal reset node and is used for charging and discharging the parasitic capacitor according to the logic operation results of the external reset signal and the second voltage signal to generate an internal reset signal. The reset circuit of the invention reduces the time sequence requirement of the reset of the internal circuit of the chip by expanding the external reset signal with smaller pulse width into the internal reset signal with larger pulse width, so that the internal reset signal can reach the level required by effective reset, thereby effectively resetting the chip on the premise of not increasing the dynamic power consumption of the circuit.

It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present invention. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state (e.g., "or") of the signal depends on whether positive or negative logic is used.

Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the following claims.

Claims (10)

1. A reset circuit for a logic chip for converting an external reset signal to an internal reset signal, comprising:

the hysteresis comparison module is used for obtaining a first voltage signal according to the external reset signal and comparing the first voltage signal with a set threshold voltage to generate a second voltage signal; and

a logic module connected with the parasitic capacitance at the internal reset node and used for charging and discharging the parasitic capacitance according to the logic operation result of the external reset signal and the second voltage signal so as to generate the internal reset signal,

wherein the external reset signal has a first pulse width and the internal reset signal has a second pulse width that is greater than the first pulse width.

2. The reset circuit of claim 1, wherein the second voltage signal becomes an inactive level after a set delay time when the external reset signal changes from an active level to an inactive level,

the logic module is configured to charge or discharge the parasitic capacitance when the external reset signal is at an active level, and to discharge or charge the parasitic capacitance when the external reset signal and the second voltage signal are both at an inactive level,

wherein the delay time is greater than a time required for the logic module to charge or discharge the parasitic capacitance to a high level or a low level such that the internal reset signal reaches an effective reset.

3. The reset circuit of claim 2, wherein the hysteresis comparison module comprises:

a signal conversion unit for converting the external reset signal into an intermediate reset signal;

the charge-discharge unit is connected with the first node and is used for charging and discharging the first node according to the intermediate reset signal so as to generate the first voltage signal; and

and the hysteresis comparator is used for comparing the first voltage signal with the threshold voltage and generating the second voltage signal according to a comparison result.

4. The reset circuit of claim 3, wherein the charge-discharge unit discharges the first node when the external reset signal changes from an active level to an inactive level, and the second voltage signal changes to an inactive level when the first voltage signal decreases to a negative-going threshold voltage of the hysteresis comparator,

wherein the set delay time is equal to a period between when the charge-discharge unit starts discharging the first node until the first voltage signal decreases to the negative-going threshold voltage.

5. The reset circuit of claim 4, wherein the charge-discharge unit comprises:

the first end of the PMOS tube is connected with the power supply voltage, the second end of the PMOS tube is connected with the first node, and the control end of the PMOS tube is connected with the intermediate reset signal;

a resistor, a first end of which is connected with the first node;

the first end of the NMOS tube is connected with the second end of the resistor, the second end of the NMOS tube is connected with the ground, and the control end of the NMOS tube is connected with the intermediate reset signal; and

and the first end of the capacitor is connected with the power supply voltage, and the second end of the capacitor is connected with the first node.

6. The reset circuit of claim 5, wherein an active level of the external reset signal is a high level, the signal conversion unit includes a first inverter, and the intermediate reset signal and the external reset signal are mutually inverted signals.

7. The reset circuit of claim 6, wherein the logic module comprises an or circuit to or the second voltage signal with the external reset signal.

8. The reset circuit of claim 4, wherein the active level of the external reset signal is a low level, the signal conversion unit includes a buffer, and the intermediate reset signal and the external reset signal are in-phase signals,

the hysteresis comparison module also comprises a second inverter, the input of the second inverter is connected with the output of the hysteresis comparator and is used for obtaining the second voltage signal according to the output of the hysteresis comparator,

the logic module comprises an AND gate circuit, and the AND gate circuit is used for performing AND logic operation on the second voltage signal and the external reset signal.

9. A reset circuit according to claim 3, wherein the hysteresis comparator is implemented by a schmitt trigger.

10. A logic chip comprising the reset circuit of any one of claims 1-9 for generating an internal reset signal from an external reset signal applied by a reset pin of the logic chip.