CN110943496B - Charging and discharging circuit and oscillator - Google Patents
Charging and discharging circuit and oscillator Download PDFInfo
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- CN110943496B CN110943496B CN201811109495.6A CN201811109495A CN110943496B CN 110943496 B CN110943496 B CN 110943496B CN 201811109495 A CN201811109495 A CN 201811109495A CN 110943496 B CN110943496 B CN 110943496B
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Abstract
The embodiment of the invention provides a charge and discharge circuit and an oscillator, wherein the charge and discharge circuit comprises: a reference voltage generating unit, a charging unit, and a discharging unit; the reference voltage generating unit is used for outputting the reference voltage through a reference voltage output end after the reference voltage generating unit generates the reference voltage; the discharging unit is used for outputting comparison voltage at a comparison voltage output end according to the clock signal received by the clock input end; the charging unit is used for charging the comparison voltage output end; the discharge unit is connected with the grounding terminal. In the charging and discharging circuit in the embodiment of the invention, in the charging process, even if noise occurs in a power supply end, as the clock signal is connected into the discharging unit, the charging and discharging time of the charging and discharging circuit is kept unchanged, and when the charging and discharging circuit is applied to an oscillator, the clock period output by the oscillator can be kept unchanged; thereby avoiding or reducing fluctuations in the period and duty cycle of the oscillator circuit output clock.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a charging and discharging circuit and an oscillator.
Background
A circuit capable of generating an oscillating current, which is an alternating current and whose magnitude and direction vary with the period, is generally called an oscillating circuit.
In the prior art, when an oscillation circuit is built, two comparators are usually adopted: a comparator A and a comparator B, wherein the comparator A usually has two input terminals, one input terminal is used for inputting a reference voltage VREF11, the other input terminal is used for inputting a periodically-changed voltage V11, and the comparator A has a corresponding output according to the comparison result of V11 and VREF 11; the comparator B usually has two input terminals, wherein one input terminal is used for inputting a reference voltage VREF22, the other input terminal is used for inputting a periodically-varying voltage V22, and the comparator B has a corresponding output according to the comparison result of V22 and VREF 22; the oscillator circuit may then generate a periodically varying clock based on the different outputs of comparator a and comparator B.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: in the oscillation circuit in the prior art, the phenomenon that the period and duty ratio of an output clock fluctuate greatly often occurs, so that the output of the oscillation circuit is unstable.
Disclosure of Invention
In view of the above problems, a charging and discharging circuit according to an embodiment of the present invention is provided, which is applied to an oscillator to avoid or reduce fluctuations in the period and duty ratio of an output clock.
According to a first aspect of the present invention, there is provided a charge and discharge circuit comprising:
a reference voltage generating unit, a charging unit, and a discharging unit;
the reference voltage generating unit comprises a reference voltage output end, and the reference voltage output end is used for outputting the reference voltage generated by the reference voltage generating unit;
the discharge unit includes: the discharging unit is used for outputting comparison voltage at the comparison voltage output end according to the clock signal received by the clock input end;
the charging unit is connected with a power supply end and the comparison voltage output end and is used for charging the comparison voltage output end;
the discharge unit is connected with a grounding terminal.
According to a second aspect of the present invention, there is provided an oscillator comprising:
the charge-discharge circuit comprises a first charge-discharge circuit, a second charge-discharge circuit, a first comparator, a second comparator and an RS trigger;
wherein the first charge and discharge circuit includes: a first reference voltage output terminal, a first comparison voltage output terminal, a first clock input terminal; the second charge and discharge circuit includes: a second reference voltage output terminal, a second comparison voltage output terminal, and a second clock input terminal; the first comparator includes: a first reference voltage input terminal, a first comparison output terminal; the second comparator includes: a second reference voltage input terminal, a second comparison voltage input terminal, and a second comparison output terminal; the RS flip-flop includes: the first trigger input end, the second trigger input end, the first clock output end and the second clock output end;
the first reference voltage output end is connected with the first reference voltage input end;
the first comparison voltage output end is connected with the first comparison voltage input end;
the second reference voltage output end is connected with the second reference voltage input end;
the second comparison voltage output end is connected with the second comparison voltage input end;
the first comparison output end is connected with the first trigger input end;
the second comparison output end is connected with the second trigger input end;
the first clock output end is connected with the first clock input end;
the second clock output end is connected with the second clock input end;
the first charge and discharge circuit further includes: the device comprises a first reference voltage generating unit, a first charging unit and a first discharging unit;
the first charging unit is connected with a first charging power supply and the first comparison voltage output end;
the first discharge unit is connected with a first grounding end, the first clock output end and the first comparison voltage output end;
the second charge and discharge circuit further includes: a second reference voltage generating unit, a second charging unit, a second discharging unit;
the second charging unit is connected with a second charging power supply and the second comparison voltage output end;
the second discharge unit is connected to a second ground terminal, the second clock output terminal, and the second comparison voltage output terminal.
In the charging and discharging circuit in the embodiment of the invention, in the charging process, even if noise occurs in the power supply end, for example, the voltage of the power supply end rises, the voltage of the reference voltage output end also rises, and as the clock signal is connected into the discharging unit, the charging current increases in the same proportion, the charging and discharging time of the charging and discharging circuit is kept unchanged, and when the charging and discharging circuit is applied to an oscillator, the clock period output by the oscillator can be kept unchanged; thereby avoiding or reducing fluctuations in the period and duty cycle of the oscillator circuit output clock.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a charging/discharging circuit according to an embodiment of the present invention;
FIG. 2 is an oscillator circuit according to an embodiment of the present invention;
FIG. 3 is a prior art charge and discharge circuit;
FIG. 4 is a timing diagram of the operation of a prior art oscillator circuit;
FIG. 5 is a schematic diagram of the effect of power supply noise on a charging unit of the prior art;
FIG. 6 is another charging/discharging circuit according to an embodiment of the present invention;
fig. 7 is an oscillator circuit according to an embodiment of the present invention;
FIG. 8 is a timing diagram illustrating the operation of an oscillator circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating that the power supply noise does not affect the charging unit according to the embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 1, a charge and discharge circuit is shown.
The charge and discharge circuit in the embodiment of the present invention may be applied to an oscillator, and the oscillator circuit may be specifically shown in fig. 2, where 1 and 2 in the block diagram are charge and discharge circuits, 3 and 4 are comparators, 5 is RS flip-flop logic, and the oscillator generates output clocks OUT and OUTB.
After a lot of experiments and researches, the applicant finds that in the prior art, the oscillation circuit often has a phenomenon of large fluctuation of the period and the duty ratio of an output clock, and a clock signal is usually connected to a charging module when a charging and discharging unit is arranged in an oscillator. As shown in fig. 3, VREFX is a reference voltage output terminal of the charge/discharge unit in the prior art, and VX is a comparison voltage output terminal of the charge/discharge unit in the prior art; the clock signal is connected to the gate of the N-type transistor M3 as a charging unit.
When the oscillator circuit adopts the charge and discharge unit of the prior art, the comparison voltage of the charge and discharge unit 1 is V1, the comparison voltage of the charge and discharge unit 2 is V2, the working process is as shown in fig. 4, when OUT is low, the charge and discharge unit 1 is charged, V1 is initialized to VDD, and simultaneously OUTB is high, V2 is discharged. When V2 reaches VREFX, the OUT output is high, M2 mirrors the current, charging V1, and when VREFX is reached, the comparator is inverted, and reinitialized by the logic of the RS flip-flop. The charge and discharge unit 1 and the charge and discharge unit 2 alternately work to generate a clock with a duty ratio of 50% and generate a proper duty ratio.
In the process:
the charging current is I ═ VDD-VGS1)/(R9+ R10; VGS1 is the M3 turn-on voltage, and R9 and R10 are the resistances of the corresponding resistors in FIG. 3.
Charging voltage difference is dV ═ l R9
The period 2 × T ═ 2 × dv × C/I ═ 2 × R9 × C is independent of the supply voltage and the transistors, and is dependent only on the resistor R and the capacitor C.
However, when the power supply voltage varies during charging at V1 or V2, both the cycle and the duty cycle are severely affected. For example, as shown in fig. 5, at time t1, the power supply voltage becomes low and VREFX also becomes low, but the voltage V1 does not change, so the distance from V1 to VREFX becomes large, and the charging current becomes small, and since the clock signal is turned on to the charging circuit, V1 changes in a tendency to fall from VDD to VREFX, and assuming that the slope before the power supply voltage becomes low is k1, the charging current becomes small, and then the slope k2 becomes smaller than k1, so the charging time becomes long. As shown in fig. 5, at time t1, although the power supply voltage becomes high and VREFX also becomes high, the voltage V1 does not change, so that the distance from V1 to VREFX becomes small and the charging current becomes large. Resulting in a phenomenon in which the period and duty ratio of the output clock fluctuate greatly.
Based on this finding, in the embodiment of the present invention, as shown in fig. 1, the charge and discharge circuit includes:
a reference voltage generating unit 10, a charging unit 20, a discharging unit 30; the reference voltage generating unit 10 includes a reference voltage output terminal 11, configured to output a reference voltage through the reference voltage output terminal 11 after the reference voltage generating unit 10 generates the reference voltage; the discharge cell 30 includes: a comparison voltage output terminal 32, a clock input terminal 31, wherein the discharging unit 30 is configured to output a comparison voltage at the comparison voltage output terminal 32 according to a clock signal received at the clock input terminal 31; the charging unit 20 is connected to a power supply terminal and the comparison voltage output terminal 32, and is configured to charge the comparison voltage output terminal 32; the discharge unit 30 is connected to a ground terminal.
In the embodiment of the present invention, the clock signal input terminal 31 is disposed in the discharging unit 30, when the power source terminal voltage generates noise (becomes high or low), if the power source voltage becomes low, the reference voltage VREF generated by the reference voltage generating unit also becomes low in the embodiment of the present invention, and the voltage of the comparison voltage V1 does not change suddenly, and V1 keeps the original value, so the distance from V1 to VREF becomes large, and the charging current becomes small, and assuming that the slope before the power source voltage becomes low is k3, the slope k4 is further smaller than k3 after the charging current becomes small, but since the clock signal is connected to the discharging circuit 30, the voltage of the comparison voltage output terminal is a trend increasing from 0 to the reference voltage VREF, and the slowed slope just can make the charging time not change. When the power supply voltage is higher, VREF is also higher, and the voltage of V1 is unchanged, so that the distance from V1 to VREF is smaller, the charging current is larger, and the charging time is also unchanged based on similar reasons, thereby avoiding the phenomenon that the period of the output clock and the duty ratio are greatly fluctuated.
As a preferable mode of the embodiment of the present invention, as shown in fig. 1, the charging unit 20 includes: a first P-type transistor P1; the gate of the first P-type transistor P1 is connected to the reference voltage generating unit 10; the source of the first P-type transistor P1 is connected to the power supply terminal; the drain of the first P-type transistor P1 is connected to the comparison voltage output terminal.
The discharge cell 30 includes: a capacitor C, a first N-type transistor N1; one end of the capacitor C is connected to the comparison voltage output terminal 32; the other end of the capacitor C is connected with the grounding end; the gate of the first N-type transistor N1 is connected to the clock output 32; the source of the first N-type transistor N1 is connected with the ground terminal; the drain of the first N-type transistor N1 is connected to the comparison voltage output terminal 31.
As a specific implementation manner of the embodiment of the present invention, the reference voltage generating unit 10 includes: a first resistor R1, a second resistor R2 and a second P-type transistor P2; the gate of the second P-type transistor P2 is connected with the gate of the first P-type transistor P1 and the drain of the second P-type transistor P2; the source of the second P-type transistor P2 is connected to the power supply terminal; the drain electrode of the second P-type transistor P2 is connected with one end of the first resistor R1; the other end of the first resistor R1 is connected with one end of the second resistor R2 and is connected with the reference voltage output end 11; the other end of the second resistor R2 is connected to the ground terminal.
As another specific implementation manner of the embodiment of the present invention, as shown in fig. 6, the reference voltage generating unit includes: a third resistor R3, a fourth resistor R4, a third P-type transistor P3, a fourth P-type transistor P4, a second N-type transistor N2 and a third N-type transistor N3.
Wherein the gate of the third P-type transistor P3 is connected to the gate of the first P-type transistor P1, the gate of the fourth P-type transistor P4, and the drain of the third P-type transistor P3; the source of the third P-type transistor P3 is connected to the power supply terminal; the drain of the third P-type transistor P3 is connected with the drain of the third N-type transistor N3; the source of the fourth P-type transistor P4 is connected to the power supply terminal; the drain of the fourth P-type transistor P4 is connected to one end of the fourth resistor R4 and the reference voltage output terminal 11; the other end of the fourth resistor R4 is connected to the ground terminal; the source of the second N-type transistor N2 and the third N-type transistor N3 are connected to the ground terminal; the gate of the third N-type transistor N3 is connected with the gate of the second N-type transistor N2 and the drain of the second N-type transistor N2; the drain of the second N-type transistor N2 is connected with one end of the third resistor R3; the other end of the third resistor R3 is connected to the power supply terminal.
In a specific application, the transistor may be a MOS transistor or other field effect transistor, and the embodiment of the present invention is not limited in particular.
In the charging and discharging circuit in the embodiment of the invention, in the charging process, even if noise occurs in the power supply end, for example, the voltage of the power supply end rises, the voltage of the reference voltage output end also rises, and as the clock signal is connected into the discharging unit, the charging current increases in the same proportion, the charging and discharging time of the charging and discharging circuit is kept unchanged, and when the charging and discharging circuit is applied to an oscillator, the clock period output by the oscillator can be kept unchanged; thereby avoiding or reducing fluctuations in the period and duty cycle of the oscillator circuit output clock.
Example two
Referring to fig. 7, an oscillator is shown.
The oscillator includes: a first charge and discharge circuit 71, a second charge and discharge circuit 72, a first comparator 73, a second comparator 74, and an RS flip-flop 75.
Wherein the first charge and discharge circuit 71 includes: a first reference voltage output terminal 711, a first comparison voltage output terminal 712, a first clock input terminal 713; the second charge and discharge circuit 72 includes: a second reference voltage output 721, a second comparison voltage output 722, a second clock input 723; the first comparator 73 includes: a first reference voltage input 731, a first comparison voltage input 732, a first comparison output 733; the second comparator 74 includes: a second reference voltage input 741, a second comparison voltage input 742, and a second comparison output 743; the RS flip-flop 75 includes: a first trigger input 751, a second trigger input 752, a first clock output 753, a second clock output 754; the first reference voltage output terminal 711 is connected to the first reference voltage input terminal 731; the first comparison voltage output 712 is connected to the first comparison voltage input 732; the second reference voltage output end 721 is connected to the second reference voltage input end 741; the second comparison voltage output terminal 722 is connected to the second comparison voltage input terminal 742; the first comparison output 733 is connected to the first trigger input 751; the second comparison output 743 is connected to the second trigger input 752; the first clock output port 753 being coupled to the first clock input port 713; the second clock output 754 is connected to the second clock input 723; the first charge and discharge circuit 71 further includes: the device comprises a first reference voltage generating unit, a first charging unit and a first discharging unit; the first charging unit is connected with a first charging power supply and the first comparison voltage output end; the first discharge unit is connected with a first grounding end, the first clock output end and the first comparison voltage output end; the second charge and discharge circuit further includes: a second reference voltage generating unit, a second charging unit, a second discharging unit; the second charging unit is connected with a second charging power supply and the second comparison voltage output end; the second discharge unit is connected to a second ground terminal, the second clock output terminal, and the second comparison voltage output terminal.
In the embodiment of the present invention, both the first charge and discharge circuit and the second charge and discharge circuit may be any one of the charge and discharge circuits of the present invention in the first embodiment, and have the same components and connection relationships as those of the charge and discharge circuit of the first embodiment.
As a preferable mode of the embodiment of the present invention, the first charging unit includes: a first P-type transistor; the grid electrode of the first P-type transistor is connected with the first reference voltage generation unit; the source electrode of the first P-type transistor is connected with the first charging power supply; the drain electrode of the first P-type transistor is connected with the first comparison voltage output end. The first discharge unit includes: a first capacitor, a first N-type transistor; one end of the first capacitor is connected with the first comparison voltage output end; the other end of the first capacitor is connected with the first grounding end; the grid electrode of the first N-type transistor is connected with the first clock output end; the source electrode of the first N-type transistor is connected with the first grounding end; and the drain electrode of the first N-type transistor is connected with the first comparison voltage output end.
As a specific implementation manner of the embodiment of the present invention, the first reference voltage generating unit includes: the first resistor, the second resistor and the second P-type transistor; the grid electrode of the second P-type transistor is connected with the grid electrode of the first P-type transistor and the drain electrode of the second P-type transistor; the source electrode of the second P-type transistor is connected with the first charging power supply; the drain electrode of the second P-type transistor is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the second resistor and is connected with the first reference voltage output end; the other end of the second resistor is connected to the first ground terminal.
As another specific implementation manner of the embodiment of the present invention, the first reference voltage generating unit includes: the third resistor, the fourth resistor, the third P-type transistor, the fourth P-type transistor, the second N-type transistor and the third N-type transistor; the grid electrode of the third P-type transistor is connected with the grid electrode of the first P-type transistor, the grid electrode of the fourth P-type transistor and the drain electrode of the third P-type transistor; the source electrode of the third P-type transistor is connected with the first charging power supply; the drain electrode of the third P-type transistor is connected with the drain electrode of the third N-type transistor; the source electrode of the fourth P-type transistor is connected with the first charging power supply; the drain electrode of the fourth P-type transistor is connected with one end of the fourth resistor and the first reference voltage output end; the other end of the fourth resistor is connected with the first grounding end; the source electrode of the second N-type transistor and the third N-type transistor are connected with the first grounding end; the grid electrode of the third N-type transistor is connected with the grid electrode of the second N-type transistor and the drain electrode of the second N-type transistor; the drain electrode of the second N-type transistor is connected with one end of the third resistor; the other end of the third resistor is connected with the first charging power supply.
As a preferable aspect of the embodiment of the present invention, the second charging unit includes: a fifth P-type transistor; the grid electrode of the fifth P-type transistor is connected with the second reference voltage generation unit; the source electrode of the fifth P-type transistor is connected with the second charging power supply; and the drain electrode of the fifth P-type transistor is connected with the second comparison voltage output end. The second discharge unit includes: a second capacitor, a fourth N-type transistor; one end of the second capacitor is connected with the second comparison voltage output end; the other end of the second capacitor is connected with the second grounding end; the grid electrode of the fourth N-type transistor is connected with the second clock output end; a source of the fourth N-type transistor is connected to the second ground terminal; and the drain electrode of the fourth N-type transistor is connected with the second comparison voltage output end.
As a specific implementation manner of the embodiment of the present invention, the second reference voltage generating unit includes: a fifth resistor, a sixth resistor, and a sixth P-type transistor; the grid electrode of the sixth P-type transistor is connected with the grid electrode of the fifth P-type transistor and the drain electrode of the sixth P-type transistor; the source electrode of the sixth P-type transistor is connected with the second charging power supply; the drain electrode of the sixth P-type transistor is connected with one end of the fifth resistor; the other end of the fifth resistor is connected with one end of the sixth resistor and is connected with the second reference voltage output end; the other end of the sixth resistor is connected to the second ground terminal.
As another specific implementation manner of the embodiment of the present invention, the second reference voltage generating unit includes: a seventh resistor, an eighth resistor, a seventh P-type transistor, an eighth P-type transistor, a fifth N-type transistor, and a sixth N-type transistor; the grid electrode of the seventh P-type transistor is connected with the grid electrode of the second P-type transistor, the grid electrode of the eighth P-type transistor and the drain electrode of the seventh P-type transistor; the source electrode of the seventh P-type transistor is connected with the second charging power supply; the drain electrode of the seventh P-type transistor is connected with the drain electrode of the sixth N-type transistor; the source electrode of the eighth P-type transistor is connected with the second charging power supply; the drain electrode of the eighth P-type transistor is connected with one end of the eighth resistor and the second reference voltage output end; the other end of the eighth resistor is connected with the second grounding end; the source electrode of the fifth N-type transistor and the sixth N-type transistor are connected with the second grounding end; the grid electrode of the sixth N-type transistor is connected with the grid electrode of the fifth N-type transistor and the drain electrode of the fifth N-type transistor; the drain electrode of the fifth N-type transistor is connected with one end of the seventh resistor; the other end of the seventh resistor is connected with the second charging power supply.
In the embodiment of the present invention, assuming that the reference voltages output by the first charge and discharge unit 71 and the second charge and discharge unit 72 are both VREF, the comparison voltage output by the first charge and discharge unit 71 is V1, the comparison voltage output by the second charge and discharge unit 72 is V2, the voltage output by the first comparator 73 is V3, the voltage output by the second comparator 74 is V4, and the clock signals OUT and OUTB output by the RS flip-flop are inverted voltages, the operation process of the oscillator according to the embodiment of the present invention may be as shown in fig. 8.
Specifically, in the first stage, when OUT is high, the discharging unit of the first charging and discharging unit 71 is turned on to keep V1 at 0, and at the same time, OUTB is low, the discharging unit of the second charging and discharging unit 72 is turned off, so that V2 starts to be charged from 0 through the charging unit in the second charging and discharging unit; when V2 is greater than VREF, the output voltage V4 of the second comparator 74 is inverted to a high level, and through logic triggering of the RS flip-flop 75, OUT is inverted to a low level, and OUTB is a high level; in the second stage, when OUTB is high, the discharging unit of the second charging and discharging unit 72 is turned on, pulling V2 low by 0, and at the same time, OUT is low, the discharging unit of the first charging and discharging unit 71 is blocked, so that V1 starts to be charged from 0 by the charging unit in the first charging and discharging unit; when V1 is greater than VREF, the output voltage V3 of the first comparator 73 is inverted to a high level, and through logic triggering of the RS flip-flop 75, OUT is inverted to a high level, and OUTB is a low level; and the process is circulated.
In the embodiment of the present invention, in the charging process of the first charge/discharge unit 71 or the second charge/discharge unit 72, assuming that the charging power VDD connected to the first charging power terminal generates noise (becomes higher or lower), as shown in fig. 9, if VDD becomes lower, VREF also becomes lower, and the voltage of V1 does not change, so the distance from V1 to VREF becomes larger, and the charging current becomes smaller, and assuming that the slope before the power voltage becomes lower is k5, after the charging current becomes smaller, the slope k6 is further smaller than k5, but V1 is a trend increasing from 0 to the reference voltage VREF, and the slope is slowed down to just make the charging time not change. If VDD becomes high, VREF also becomes high, and the voltage of V1 does not change, so the distance from V1 to VREF becomes small, and the charging current becomes large, and for similar reasons, the charging time also does not change, thereby avoiding the phenomenon that the cycle of the output clock and the duty ratio fluctuate greatly.
It should be noted that, for simplicity, the foregoing embodiments are described as a series of circuit combinations, but those skilled in the art should understand that the embodiments described in the specification are all preferred embodiments, and the related components are not necessarily essential to the invention.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
It should be noted that modifications and adaptations may occur to those skilled in the art without departing from the principles of the present invention and should be considered within the scope of the present invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The charging and discharging unit and the oscillator provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A charging and discharging circuit, comprising:
a reference voltage generating unit, a charging unit, and a discharging unit;
the reference voltage generating unit comprises a reference voltage output end, and the reference voltage output end is used for outputting the reference voltage generated by the reference voltage generating unit;
the discharge unit includes: the discharging unit is used for outputting comparison voltage at the comparison voltage output end according to the clock signal received by the clock input end;
the charging unit is connected with a power supply end and the comparison voltage output end and is used for charging the comparison voltage output end;
the discharge unit is connected with a grounding terminal;
the charging unit includes:
a first P-type transistor;
the grid electrode of the first P-type transistor is connected with the reference voltage generating unit;
the source electrode of the first P-type transistor is connected with the power supply end;
the drain electrode of the first P-type transistor is connected with the comparison voltage output end;
the reference voltage generating unit includes:
the first resistor, the second resistor and the second P-type transistor;
the grid electrode of the second P-type transistor is connected with the grid electrode of the first P-type transistor and the drain electrode of the second P-type transistor;
the source electrode of the second P-type transistor is connected with the power supply end;
the drain electrode of the second P-type transistor is connected with one end of the first resistor;
the other end of the first resistor is connected with one end of the second resistor and is connected with the reference voltage output end;
the other end of the second resistor is connected with the grounding end.
2. The circuit of claim 1, wherein the discharge unit comprises: a capacitor, a first N-type transistor;
one end of the capacitor is connected with the comparison voltage output end;
the other end of the capacitor is connected with the grounding end;
the grid electrode of the first N-type transistor is connected with the clock output end;
the source electrode of the first N-type transistor is connected with the grounding end;
and the drain electrode of the first N-type transistor is connected with the comparison voltage output end.
3. The circuit of claim 2, wherein the reference voltage generation unit comprises:
the third resistor, the fourth resistor, the third P-type transistor, the fourth P-type transistor, the second N-type transistor and the third N-type transistor;
the grid electrode of the third P-type transistor is connected with the grid electrode of the first P-type transistor, the grid electrode of the fourth P-type transistor and the drain electrode of the third P-type transistor;
the source electrode of the third P-type transistor is connected with the power supply end;
the drain electrode of the third P-type transistor is connected with the drain electrode of the third N-type transistor;
the source electrode of the fourth P-type transistor is connected with the power supply end;
the drain electrode of the fourth P-type transistor is connected with one end of the fourth resistor and the reference voltage output end;
the other end of the fourth resistor is connected with the grounding end;
the source electrode of the second N-type transistor and the third N-type transistor are connected with the grounding terminal;
the grid electrode of the third N-type transistor is connected with the grid electrode of the second N-type transistor and the drain electrode of the second N-type transistor;
the drain electrode of the second N-type transistor is connected with one end of the third resistor;
the other end of the third resistor is connected with the power supply end.
4. An oscillator, characterized in that the oscillator comprises: the charge-discharge circuit comprises a first charge-discharge circuit, a second charge-discharge circuit, a first comparator, a second comparator and an RS trigger;
wherein the first charge and discharge circuit includes: a first reference voltage output terminal, a first comparison voltage output terminal, a first clock input terminal; the second charge and discharge circuit includes: a second reference voltage output terminal, a second comparison voltage output terminal, and a second clock input terminal; the first comparator includes: a first reference voltage input terminal, a first comparison output terminal; the second comparator includes: a second reference voltage input terminal, a second comparison voltage input terminal, and a second comparison output terminal; the RS flip-flop includes: the first trigger input end, the second trigger input end, the first clock output end and the second clock output end;
the first reference voltage output end is connected with the first reference voltage input end;
the first comparison voltage output end is connected with the first comparison voltage input end;
the second reference voltage output end is connected with the second reference voltage input end;
the second comparison voltage output end is connected with the second comparison voltage input end;
the first comparison output end is connected with the first trigger input end;
the second comparison output end is connected with the second trigger input end;
the first clock output end is connected with the first clock input end;
the second clock output end is connected with the second clock input end;
the first charge and discharge circuit further includes: the device comprises a first reference voltage generating unit, a first charging unit and a first discharging unit;
the first charging unit is connected with a first charging power supply and the first comparison voltage output end;
the first discharge unit is connected with a first grounding end, the first clock output end and the first comparison voltage output end;
the second charge and discharge circuit further includes: a second reference voltage generating unit, a second charging unit, a second discharging unit;
the second charging unit is connected with a second charging power supply and the second comparison voltage output end;
the second discharge unit is connected with a second grounding end, the second clock output end and the second comparison voltage output end;
the first charging unit includes: a first P-type transistor;
the grid electrode of the first P-type transistor is connected with the first reference voltage generation unit;
the source electrode of the first P-type transistor is connected with the first charging power supply;
the drain electrode of the first P-type transistor is connected with the first comparison voltage output end;
the first reference voltage generating unit includes:
the first resistor, the second resistor and the second P-type transistor;
the grid electrode of the second P-type transistor is connected with the grid electrode of the first P-type transistor and the drain electrode of the second P-type transistor;
the source electrode of the second P-type transistor is connected with the first charging power supply;
the drain electrode of the second P-type transistor is connected with one end of the first resistor;
the other end of the first resistor is connected with one end of the second resistor and is connected with the first reference voltage output end;
the other end of the second resistor is connected to the first ground terminal.
5. The oscillator of claim 4,
the first discharge unit includes:
a first capacitor, a first N-type transistor;
one end of the first capacitor is connected with the first comparison voltage output end;
the other end of the first capacitor is connected with the first grounding end;
the grid electrode of the first N-type transistor is connected with the first clock output end;
the source electrode of the first N-type transistor is connected with the first grounding end;
and the drain electrode of the first N-type transistor is connected with the first comparison voltage output end.
6. The oscillator according to claim 5, wherein the first reference voltage generating unit comprises:
the third resistor, the fourth resistor, the third P-type transistor, the fourth P-type transistor, the second N-type transistor and the third N-type transistor;
the grid electrode of the third P-type transistor is connected with the grid electrode of the first P-type transistor, the grid electrode of the fourth P-type transistor and the drain electrode of the third P-type transistor;
the source electrode of the third P-type transistor is connected with the first charging power supply;
the drain electrode of the third P-type transistor is connected with the drain electrode of the third N-type transistor;
the source electrode of the fourth P-type transistor is connected with the first charging power supply;
the drain electrode of the fourth P-type transistor is connected with one end of the fourth resistor and the first reference voltage output end;
the other end of the fourth resistor is connected with the first grounding end;
the source electrode of the second N-type transistor and the third N-type transistor are connected with the first grounding end;
the grid electrode of the third N-type transistor is connected with the grid electrode of the second N-type transistor and the drain electrode of the second N-type transistor;
the drain electrode of the second N-type transistor is connected with one end of the third resistor;
the other end of the third resistor is connected with the first charging power supply.
7. The oscillator of claim 5, wherein the second charging unit comprises: a fifth P-type transistor;
the grid electrode of the fifth P-type transistor is connected with the second reference voltage generation unit;
the source electrode of the fifth P-type transistor is connected with the second charging power supply;
the drain electrode of the fifth P-type transistor is connected with the second comparison voltage output end;
the second discharge unit includes:
a second capacitor, a fourth N-type transistor;
one end of the second capacitor is connected with the second comparison voltage output end;
the other end of the second capacitor is connected with the second grounding end;
the grid electrode of the fourth N-type transistor is connected with the second clock output end;
a source of the fourth N-type transistor is connected to the second ground terminal;
and the drain electrode of the fourth N-type transistor is connected with the second comparison voltage output end.
8. The oscillator according to claim 7, wherein the second reference voltage generating unit comprises:
a fifth resistor, a sixth resistor, and a sixth P-type transistor;
the grid electrode of the sixth P-type transistor is connected with the grid electrode of the fifth P-type transistor and the drain electrode of the sixth P-type transistor;
the source electrode of the sixth P-type transistor is connected with the second charging power supply;
the drain electrode of the sixth P-type transistor is connected with one end of the fifth resistor;
the other end of the fifth resistor is connected with one end of the sixth resistor and is connected with the second reference voltage output end;
the other end of the sixth resistor is connected to the second ground terminal.
9. The oscillator according to claim 7, wherein the second reference voltage generating unit comprises:
a seventh resistor, an eighth resistor, a seventh P-type transistor, an eighth P-type transistor, a fifth N-type transistor, and a sixth N-type transistor;
the grid electrode of the seventh P-type transistor is connected with the grid electrode of the second P-type transistor, the grid electrode of the eighth P-type transistor and the drain electrode of the seventh P-type transistor;
the source electrode of the seventh P-type transistor is connected with the second charging power supply;
the drain electrode of the seventh P-type transistor is connected with the drain electrode of the sixth N-type transistor;
the source electrode of the eighth P-type transistor is connected with the second charging power supply;
the drain electrode of the eighth P-type transistor is connected with one end of the eighth resistor and the second reference voltage output end;
the other end of the eighth resistor is connected with the second grounding end;
the source electrode of the fifth N-type transistor and the sixth N-type transistor are connected with the second grounding end;
the grid electrode of the sixth N-type transistor is connected with the grid electrode of the fifth N-type transistor and the drain electrode of the fifth N-type transistor;
the drain electrode of the fifth N-type transistor is connected with one end of the seventh resistor;
the other end of the seventh resistor is connected with the second charging power supply.
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| CN201811109495.6A CN110943496B (en) | 2018-09-21 | 2018-09-21 | Charging and discharging circuit and oscillator |
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| CN102158202A (en) * | 2011-04-15 | 2011-08-17 | 上海大学 | High accuracy digital adjustable RC (Resistance Capacitance) oscillator |
| KR20160029593A (en) * | 2014-09-05 | 2016-03-15 | 삼성전자주식회사 | Oscillator and display driving circuit comprising thereof |
| CN105958943B (en) * | 2016-04-21 | 2018-12-04 | 新茂国际科技股份有限公司 | relaxation oscillator |
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| CN1848667A (en) * | 2005-04-04 | 2006-10-18 | 凌阳科技股份有限公司 | Ring oscillator for compensating voltage source offset |
| CN102324912A (en) * | 2011-08-13 | 2012-01-18 | 中科芯集成电路股份有限公司 | Current control oscillator |
| US9099994B2 (en) * | 2012-12-20 | 2015-08-04 | Silicon Laboratories Inc. | Relaxation oscillator |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |
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