CN117766402A

CN117766402A - Method for manufacturing semiconductor device, and electronic apparatus

Info

Publication number: CN117766402A
Application number: CN202311865728.6A
Authority: CN
Inventors: 唐建石; 杨慧敏; 李怡均; 杜宜威; 安然; 高滨; 钱鹤; 吴华强
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-03-26

Abstract

A method for manufacturing a semiconductor device, and an electronic apparatus. The method for manufacturing the semiconductor device comprises the following steps: preparing a transistor on a substrate, wherein a semiconductor layer of the transistor comprises indium-based oxide; forming a passivation protection layer covering the transistor on one side of the transistor far away from the substrate through a physical vapor deposition process; and forming a passivation layer on the side of the passivation protection layer away from the substrate. The method for manufacturing the semiconductor device can improve the performance and stability of the semiconductor device.

Description

Method for manufacturing semiconductor device, and electronic apparatus

Technical Field

Embodiments of the present disclosure relate to a method of manufacturing a semiconductor device, and an electronic apparatus.

Background

Monolithic three-dimensional integration is an advanced integrated circuit technology that aims to improve chip performance and functional density by vertically stacking multiple layers of devices. Monolithic three-dimensional integration techniques require post-compatible transistor technology to achieve efficient stacking and interconnection of multi-layer devices.

However, silicon-based devices such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, metal Oxide semiconductor Field effect transistors) and finfets (Fin Field effect transistors) are complex and costly to manufacture, and they typically require a single crystal silicon substrate to ensure device performance and reliability, which makes them difficult to achieve subsequent compatibility.

Disclosure of Invention

At least one embodiment of the present disclosure provides a method of manufacturing a semiconductor device, the method including: preparing a transistor on a substrate, wherein a semiconductor layer of the transistor comprises indium-based oxide; forming a passivation protection layer covering the transistor on one side of the transistor far away from the substrate through a physical vapor deposition process; and forming a passivation layer on one side of the passivation protection layer away from the substrate.

For example, the preparation method provided in an embodiment of the present disclosure further includes: and forming a silicon-based semiconductor device layer on the substrate through a semiconductor preparation process, wherein the substrate is a silicon substrate, and preparing the transistor on one side of the silicon-based semiconductor device layer far away from the substrate.

For example, in the preparation method provided in an embodiment of the present disclosure, the indium-based oxide includes IGZO or IGO.

For example, in the preparation method provided in an embodiment of the present disclosure, the passivation protection layer includes yttrium oxide or aluminum oxide.

For example, in the preparation method provided in an embodiment of the present disclosure, the physical vapor deposition process includes a sputtering process or an evaporation process.

For example, in the preparation method provided in an embodiment of the present disclosure, the forming a passivation layer on a side of the passivation protection layer away from the substrate includes: and forming a passivation layer on the side, away from the substrate, of the passivation protection layer through a chemical vapor deposition process.

For example, in the method for manufacturing according to an embodiment of the present disclosure, the passivation layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, or hafnium oxide.

For example, in the method of manufacturing provided in an embodiment of the present disclosure, the transistor is a back gate transistor.

For example, in a method for manufacturing a transistor provided in an embodiment of the present disclosure, the manufacturing a transistor on a substrate includes: forming a gate electrode on the substrate; covering a gate insulating layer on one side of the gate away from the substrate; forming the semiconductor layer on one side of the gate insulating layer away from the substrate; a source electrode and a drain electrode are formed on a side of the semiconductor layer remote from the substrate, wherein the source electrode and the drain electrode are spaced apart by a portion of the semiconductor layer that serves as a channel region.

For example, in the preparation method provided in an embodiment of the present disclosure, before the forming, by a physical vapor deposition process, a passivation protection layer covering the transistor on a side of the transistor away from the substrate, the method further includes: and carrying out annealing treatment, wherein the temperature range of the annealing treatment is 200-300 ℃.

At least one embodiment of the present disclosure provides a semiconductor device including: a substrate; a transistor formed on the substrate, wherein a semiconductor layer of the transistor includes indium-based oxide; a passivation protection layer formed by a physical vapor deposition process and covering one side of the transistor away from the substrate; and the passivation layer is covered on one side of the passivation protection layer away from the substrate.

For example, in the semiconductor device provided in an embodiment of the present disclosure, further includes: and the silicon-based semiconductor device layer is formed between the substrate and the transistor, wherein the substrate comprises a silicon substrate, and the transistor is formed on the side, away from the substrate, of the silicon-based semiconductor device layer.

For example, in the semiconductor device provided in an embodiment of the present disclosure, the transistor is a back gate transistor.

At least one embodiment of the present disclosure provides an electronic device including the semiconductor apparatus provided by any one of the embodiments of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1 is a schematic flow diagram illustrating a method for manufacturing a semiconductor device according to at least one embodiment of the present disclosure;

FIG. 2 illustrates a schematic diagram of a process flow for fabricating a transistor provided in accordance with at least one embodiment of the present disclosure;

fig. 3 illustrates a schematic structure of a transistor provided in at least one embodiment of the present disclosure;

FIG. 4 illustrates a transmission electron micrograph of a transistor fabricated by a fabrication method provided in accordance with at least one embodiment of the present disclosure;

FIG. 5 illustrates a performance comparison schematic of transistors fabricated using at least one embodiment of the present disclosure and transistors fabricated using other fabrication methods; and

fig. 6 illustrates a schematic block diagram of an electronic device provided by at least one implementation of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The monolithic three-dimensional integration technology vertically stacks multiple layers of heterogeneous or homogeneous semiconductor devices together through interlayer dielectric layers and vias (insulating layer vias) in the dielectric layers, and compared with a technology of stacking multiple chips together by adopting a silicon substrate and forming vias (silicon vias) in the silicon substrate, the monolithic three-dimensional integration technology can improve the integration level of the semiconductor devices in a three-dimensional space, and can place more transistors and other devices in a limited space, thereby realizing higher performance. In addition, the monolithic three-dimensional integration technology can also utilize the interlayer dielectric layer via hole with high density and low delay to carry out inter-module communication, thereby improving the speed and the efficiency of data transmission.

Compared with the traditional silicon-based transistor (silicon material is used as an active layer (or a semiconductor layer)), the indium-based oxide transistor (indium-based oxide is used as the active layer) has the characteristics of good post-process compatibility and the like, and can realize good compatibility with other semiconductor devices in post-process manufacture.

In monolithic three-dimensional integration technology, indium-based oxide transistors can be integrated into a chip as an important semiconductor device. Therefore, in the process of manufacturing the indium-based oxide transistor, the indium-based oxide transistor needs to be passivation-protected after manufacturing in order to ensure smooth subsequent processes.

However, the inventors of the present disclosure noted that the passivation layer growth manner may adversely affect the performance of the indium-based oxide transistor, and hydrogen atoms or hydrogen ions included in the passivation layer growth process may cause problems such as an increase in resistivity, a decrease in carrier mobility, and a threshold voltage shift of the indium-based oxide transistor, which greatly affect the performance of the indium-based oxide transistor.

At least one embodiment of the present disclosure provides a method for manufacturing a semiconductor device, and an electronic apparatus.

The preparation method of the semiconductor device provided by the embodiment of the disclosure comprises the following steps: preparing a transistor on a substrate, wherein a semiconductor layer of the transistor includes indium-based oxide; forming a passivation protection layer covering the transistor on one side of the transistor far away from the substrate through a physical vapor deposition process; and forming a passivation layer on the side of the passivation protection layer away from the substrate. The method for manufacturing the semiconductor device can improve the performance and stability of the semiconductor device.

Correspondingly, the semiconductor device provided by the embodiment of the disclosure comprises: a substrate, a transistor, a passivation protection layer and a passivation layer. Here, a transistor is formed over a substrate, and a semiconductor layer of the transistor includes indium-based oxide; the passivation protection layer is formed through a physical vapor deposition process and covers one side of the transistor far away from the substrate; the passivation layer covers one side of the passivation protection layer away from the substrate. The semiconductor device may have improved performance and stability.

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to at least one embodiment of the present disclosure.

As shown in fig. 1, the preparation method may include steps S100 to S120.

Step S100: transistors are fabricated on a substrate. The semiconductor layer of the transistor includes indium-based oxide.

Step S110: and forming a passivation protection layer covering the transistor on the side of the transistor far from the substrate through a physical vapor deposition process.

Step S120: and forming a passivation layer on the side of the passivation protection layer away from the substrate.

In the above method, the transistor formed over the substrate may be an integral part of a certain functional circuit, that is, the transistor is formed during formation of the functional circuit. For example, the functional circuit may be a logic circuit for implementing a control or calculation function or a memory circuit for implementing a semiconductor memory (e.g., a volatile or nonvolatile memory device).

For step S100, for example, a suitable substrate material may be selected as needed. For example, the material of the substrate may include silicon, glass, quartz, or the like, e.g., the silicon substrate may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate, or the like, and embodiments of the present disclosure are not limited to the material of the substrate.

For example, the transistor fabrication process may include photolithography, etching, deposition, ion implantation, and heat treatment.

For example, a photolithographic process may be used to form minute patterns on a substrate, an etching process may be used to remove unwanted materials, a deposition technique process may be used to grow or deposit a thin film on the substrate, an ion implantation process may be used to implant dopants into the substrate to alter its conductivity, and a thermal treatment process may be used to activate the dopants or repair lattice damage.

For example, the transistor may include an indium-based oxide transistor, that is, the semiconductor layer of the transistor is indium-based oxide.

For example, the indium-based oxide may include at least one of IGZO, IGO, IGTO, inO or any combination thereof. The indium-based oxide transistor may include an IGZO transistor, an IGO transistor, or an IGTO transistor, for example.

For example, the thickness of the semiconductor layer may be 5nm to 150nm, for example 10nm. Illustratively, the semiconductor layer may include IGZO or IGO having a thickness of 10nm to 20 nm.

It should be noted that, in consideration of the mass production process error, a certain process error may exist in the actual film thickness. Illustratively, the film thickness of the indium-based oxide may range from 5nm to 15nm. In some embodiments, the thickness of the indium-based oxide film may also range from 5nm to 100nm, and embodiments of the present disclosure are not limited to indium-based oxide film thicknesses.

For step S110, for example, the passivation protection layer may include a material having high insulation and chemical stability to reduce the influence of the passivation layer on the indium-based oxide in the semiconductor layer.

For example, the passivation protection layer may include a metal oxide. For example, the passivation protection layer may include yttrium oxide or aluminum oxide, and may include aluminum oxide (Al ₂ O ₃ ) Or yttrium oxide (Y) ₂ O ₃ )。

For example, the passivation protection layer may be formed by a physical vapor deposition process (Physical Vapor Deposition, PVD). For example, the physical vapor deposition process may include a sputtering process or an evaporation process.

For example, during physical vapor deposition, the passivation protection material may be vaporized or sputtered by heating or bombardment and then deposited on the transistor surface. In practice, the passivation layer having the desired thickness and properties may be formed by controlling the deposition conditions (e.g., evaporation rate, vacuum, deposition time, temperature, pressure, atmosphere, or deposition rate, etc.).

For step S120, for example, the passivation layer may include a material having superior insulation, chemical stability, and mechanical properties. For example, the material of the passivation layer may be determined according to compatibility with other layers. For example, the material of the passivation layer may be the same as or different from the material of the passivation layer.

For example, the passivation layer may comprise at least one of silicon nitride, silicon oxide, silicon oxynitride, or hafnium oxide, e.g., may comprise SiN _x 、SiO ₂ 、HfO ₂ At least one of them.

In SiN _x May include different proportions of nitrogen atoms. Exemplary SiN _x May include Si ₃ N ₄ 、SiN、Si ₅ N ₆ Etc.

For example, the passivation material may be deposited on the side of the passivation layer remote from the substrate by a deposition process. For example, the deposition process may include a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition Process (PVD), or an atomic layer deposition process (Atomic Layer Deposition, ALD).

For example, the thickness and quality of the passivation layer may be controlled by controlling parameters of the deposition process (e.g., temperature, pressure, gas flow, deposition rate, environmental cleanliness, etc.).

For example, the passivation layer may have a film thickness of 25nm to 35nm. Exemplary, the passivation layer may comprise 25nm to 35nm SiN _x Or SiO ₂ 。

It should be noted that, in consideration of the mass production process error, a certain process error may exist in the actual film thickness of the passivation layer. The passivation layer may have a film thickness in the range of 25nm to 55nm, for example. In some embodiments, the thickness of the passivation layer may also range from 10nm to 100nm, and embodiments of the present disclosure are not limited to the thickness of the passivation layer.

For example, the method in at least one embodiment of the present disclosure may further post-treat the deposited passivation layer, such as annealing or heat treatment, to improve the performance of the passivation layer.

For example, after the passivation layer deposition is completed, the passivation layer may be further planarized, such as by chemical mechanical polishing (Chemical Mechanical Polishing, CMP) to ensure the surface of the passivation layer is planarized, providing a good basis for subsequent processing.

For example, after the passivation layer deposition is completed, the passivation protection layer and passivation layer may also be evaluated for performance to ensure that they meet design requirements. For example, it may include measuring the thickness, uniformity, insulation properties, chemical stability, etc. of the passivation protection layer and passivation layer.

In the above embodiments of the present disclosure, for example, in the form of a chemical vapor deposition processIn the passivation layer formation process, even if a precursor including a hydrogen atom (e.g., silane (SiH) ₄ ) Or ammonia (NH) ₃ ) Etc.) growth of SiNx, siO ₂ Or HfO ₂ Etc. These precursors, including hydrogen atoms, may decompose under the influence of the plasma and react with other reactive gases (e.g., oxygen or nitrogen, etc.) to form the passivation layer material. Due to the decomposition of the precursor and the chemical reaction in the plasma, a large amount of hydrogen atoms or hydrogen ions may be generated, which may enter into the semiconductor layer. Since the indium-based oxide in the semiconductor layer has a certain hydrogen adsorption capacity, various effects may be exerted on the performance of the indium-based oxide. For example, hydrogen atoms or hydrogen ions may act as donor or acceptor impurities, altering the carrier concentration and mobility of the indium-based oxide, thereby affecting the electrical performance of the indium-based oxide transistor. For example, hydrogen atoms or hydrogen ions may also interact with oxygen vacancies or other defects in the indium-based oxide, altering the energy level or distribution of the defects, affecting the performance of the indium-based oxide transistor. For example, hydrogen atoms or hydrogen ions may also cause structural changes or stress changes in the semiconductor layer including the indium-based oxide, thereby affecting the performance of the indium-based oxide transistor.

In at least one embodiment of the present disclosure, a passivation layer is formed on a side of the indium-based oxide transistor away from the substrate by a physical vapor deposition process, and then a passivation layer is formed on a side of the passivation layer away from the substrate, so that diffusion of hydrogen can be reduced, thereby reducing an influence of hydrogen on performance of the indium-based oxide transistor, and improving performance and stability of the semiconductor device.

In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes step S101 (not shown in the drawings).

Step S101: a silicon-based semiconductor device layer is formed on a substrate by a semiconductor fabrication process. Here, the substrate includes a silicon substrate.

A specific example of the above step S100 may further include step S102 (not shown in the figure).

Step S102: transistors are fabricated on the silicon-based semiconductor device layer on the side remote from the substrate.

For step S101, for example, in at least one embodiment of the present disclosure, a memristor device layer or a carbon nanotube transistor device layer may be formed on a side of the silicon-based device layer away from the substrate, and then a transistor in which the semiconductor layer is indium-based oxide may be formed on a side of the memristor device layer or the carbon nanotube transistor device layer away from the substrate.

For example, a silicon-based semiconductor device layer may be formed on a silicon substrate by a semiconductor fabrication process. The semiconductor manufacturing process adopted in step S101 may be adjusted according to specific requirements to obtain a desired semiconductor device layer, and the semiconductor manufacturing process adopted in step S101 in the embodiment of the present disclosure is not limited.

For step S102, reference may be made to the description of the preparation of the transistor on the substrate in the previous embodiment, and the description is omitted here.

In some embodiments of the present disclosure, a specific example of the step S110 may further include: and forming a passivation protection layer covering the transistor on the side of the transistor away from the substrate through a sputtering process.

For example, the sputtering process may include a magnetron sputtering process or a reactive sputtering process.

For example, a metal oxide layer may be coated on the side of the transistor remote from the substrate by a magnetron sputtering process to act as a passivation protection layer for the transistor.

In the above embodiments, the use of the magnetron sputtering process may enable the preparation of a passivation protection layer at high speed, low temperature (e.g., no more than 300 degrees celsius), low damage, and may improve manufacturing efficiency and reduce potential thermal damage. In addition, the metal oxide layer prepared by the magnetron sputtering process can have excellent adhesive force and uniformity, so that the transistor can be effectively protected, and the consistency and stability of the transistor can be improved.

For example, a metal layer may be covered on a side of the transistor away from the substrate by a magnetron sputtering process, and then the metal layer is subjected to an oxidation treatment to form a metal oxide layer. For example, the oxidation treatment may include performing an annealing oxidation treatment, i.e., oxidizing the metal layer during annealing. For example, the metal layer may undergo an oxidation reaction with oxygen in the air. For example, oxygen may also be introduced during the process so that oxidation of the metal layer may occur. For example, the temperature of the anneal may range from 200 degrees celsius to 300 degrees celsius.

For example, the transistor may be covered with a metal oxide layer on the side of the transistor remote from the substrate by a reactive sputtering process to act as a passivation protection layer for the transistor.

For example, the metal oxide layer may include yttrium oxide or aluminum oxide, and may include aluminum oxide (Al ₂ O ₃ ) Or yttrium oxide (Y) ₂ O ₃ )。

In the above embodiments, the passivation protection layer preparation with high purity, high density and excellent performance can be achieved using the reactive sputtering process. The reactive sputtering process introduces a reactive gas during the sputtering process to react chemically with sputtered metal atoms to form a metal oxide layer on the side of the transistor remote from the substrate. The reactive sputtering process can precisely control the composition and thickness of the thin film, can be performed at a lower temperature (not more than 300 ℃), and can avoid thermal damage to the transistor. Meanwhile, the metal oxide layer prepared by the reactive sputtering process has excellent adhesive force and uniformity, can be tightly adhered to the surface of the transistor, and ensures effective protection.

In some embodiments of the present disclosure, a specific example of the step S110 may further include: and forming a passivation protection layer covering the transistor on one side of the transistor far away from the substrate through an evaporation process.

For example, the evaporation process may include an electron beam evaporation process, a resistance heating evaporation process, or an induction heating evaporation process.

For example, the transistor may be covered with a metal oxide layer on a side of the transistor remote from the substrate by an electron beam evaporation process to act as a passivation protection layer for the transistor.

For example, a metal layer may be covered on a side of the transistor away from the substrate by an electron beam evaporation process, and then the metal layer is subjected to an oxidation treatment to form a metal oxide layer. For example, the oxidation treatment may include performing an annealing oxidation treatment, i.e., oxidizing the metal layer during annealing. For example, the metal layer may undergo an oxidation reaction with oxygen in the air. For example, oxygen may also be introduced during the process so that oxidation of the metal layer may occur. For example, the temperature of the anneal may range from 200 degrees celsius to 300 degrees celsius.

In the above embodiment, the electron beam evaporation process is adopted to cover the metal oxide layer on the side of the transistor away from the substrate as the passivation protection layer, so that the thickness and composition of the metal oxide layer can be precisely controlled, and a high deposition rate can be realized. The electron beam evaporation process can utilize a high-energy electron beam to heat a metal oxide evaporation source, so that metal oxide is evaporated and deposited on the surface of a transistor to form a thin film. The electron beam evaporation process has higher energy density and heating speed, and can realize rapid and uniform film deposition. Meanwhile, the metal oxide layer prepared by the electron beam evaporation process has excellent adhesive force and compactness, can be tightly adhered to the surface of the transistor, and can provide a good protection effect for the transistor.

In some embodiments of the present disclosure, the transistor prepared in step S100 may include a back gate transistor.

In a back gate transistor, the gate is closer to the substrate than the source and drain, and the gate is also formed before the semiconductor layer of the transistor, so the fabrication process of the gate does not affect the properties of the semiconductor layer. Compared to transistors of top gate structure, back gate transistors may have better power control capability, less leakage current, and better temperature saturation characteristics. Furthermore, in some examples, the back gate transistor may also have a higher operating speed and a greater noise margin.

In some embodiments of the present disclosure, a specific example of the step S100 may further include steps S1001-S1004 (not shown in the figures) for forming a back gate transistor.

Step S1001: a gate is formed on a substrate.

Step S1002: and covering the gate insulating layer on the side of the gate away from the substrate.

Step S1003: a semiconductor layer is formed on a side of the gate insulating layer remote from the substrate.

Step S1004: and forming a source electrode and a drain electrode on one side of the semiconductor layer away from the substrate. Here, the source and drain electrodes are spaced apart by a portion of the semiconductor layer serving as a channel region.

For step S1001, a suitable substrate material may be selected as desired. For example, the material of the substrate may include silicon, glass, quartz, etc., and embodiments of the present disclosure are not limited to materials of the substrate.

For example, the substrate may be cleaned to remove impurities and contaminants from the surface of the substrate.

For example, a layer of gate material may be deposited on a substrate. For example, the gate material may include a metal (e.g., titanium, molybdenum, platinum, aluminum, copper, titanium nitride, etc., metal or alloy material), polysilicon, or a conductive oxide (e.g., indium tin oxide), etc.

For example, the gate material may be patterned into a desired shape and size by photolithography and etching processes.

For example, the gate material may also be a metal layer stack, for example, a metal layer stack of Ti (first adhesion layer), pd (intermediate metal layer), ti (second adhesion layer) may be sequentially grown by a photolithography process, an electron beam evaporation process, and then patterned as a gate electrode by a lift-off process or an etching process.

For example, the first adhesion layer may further include TaN or the like; the gate metal layer may also include Ti, mo, tiN, pt and the like; the second adhesion layer may further include Al or the like.

For example, the first adhesion layer may have a thickness of 10nm or other, the intermediate metal layer may have a thickness of 15nm or other, and the second adhesion layer may have a thickness of 1nm or other. It should be noted that, in consideration of the mass production process error, a certain process error may exist in the actual film thickness. Further, embodiments of the present disclosure are not limited to the thickness of the film layer in the gate electrode.

For step S1002, for example, an insulating material having good insulating properties and stability may be selected as the gate insulating layer. For example, the gate insulating layer may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, or the like.

For example, a gate insulating layer may be prepared on the side of the gate remote from the substrate by a thin film formation process (e.g., CVD, PVD, etc.).

For example, an Atomic Layer Deposition (ALD) process may be used to grow HfO ₂ As a gate oxide layer of the transistor to serve as a gate insulating layer. Here, the gate oxide layer may further include Al ₂ O ₃ Or Al ₂ O ₃ With HfO ₂ Is a combination of (a) and (b). Exemplary, may include 10nm of HfO ₂ Or 10nm Al ₂ O ₃ +5nm HfO ₂ . For example, the gate oxide layer may also be grown using a plasma enhanced chemical vapor deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) or a plasma enhanced atomic layer deposition process (Plasma Enhanced Atomic Layer Deposition, PEALD). It should be noted that, in consideration of the mass production process error, a certain process error may exist in the actual film thickness. Further, embodiments of the present disclosure are not limited to the film thickness of the gate oxide layer.

For step S1003, the semiconductor layer includes indium-based oxide, for example.

For example, indium-based oxide may be prepared on the side of the gate insulating layer remote from the substrate by a thin film formation process (e.g., CVD, PVD, etc.).

For example, IGZO may be grown as the semiconductor layer by an ALD process. IGZO may also be grown as a semiconductor layer, for example, by PEALD process. The material of the semiconductor layer may include IGZO, IGO, or a combination of materials of IGZO and InO. The thickness of the semiconductor layer may be IGZO or IGO of 10nm, or a combination of materials of 5nm IGZO+2nm InO+5nm IGZO, for example. It should be noted that, in consideration of the mass production process error, a certain process error may exist in the actual film thickness. Further, embodiments of the present disclosure are not limited to the film thickness of the semiconductor layer.

For example, the semiconductor layer may be annealed to improve the crystalline quality and electrical properties of the semiconductor layer.

For step S1004, a conductive layer may be deposited on a side of the semiconductor layer remote from the substrate, for example, the conductive layer may include one or more of titanium, palladium, molybdenum, titanium nitride, indium tin oxide, platinum, gold. Thereafter, the conductive layer may be patterned to form a source electrode and a drain electrode through photolithography and etching processes.

For example, the channel region may be defined by a photolithographic process, and the channel region may space the source and drain apart.

For example, a metal layer may be deposited on a side of the semiconductor layer remote from the substrate by a photolithography process, an evaporation process, and then stripped to form a pattern to serve as a source and a drain of the transistor. The growth and etching process may also be adopted, i.e. the metal layer is grown on the side of the semiconductor layer far away from the substrate, and then the photoetching process and the etching process are adopted to form source-drain metal.

In the embodiment, the shapes and the sizes of all layers of the transistor can be accurately controlled, the stability of the transistor can be enhanced, and the consistency and the reliability of transistor preparation are improved.

In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes step S130 (not shown in the figures) before step S110.

Step S130: and (5) annealing treatment is carried out. Here, the temperature range of the annealing treatment may be controlled between 200 degrees celsius and 300 degrees celsius.

For step S130, for example, during the preparation of the indium-based oxide transistor, an ion implantation process may be used to introduce a desired doping element into the indium-based oxide material, and the annealing process may activate the implanted ions, promoting their diffusion, so that the implanted ions may move to the correct position.

For example, the annealing process may also repair some damage or defects generated by the indium-based oxide material during ion implantation.

For example, the annealing process may also supplement the oxygen content in the indium-based oxide transistor.

For example, the annealing process may promote rearrangement of atoms in the indium-based oxide material by thermal motion, promote recovery of the crystal lattice, and thereby repair damage or defects of the indium-based oxide material.

For example, the annealing treatment may improve electrical properties of the indium-based oxide material, such as mobility, carrier concentration, etc., thereby improving the performance of the indium-based oxide transistor.

In addition, as described above, by performing annealing treatment on the prepared transistor, covering the passivation layer on the side of the transistor away from the substrate by a physical vapor deposition process, and forming the passivation layer on the side of the passivation layer away from the substrate, diffusion of hydrogen can be further reduced, so that the influence of hydrogen on the performance of the indium-based oxide transistor is reduced, and the performance and stability of the semiconductor device are improved.

Fig. 2 illustrates a schematic diagram of a process flow for fabricating a transistor according to at least one embodiment of the present disclosure.

As shown in fig. 2, the method of manufacturing the transistor of the present disclosure is exemplarily described below taking the method of manufacturing an IGZO transistor as an example.

For example, the method of manufacturing the IGZO transistor may include the steps of:

(a) Sequentially forming a stack of 10nm Ti, 15nm Pd and 1nm Ti on a substrate by adopting a photoetching process and an electron beam evaporation process, and then stripping to form a pattern to be used as a back gate of the transistor.

(b) Growing 10nm HfO by ALD process ₂ As a gate insulating layer of the transistor, and then using an Inductively Coupled Plasma (ICP) to transfer HfO on the gate of the transistor ₂ Etching and removing to expose the gate metal.

(c) An ALD process is used to grow 10nm IGZO, 10nm IGO, or (5nm IGZO+2nm InO+5nm IGZO) as the active layer of the transistor.

(d) Depositing 20nm Ti and 45nm Pd by adopting a photoetching process and an electron beam evaporation process, and then stripping to form patterns serving as a source electrode and a drain electrode of the transistor.

(e) And defining a channel region of the IGZO by photoetching, etching the IGZO outside the channel region by adopting a wet etching process or a dry etching process to realize channel isolation, and isolating a source electrode and a drain electrode by the channel region.

(f) Annealing treatment is performed, and annealing is performed at a temperature of 250 ℃ in air for 30 minutes (min) to supplement oxygen vacancies in IGZO.

(g) Growing 10nm Y by magnetron sputtering process ₂ O ₃ As a passivation layer.

(h) Growth of 30nm SiN by PECVD process _x As a passivation layer.

It should be noted that, in consideration of the mass production process error, a certain process error may exist in the actual film thickness.

In some embodiments of the present disclosure, a semiconductor device includes a substrate, a transistor, a passivation protection layer, and a passivation layer. Here, the transistor is formed on the substrate, the passivation layer is formed by a physical vapor deposition process and covers a side of the transistor away from the substrate, and the passivation layer covers a side of the passivation layer away from the substrate.

For example, the material of the substrate may include silicon, glass, quartz, etc., and embodiments of the present disclosure are not limited to materials of the substrate.

For example, the transistor may be a back gate transistor.

For example, the transistor may include an indium-based oxide transistor, and for example, may include an IGZO transistor, an IGO transistor, or an IGTO transistor.

For example, the passivation layer covers a side of the transistor remote from the substrate.

For example, the passivation protection layer may include a metal oxide layer. The metal oxide layer may comprise yttrium oxide or aluminum oxide, for example, may comprise aluminum oxide (Al ₂ O ₃ ) Or yttrium oxide (Y) ₂ O ₃ )。

For example, the passivation protection layer may deposit a metal oxide layer on the sides of the source and drain electrodes remote from the substrate through a sputtering process or an evaporation process.

For example, the passivation layer covers a side of the passivation protection layer remote from the substrate.

For example, the passivation layer may include at least one passivation material of silicon nitride, silicon oxide, silicon oxynitride, or hafnium oxide.

For example, the passivation layer may deposit a passivation material on a side of the passivation protection layer remote from the substrate by a chemical vapor deposition process.

The structure, function, material, preparation process, beneficial effect, etc. of the substrate, transistor, passivation layer and passivation layer in the embodiments of the present disclosure may also refer to the related descriptions of the substrate, transistor, passivation layer and passivation layer in the foregoing embodiments, which are not repeated herein.

In some embodiments of the present disclosure, the semiconductor apparatus further comprises a silicon-based device layer. Here, a silicon-based device layer is formed over the substrate, and a transistor is formed on a side of the silicon-based device layer remote from the substrate.

For example, the substrate may comprise a silicon substrate, such as a monocrystalline silicon substrate or a silicon-on-insulator substrate, embodiments of the present disclosure are not limited to the material of the substrate.

For example, at least one other device layer may also be included between the silicon-based device layer and the transistor. For example, the other device layers may include semiconductor device layers.

For example, the semiconductor device layers may include memristor device layers or carbon nanotube transistor device layers, for example, the memristor device layers may be configured to perform a memory-integrated operation on input data, and the carbon nanotube transistor device layers may be configured to form a control circuit layer of the memristor device layers. For example, a silicon-based device layer, a control circuit layer, a memristor device layer, and a device layer including the aforementioned transistors may be at least partially stacked, where interlayer dielectrics are respectively disposed between the device layers, where the interlayer dielectrics include a plurality of vias, and communication may be performed between the device layers through the plurality of vias.

For example, the silicon-based device layer may be fabricated using a CMOS logic fabrication process (or simply a silicon-based CMOS process) to fabricate CMOS transistors and other components.

Fig. 3 illustrates a schematic structure of a transistor provided in at least one embodiment of the present disclosure.

As shown in fig. 3, in some embodiments of the present disclosure, a transistor includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, a drain electrode, a channel region, a passivation protection layer, and a passivation layer.

The gate is formed on a substrate (not shown in the drawings); the grid insulating layer covers one side of the grid far away from the substrate; the semiconductor layer is formed on one side of the gate insulating layer away from the substrate; the source electrode and the drain electrode are formed on the side of the semiconductor layer away from the substrate and are spaced apart by a portion of the semiconductor layer serving as a channel region; the passivation layer covers one side of the source electrode and the drain electrode far away from the substrate, and the passivation layer covers one side of the passivation layer far away from the substrate.

For example, the transistor may be a back gate transistor.

For example, the gate electrode may be formed on a silicon substrate.

For example, the gate may include a metal (e.g., titanium, molybdenum, platinum, aluminum, copper, titanium nitride, etc., metal or alloy material), polysilicon, or a conductive oxide (e.g., indium tin oxide), etc. .

For example, the gate electrode may be formed on the substrate by photolithography, vapor deposition, and lift-off processes, or may be formed on the substrate by growth and etching processes.

For example, the gate insulating layer may be deposited on the side of the gate remote from the substrate by a thin film formation process (e.g., CVD, PVD, etc.).

For example, the gate insulating layer may include HfO ₂ 、Al ₂ O ₃ At least one of them.

For example, the semiconductor layer may include indium-based oxide. The indium-based oxide may include IGZO or IGO, for example.

For example, the semiconductor layer may be deposited with an indium-based oxide on the side of the gate insulating layer remote from the substrate by a thin film formation process (e.g., CVD, PVD, etc.).

For example, the semiconductor layer is also covered with a metal layer on the side remote from the substrate. The metal layer may comprise one or more of titanium, palladium, molybdenum, titanium nitride, indium tin oxide, platinum, gold.

For example, the metal layer may be patterned to form a source and a drain.

For example, the passivation protection layer covers the source and drain electrodes on a side away from the substrate.

For example, the passivation protection layer may deposit a metal oxide layer on the sides of the source and drain electrodes remote from the substrate through a magnetron sputtering process or a reactive sputtering process.

For example, the passivation layer may include at least one passivation material of silicon nitride, silicon oxide, silicon oxynitride, or hafnium oxide, and may include, for example: siN (SiN) _x 、SiO ₂ 、HfO ₂ At least one of them.

Fig. 4 shows a transmission electron micrograph of a transistor prepared by a preparation method provided in at least one embodiment of the present disclosure.

In some embodiments of the present disclosure, a transmission electron micrograph of a transistor fabricated using the aforementioned fabrication method may be as shown in fig. 4.

As shown in fig. 4, a gate electrode, a gate insulating layer, a semiconductor layer, a source drain layer, a passivation protection layer, a passivation layer, and the like are sequentially formed in the vertical direction from the substrate. Here, the gate layer includes titanium and platinum, the semiconductor layer includes IGZO, the source drain layer includes titanium and platinum, and the passivation protection layer includes Y ₂ O ₃ The passivation layer comprises Si ₃ N ₄ 。

Fig. 5 illustrates a performance comparison schematic of a semiconductor device fabricated using a fabrication method provided by at least one embodiment of the present disclosure and a transistor fabricated using other fabrication methods.

Taking a transistor prepared by a PVD process to prepare a passivation layer and an ALD process to prepare a passivation layer as an example, performance comparisons of the transistor prepared by the preparation method of the present disclosure and the transistor prepared by the preparation method of preparing a passivation layer only by an ALD process are described as follows:

V _G can be used to represent the Gate Voltage (Gate Voltage), I _D W may be used to represent drain current density (Drain Current Density), I _D Can be used to represent Drain Current (Drain Current), I _g (I _D ) May be used to represent the relationship or transfer characteristics between the gate current and the drain current.

As shown in FIG. 5, the PVD process is used to fabricate a wafer comprising Y ₂ O ₃ Is prepared by ALD process and includes HfO ₂ The measured drain current and drain current density of the passivation layer of the indium-based oxide transistor is lower than that of the indium-based oxide transistor prepared by ALD process only and including HfO ₂ The indium-based oxide transistor of the passivation layer of (2) has better turn-off characteristics and lower power consumption.

As shown in fig. 6, the electronic apparatus 2000 includes a semiconductor device 210. For example, the semiconductor device 210 may include the semiconductor device provided in any of the above embodiments. For example, the electronic device 2000 may further include other devices, such as a central processing unit (Central Processing Unit, CPU), a data bus, a memory, and so on. The electronic device 2000 may be a signal processing device, a computing device, or the like, and may be used for a controller, a terminal device, a server device, or the like, for example.

In addition to the above exemplary description, the following points of the present disclosure need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

(3) It should be understood that, in the embodiments of the present disclosure, the sequence number of each step is not meant to indicate the order of execution, and the order of execution of each step should be determined by the functions and the internal logic, and should not be construed as limiting the implementation process of the embodiments of the present disclosure.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A method of manufacturing a semiconductor device, comprising:

preparing a transistor on a substrate, wherein a semiconductor layer of the transistor comprises indium-based oxide;

forming a passivation protection layer covering the transistor on one side of the transistor far away from the substrate through a physical vapor deposition process;

and forming a passivation layer on one side of the passivation protection layer away from the substrate.

2. The preparation method according to claim 1, further comprising:

a silicon-based semiconductor device layer is formed on the substrate by a semiconductor fabrication process,

the substrate is a silicon substrate, and the transistor is prepared on one side of the silicon-based semiconductor device layer far away from the substrate.

3. The production method according to claim 1, wherein the indium-based oxide comprises IGZO or IGO.

4. The method of manufacturing according to claim 1, wherein the passivation protection layer comprises yttrium oxide or aluminum oxide.

5. The method of claim 1, wherein the physical vapor deposition process comprises a sputtering process or an evaporation process.

6. The method of manufacturing according to claim 1, wherein the forming a passivation layer on a side of the passivation protection layer away from the substrate comprises:

and forming a passivation layer on the side, away from the substrate, of the passivation protection layer through a chemical vapor deposition process.

7. The method of manufacturing of claim 1, wherein the passivation layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, or hafnium oxide.

8. The manufacturing method according to claim 1 or 2, wherein the manufacturing of the transistor over the substrate includes:

forming a gate electrode on the substrate;

covering a gate insulating layer on one side of the gate away from the substrate;

forming the semiconductor layer on one side of the gate insulating layer away from the substrate;

a source electrode and a drain electrode are formed on a side of the semiconductor layer remote from the substrate, wherein the source electrode and the drain electrode are spaced apart by a portion of the semiconductor layer that serves as a channel region.

9. The method of manufacturing according to claim 1, further comprising, before the forming a passivation protection layer covering the transistor on a side of the transistor remote from the substrate by a physical vapor deposition process:

and carrying out annealing treatment, wherein the temperature range of the annealing treatment is 200-300 ℃.

10. A semiconductor device, comprising:

a substrate;

a transistor formed on the substrate, wherein a semiconductor layer of the transistor includes indium-based oxide;

a passivation protection layer formed by a physical vapor deposition process and covering one side of the transistor away from the substrate;

and the passivation layer is covered on one side of the passivation protection layer away from the substrate.

11. The semiconductor device according to claim 10, further comprising:

and the silicon-based semiconductor device layer is formed between the substrate and the transistor, wherein the substrate comprises a silicon substrate, and the transistor is formed on the side, away from the substrate, of the silicon-based semiconductor device layer.

12. The semiconductor device according to claim 10, wherein the transistor is a back gate transistor.

13. An electronic device, comprising:

the semiconductor device according to any one of claims 10 to 12.