CN102983104B - The manufacture method of CMOS transistor - Google Patents
The manufacture method of CMOS transistor Download PDFInfo
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- CN102983104B CN102983104B CN201110264366.6A CN201110264366A CN102983104B CN 102983104 B CN102983104 B CN 102983104B CN 201110264366 A CN201110264366 A CN 201110264366A CN 102983104 B CN102983104 B CN 102983104B
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Abstract
Present invention is disclosed a kind of manufacture method of CMOS transistor, pre-amorphous injection is carried out by the polysilicon layer to NMOS area, the ion of this pre-amorphous injection makes polysilicon layer be converted into amorphous silicon by polysilicon at subsequent high temperature annealing process, and in conversion process, produce stress, this effect of stress is in the Semiconductor substrate of described NMOS area, thus improve the stress memory effect of nmos pass transistor, further increase electron mobility and the drive current of nmos pass transistor, reach the object of the overall performance improving cmos device transistor.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to a kind of manufacture method of CMOS transistor.
Background technology
Along with in semiconductor technology production process, the size of transistor constantly reduces, and the voltage and current of transistor unit need of work constantly reduces, and the speed of transistor switch is also accelerated thereupon, requires significantly to improve to semiconductor technology each side thereupon.For improving the performance of semiconductor device, industry proposes kinds of processes and method, comprising gate last process and stress memory technique.
Part along with transistor has accomplished the thickness of several molecule and atom, and the material of composition semiconductor reaches the limit of physical electrical characteristic.Existing technique adopts silicon dioxide (SiO usually
2) as the material of gate dielectric layer, the silicon dioxide layer so far in transistor has narrowed down to only has initial 1/10th, even reaches the thickness only having 5 oxygen atoms.Gate dielectric layer is as the insulating barrier between spacer gates conductive layer and its lower floor (such as Semiconductor substrate), can not reduce again, otherwise the leakage current produced can allow transistor normally work, if improve the voltage and current of effectively work, chip power-consumption more can be made to increase to surprising stage.Therefore, industry have found the material-high dielectric constant material (High-K Material) than silicon dioxide with higher dielectric constant and better field effect characteristic, in order to better to separate grid and other parts of transistor, significantly reduce electrical leakage quantity.Meanwhile, in order to compatible with high dielectric constant material, adopt the original polysilicon of metal material instead as grid conductive layer material, thus define new grid structure.The grid structure of metal material is in high-temperature annealing process process, and its work function (Work Function) can occur significantly to change, cause the problems affect performance of semiconductor device such as gate depletion and RC delay.
For solving the problem of the grid structure of above-mentioned metal material, define gate last process (Gate-LastProcess), namely the illusory gate stack with polysilicon layer is first formed, after carrying out source and drain injection and high-temperature annealing process, remove the polysilicon layer in illusory gate stack again, and deposit metallic material, finally form metal gates.
Simultaneously, for improving the device performance of CMOS transistor, industry introduces stress memory technique, namely by introducing stress in the raceway groove of Semiconductor substrate, to make the performance of device improve, the technique being improved device performance by stress has become the common technological means of semiconductor applications.In prior art, stress memory technique is included in CMOS transistor disposed thereon stressor layers (such as nitration case etc.), carrying out high-temperature annealing process is remembered on the semiconductor device to make stress, and stress is remembered removes stressor layers behind the active area of grid polycrystalline silicon or diffusion region or Semiconductor substrate.Thus use stress to be improved the mobility in electronics or hole, improve the performance of overall device.Especially the nmos pass transistor in CMOS transistor, stress memory technique is stress application (namely during compression) in a longitudinal direction, the electron mobility of nmos pass transistor can be improved, improve nmos pass transistor drive current (Idrive), and then improve the performance of nmos pass transistor.
Except above-mentioned stress memory method, in gate last process, how to realize better stress memory effect better also becomes industry problem demanding prompt solution.
Summary of the invention
The object of this invention is to provide a kind of manufacture method of CMOS transistor, to improve the stress memory effect of nmos pass transistor.
For solving the problem, the manufacture method of a kind of CMOS transistor of the present invention, comprising:
There is provided semi-conductive substrate, described Semiconductor substrate comprises NMOS area and PMOS area;
Form dielectric layer and polysilicon layer successively on the semiconductor substrate;
Pre-amorphous injection is carried out to the polysilicon layer in described NMOS area;
Described polysilicon layer forms silicon nitride layer;
Silicon nitride layer, polysilicon layer and dielectric layer described in etched portions, to form NMOS gate stack in described NMOS area, described PMOS area forms PMOS gate stack;
Described NMOS gate stack sidewall forms NMOS grid curb wall, forms PMOS grid curb wall at described PMOS gate stack sidewall;
Carry out high-temperature annealing process.
Further, carry out the step of pre-amorphous injection to the polysilicon layer in described NMOS area, comprising: at described polysilicon layer surface-coated photoresist layer; Photoresist layer described in patterning, to remove the photoresist layer be positioned in described NMOS area, exposes the polysilicon layer of described NMOS area; Pre-amorphous injection is carried out to described Semiconductor substrate; Remove remaining photoresist layer.
Further, the injection ion of described pre-amorphous injection comprises boron, phosphorus, germanium, the one of arsenic or its combination.
Further, the Implantation Energy of described pre-amorphous injection is 5KeV ~ 25KeV.
Further, between the step forming described NMOS grid curb wall and PMOS grid curb wall and the step of carrying out high-temperature annealing process, also comprise, in the Semiconductor substrate of described NMOS gate stack both sides, form NMOS source-drain area and be positioned at the NMOS metal silicide region above described NMOS source-drain area; And in the Semiconductor substrate of described PMOS gate stack both sides, form PMOS source drain region and be positioned at the PMOS metal silicide region above described PMOS source drain region.
Further, the material of NMOS metal silicide region and PMOS metal silicide region is one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.
Further, between the step forming described NMOS grid curb wall and PMOS grid curb wall and the step of carrying out high-temperature annealing process, described NMOS area surface coverage stressor layers is also included in.
Further, the material of described stressor layers is silicon nitride, and thickness is 200 dust ~ 600 dusts.
Further, the stress that described stressor layers produces is-500MPa ~ 1600MPa.
Further, the annealing temperature of described high-temperature annealing process is 900 DEG C ~ 1300 DEG C.
Further, the thickness of described polysilicon layer is 500 dust ~ 700 dusts.
Further, the thickness of described silicon nitride layer is 300 dust ~ 500 dusts.
Compared to prior art, the present invention carries out pre-amorphous injection by the polysilicon layer to NMOS area, the ion of pre-amorphous injection makes polysilicon layer be converted into amorphous silicon by polysilicon at subsequent high temperature annealing process, and in conversion process, produce stress, this effect of stress is in the Semiconductor substrate of described NMOS area, improve the stress memory effect of nmos pass transistor, the electron mobility of further raising nmos pass transistor and drive current, thus the object reaching the overall performance improving cmos device transistor.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of CMOS transistor in the embodiment of the present invention one.
Fig. 2 ~ Fig. 8 is the structural representation in the manufacturing process of CMOS transistor in the embodiment of the present invention one.
Fig. 9 is the structural representation in the manufacturing process of CMOS transistor in the embodiment of the present invention two.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
The manufacture method of CMOS transistor of the present invention, mainly for the performance improving the CMOS transistor adopting gate last process (Gate-Last Process), by the performance adopting new stress memory method to improve nmos pass transistor.Certainly, the method for the invention can be applied to employing equally and first formed in the manufacture craft of the CMOS transistor of grid technology (Gate-First Process).
Embodiment one
Fig. 1 is the schematic flow sheet of the manufacture method of CMOS transistor in the embodiment of the present invention one.Fig. 2 ~ Fig. 8 is the structural representation in the manufacturing process of CMOS transistor in the embodiment of the present invention one.
Shown in composition graphs 1 ~ Fig. 8, the manufacture method of the CMOS transistor of the present embodiment, comprises the following steps:
Step S01: as shown in Figure 2, provides semi-conductive substrate 100, and described Semiconductor substrate 100 comprises NMOS area 10 and PMOS area 20;
Wherein, described Semiconductor substrate 100 can be monocrystalline silicon, the semi-conducting materials such as polysilicon or germanium silicon compound, the necessary structure in order to form semiconductor device such as various isolated component and various doped regions is also formed in described Semiconductor substrate 100, described isolated component is such as fleet plough groove isolation structure (STI) 102, described doped region (not indicating in figure) is such as N trap, P trap and lightly-doped source drain region (LDD), said structure is determined according to actual semiconductor device manufacture craft process, be well known to those skilled in the art technology contents, do not repeat them here.
Step S02: as shown in Figure 2, described Semiconductor substrate 100 is formed dielectric layer 101 and polysilicon layer 103 successively;
Described dielectric layer 101 can be adopted as common dielectric material, such as, one in oxide, nitride, nitrogen oxide or its combination, and described dielectric layer 101 can adopt thermal oxidation method or chemical vapour deposition technique (CVD) to be formed.Described polysilicon layer 103 comprises the polysilicon layer 103a be formed in the NMOS area 10 and polysilicon layer 103b be formed in PMOS area 20, described polysilicon layer 103 can adopt chemical vapour deposition technique to be formed, and the thickness of described polysilicon layer 103 is 500 dust ~ 700 dusts.
Step S03: as shown in Fig. 3 ~ Fig. 5, the polysilicon layer 103a to described NMOS area 10 carries out pre-amorphous injection;
The process of carrying out described pre-amorphous injection specifically comprises the following steps: first, at described polysilicon layer 103a, 103b surface-coated photoresist layer; Then, photoresist layer described in patterning, retains the photoresist layer 300 be positioned in described PMOS area 20, exposes the polysilicon layer 103a of described NMOS area 10, form structure as shown in Figure 3; As shown in Figure 4, then, pre-amorphous injection (Pre Amorphization Implant is carried out to described Semiconductor substrate 100, PAI) 200, after described pre-amorphous injection 200, have pre-amorphous injection ion at the polysilicon layer 103a of described NMOS area 10, the polysilicon layer 103b of PMOS area 20 does not inject the ion of described pre-amorphous injection 200 under photoresist layer 300 blocks.Wherein preferably, the injection ion of described pre-amorphous injection 200 can be boron, phosphorus, germanium, the one of arsenic or its combination, and the Implantation Energy of described pre-amorphous injection 200 is 5KeV ~ 25KeV; Finally, remove remaining photoresist layer 300 in described PMOS area 20, form structure as shown in Figure 5.
After carrying out pre-amorphous injection 200 to the polysilicon layer 103a of described NMOS area 10, pre-amorphous injection ion is formed in the polysilicon layer 103a of described NMOS area 10, described pre-amorphous injection ion is at subsequent high temperature annealing process, the polysilicon of the polysilicon layer 103a of NMOS area 10 is made to be converted into amorphous silicon, stress is produced in conversion process, this effect of stress is in the Semiconductor substrate 100 of NMOS area 10, thus reach the electron mobility improving nmos pass transistor, improve nmos pass transistor drive current, and then the effect of the performance of raising nmos pass transistor.
Step S04: as shown in Figure 6, described polysilicon layer 103 forms silicon nitride layer 105;
Described silicon nitride layer 105 can adopt chemical vapour deposition technique to be formed, and the thickness of described silicon nitride layer 105 is 300 dust ~ 500 dusts.Described silicon nitride layer 105 is covered on described polysilicon layer 103a, 103b; for the protection of polysilicon layer 103a, 103b; prevent from polysilicon layer 103a, 103b form metal silicide simultaneously, avoid being difficult to because the metal silicide on it stops when follow-up removal polysilicon layer 103a, 103b remove.
Step S05: as shown in Figure 7, silicon nitride layer 105, polysilicon layer 103a, 103b and dielectric layer 101 described in etched portions, to form NMOS gate stack 106a in described NMOS area 10, described PMOS area 10 forms PMOS gate stack 106b;
Detailed process is as follows: spin coating photoresist film (not indicating in figure) on described nitration case 105, photoresist film is exposed and develops, graphical photoresist film, the described silicon nitride layer 105 of part, polysilicon layer 103a, 103b and dielectric layer 101 is removed for mask etches successively with described graphical photoresist film, described NMOS area 10 is formed NMOS gate stack 106a, described PMOS area 10 forms PMOS gate stack 106b, the final structure formed as shown in Figure 7.
Step S06: as shown in Figure 8, described NMOS gate stack 106a sidewall forms NMOS grid curb wall 107a, forms PMOS grid curb wall 107b at described PMOS gate stack 106b sidewall;
Preferably, the material of described NMOS grid curb wall 107a and described PMOS grid curb wall 107b is oxide layer or nitration case, also can be ONO (oxide layer-nitride layer-oxide layer) structure or ON (oxide-nitride) structure, described NMOS grid curb wall 107a and described PMOS grid curb wall 107b can adopt the method for chemical vapour deposition (CVD) and etching to be formed, the common technique means be familiar with by those skilled in the art, therefore not repeat at this.
After formation described NMOS grid curb wall 106a and PMOS grid curb wall 107a, the NMOS metal silicide region 109a forming NMOS source-drain area 108a and be positioned at above described NMOS source-drain area 108a, and PMOS source drain region 108b and the PMOS metal silicide region 109b be positioned at above described PMOS source drain region 108b.Particularly, first, the source and drain of carrying out N-type Doped ions in the Semiconductor substrate 100 of described NMOS gate stack 106a both sides is injected, form NMOS source-drain area 108a, the source and drain of carrying out P type Doped ions in the Semiconductor substrate 100 of described PMOS gate stack 106b both sides is injected, and forms PMOS source drain region 108b; Then, above described NMOS source-drain area 108a, form NMOS metal silicide region 109a, above described PMOS source drain region 108b, form PMOS metal silicide region 109b.
Wherein, described NMOS metal silicide region 109a and PMOS metal silicide region 109b preferably utilizes the mode of chemical vapour deposition (CVD) (CVD) or physical vapour deposition (PVD) (PVD) metal to be deposited on Semiconductor substrate 100 surface, and metal forms metal silicide with pasc reaction in high-temperature annealing process.The material of described NMOS metal silicide region 109a and PMOS metal silicide region 109b is one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.In the present embodiment, the material of described NMOS metal silicide region 109a and PMOS metal silicide region 109b is nickel-silicon compound, nickel beam-plasma is utilized to be sputtered onto in described Semiconductor substrate 100, with the silicon generation chemical reaction in described Semiconductor substrate 100 in subsequent high temperature annealing process, thus form nickel-silicon compound.Described NMOS metal silicide region 109a and PMOS metal silicide region 109b for improve source-drain area and follow-up formation in Semiconductor substrate 100 metal interconnecting wires between the resistance characteristic at interface, contribute to the electrical extraction of source-drain area.
In the process of NMOS metal silicide region 109a and PMOS metal silicide region 109b, described silicon nitride layer 105 blocks described polysilicon layer 103a, 103b, prevent from polysilicon layer 103a, 103b form metal silicide simultaneously, avoid the problem being difficult to because the metal silicide on it stops when follow-up removal polysilicon layer 103a, 103b remove.
Step S07: carry out high-temperature annealing process.
The annealing temperature of described high-temperature annealing process is 900 DEG C ~ 1300 DEG C.In high-temperature annealing process process, the polysilicon layer of described NMOS gate stack 106 is formed with pre-amorphous injection ion, pre-amorphous injection ion makes the polysilicon layer of described NMOS gate stack 106 be converted into amorphous silicon by polysilicon at high-temperature technology, stress is produced in conversion process, this effect of stress is in the Semiconductor substrate 100 of NMOS area 10, thus reach the electron mobility improving nmos pass transistor, improve nmos pass transistor drive current (Idrive), and then the effect of the performance of raising nmos pass transistor.
Further, after completing high-temperature annealing process, the CMOS transistor manufacturing process that the present embodiment provides can also comprise the following steps:
First, on the semiconductor substrate, the both sides of described NMOS gate stack and PMOS gate stack form first medium layer; Then, remove the nitration case in NMOS gate stack and polysilicon layer, remove the nitration case in PMOS gate stack and polysilicon layer; Then, NMOS gate stack described in depositing metal layers and PMOS gate stack, thus form metal gates.Polysilicon layer in described NMOS gate stack is finally removed, therefore carries out pre-amorphous injection pair nmos transistor and to produce after stress pair nmos transistor without other influences.In addition, described CMOS transistor manufacturing process also comprises other processing steps, and such as the processing step such as contact hole, metal lead wire etc., are those skilled in the art's common technique means, do not repeat at this.
Embodiment two:
Fig. 9 is the structural representation in the manufacturing process of the embodiment of the present invention two CMOS transistor, as shown in Figure 9, on the process base of the CMOS transistor manufacture method of embodiment one, between step S06 and step S07, be increased in the step of described NMOS area 10 surface coverage stressor layers 110.
Preferably, the material of described stressor layers 110 is silicon nitride, and its thickness range is 200 dust ~ 600 dusts.The stress that described stressor layers produces is-500MPa ~ 1600MPa, and wherein-500MPa ~ 0MPa is compression, and 0MPa ~ 1600MPa is tension stress.Stressor layers 110 stress memory that described silicon nitride is formed is good, and silicon nitride is common material in semiconductor technology, and manufacturing cost is relatively low.Can using plasma chemical vapour deposition (CVD) (PECVD), low-pressure chemical vapor deposition (LPCVD), the method such as rapid thermalization chemical vapour deposition (CVD) (RTCVD) or high density plasma deposition (HDP) being formed of stressor layers 110, the reacting gas of employing can comprise SiH
4, SiH
2cl
2, SiH
2f
2and NH
3described stressor layers 110 preferably thickness is 200 dust ~ 600 dusts, after forming stressor layers 110, in the high-temperature annealing process of described step S07, make stress be remembered in the Semiconductor substrate 100 of NMOS area 10, thus use stress to be able to stress application (namely during compression) in a longitudinal direction, the electron mobility of nmos pass transistor can be improved, and then improve nmos pass transistor drive current, further increase stress memory effect.
To sum up, compared to prior art, the present invention carries out pre-amorphous injection by the polysilicon layer to described NMOS area, the ion of pre-amorphous injection makes polysilicon layer be converted into amorphous silicon by polysilicon at subsequent high temperature annealing process, and in conversion process, produce stress, this effect of stress is in the Semiconductor substrate of described NMOS area, improve the stress memory effect of nmos pass transistor, the electron mobility of further raising nmos pass transistor and drive current, thus the object reaching the overall performance improving cmos device transistor.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (12)
1. a manufacture method for CMOS transistor, comprising:
There is provided semi-conductive substrate, described Semiconductor substrate comprises NMOS area and PMOS area;
Form dielectric layer and polysilicon layer successively on the semiconductor substrate;
Pre-amorphous injection is carried out to the polysilicon layer in described NMOS area;
Described polysilicon layer forms silicon nitride layer;
Silicon nitride layer, polysilicon layer and dielectric layer described in etched portions, to form NMOS gate stack in described NMOS area, described PMOS area forms PMOS gate stack;
Described NMOS gate stack sidewall forms NMOS grid curb wall, forms PMOS grid curb wall at described PMOS gate stack sidewall;
Carry out high-temperature annealing process.
2. the manufacture method of CMOS transistor as claimed in claim 1, is characterized in that, carry out the step of pre-amorphous injection, comprising to the polysilicon layer in described NMOS area:
At described polysilicon layer surface-coated photoresist layer;
Photoresist layer described in patterning, to remove the photoresist layer be positioned in described NMOS area, exposes the polysilicon layer of described NMOS area;
Polysilicon layer to the described NMOS area exposed carries out pre-amorphous injection;
Remove remaining photoresist layer.
3. the manufacture method of CMOS transistor as claimed in claim 1, is characterized in that, the injection ion of described pre-amorphous injection comprises boron, phosphorus, germanium, the one of arsenic or its combination.
4. the manufacture method of CMOS transistor as claimed in claim 1, it is characterized in that, the Implantation Energy of described pre-amorphous injection is 5KeV ~ 25KeV.
5. the manufacture method of CMOS transistor as claimed in claim 1, is characterized in that, between the step forming NMOS grid curb wall and PMOS grid curb wall and the step of carrying out high-temperature annealing process, also comprises:
In the Semiconductor substrate of described NMOS gate stack both sides, form NMOS source-drain area and be positioned at the NMOS metal silicide region above described NMOS source-drain area; And
In the Semiconductor substrate of described PMOS gate stack both sides, form PMOS source drain region and be positioned at the PMOS metal silicide region above described PMOS source drain region.
6. the manufacture method of CMOS transistor as claimed in claim 5, it is characterized in that, the material of described NMOS metal silicide region and PMOS metal silicide region is one in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and tantalum silicide or its combination.
7. the manufacture method of CMOS transistor as claimed in claim 1, is characterized in that, between the step forming described NMOS grid curb wall and PMOS grid curb wall and the step of carrying out high-temperature annealing process, is also included in described NMOS area surface coverage stressor layers.
8. the manufacture method of CMOS transistor as claimed in claim 7, it is characterized in that, the material of described stressor layers is silicon nitride, and thickness is 200 dust ~ 600 dusts.
9. the manufacture method of CMOS transistor as claimed in claim 7, is characterized in that, the stress that described stressor layers produces is-500MPa ~ 1600MPa.
10. as the manufacture method of CMOS transistor as described in any one in claim 1 to 9, it is characterized in that, the annealing temperature of described high-temperature annealing process is 900 DEG C ~ 1300 DEG C.
11. as the manufacture method of CMOS transistor as described in any one in claim 1 to 9, and it is characterized in that, the thickness of described polysilicon layer is 500 dust ~ 700 dusts.
12. as the manufacture method of CMOS transistor as described in any one in claim 1 to 7, and it is characterized in that, the thickness of described silicon nitride layer is 300 dust ~ 500 dusts.
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| CN104733395B (en) * | 2013-12-19 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A method of making semiconductor devices |
| CN104701234A (en) * | 2015-03-16 | 2015-06-10 | 上海华力微电子有限公司 | Manufacturing method of semiconductor device |
| CN106783557B (en) * | 2016-11-30 | 2019-11-26 | 上海华力微电子有限公司 | The preparation method of multiple graphical exposure mask |
| CN112635403B (en) * | 2021-03-09 | 2021-05-28 | 晶芯成(北京)科技有限公司 | Preparation method of static random access memory |
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