CN117712219A

CN117712219A - Solar cell and preparation method thereof

Info

Publication number: CN117712219A
Application number: CN202211100614.8A
Authority: CN
Inventors: 毛杰; 王钊; 郑霈霆; 杨洁; 张昕宇
Original assignee: Zhejiang Jinko Solar Co Ltd; Jinko Solar Co Ltd
Current assignee: Zhejiang Jinko Solar Co Ltd; Jinko Solar Co Ltd
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2024-03-15

Abstract

The embodiment of the application relates to a solar cell and a preparation method thereof, wherein the preparation method of the solar cell comprises the following steps: in the same process step, forming a first tunneling layer on the back surface of the substrate and forming an initial tunneling layer on the front surface of the substrate; in the same process step, a first polysilicon layer is formed on the surface of the first tunneling layer, and a second polysilicon layer is formed on the surface of the initial tunneling layer; performing a first doping process on the first polysilicon layer to form a first doped conductive layer with a second doping element; performing a second doping process on the second polysilicon layer to form an initial doped conductive layer with a third doping element, and diffusing the third doping element into part of the substrate to form an initial diffusion region; and removing part of the initial tunneling layer, part of the initial doped conductive layer and part of the initial diffusion region, forming a second tunneling layer and a second doped conductive layer on the front surface of the substrate aligned with the metal pattern region, and forming a diffusion region in the substrate aligned with the metal pattern region.

Description

Solar cell and preparation method thereof

Technical Field

The embodiment of the application relates to the field of solar cells, in particular to a preparation method of a solar cell and the solar cell.

Background

The solar cell has better photoelectric conversion capability, and in a tunneling oxide passivation contact cell (TOPCON), a tunneling oxide layer and a doped conductive layer are prepared on one surface of a substrate, so that carrier recombination on the surface of the substrate in the solar cell is inhibited and the passivation effect on the substrate is enhanced. The tunneling oxide layer has a good chemical passivation effect, and the doped conductive layer has a good field passivation effect. In addition, in order to transmit and collect photo-generated carriers generated by the solar cell, a metal front electrode is also prepared on the surface of the substrate, and the metal front electrode is in electrical contact with the doped conductive layer, so that the metal front electrode can collect carriers in the doped conductive layer.

However, the solar cell obtained by the current manufacturing method has a problem of poor photoelectric conversion performance.

Disclosure of Invention

The embodiment of the application provides a solar cell and a preparation method thereof, which are at least beneficial to improving the photoelectric conversion performance of the solar cell.

The embodiment of the application provides a preparation method of a solar cell, which comprises the steps of providing a substrate, wherein the substrate is provided with a front surface and a back surface which are opposite, and the substrate is provided with a first doping element; in the same process step, forming a first tunneling layer on the back surface of the substrate and forming an initial tunneling layer on the front surface of the substrate; in the same process step, a first polysilicon layer is formed on the surface of the first tunneling layer, and a second polysilicon layer is formed on the surface of the initial tunneling layer; performing a first doping process on the first polysilicon layer to form a first doped conductive layer with a second doping element; performing a second doping process on the second polysilicon layer to form an initial doped conductive layer with a third doping element, wherein the third doping element is further diffused into part of the substrate to form an initial diffusion region, and the type of the third doping element is the same as that of the first doping element and is different from that of the second doping element; and removing part of the initial tunneling layer, part of the initial doped conductive layer and part of the initial diffusion region to form a second tunneling layer and a second doped conductive layer on the front surface of the substrate aligned with the metal pattern region, and forming a diffusion region in the substrate aligned with the metal pattern region.

In addition, the method for forming the first polysilicon layer and the second polysilicon layer comprises the following steps: simultaneously performing a first deposition process on the back surface and the front surface of the substrate to form a first amorphous silicon layer on the surface of the first tunneling layer far away from the substrate, and forming a second amorphous silicon layer on the surface of the initial tunneling layer far away from the substrate; and simultaneously crystallizing the first amorphous silicon layer and the second amorphous silicon layer to convert the first amorphous silicon layer into a first polysilicon layer and convert the second amorphous silicon layer into a second polysilicon layer.

In addition, the crystallization process includes: and carrying out annealing heat treatment on the first amorphous silicon layer and the second amorphous silicon layer, wherein the annealing temperature is 800-1200 ℃.

In addition, the thickness of the second amorphous silicon layer formed is not greater than the thickness of the first amorphous silicon layer.

In addition, the third doping element concentration of the second doping conductive layer is greater than the second doping element concentration of the first doping conductive layer.

In addition, the concentration of the doping element in the first doped conductive layer is 4×10 ¹⁹ atom/cm ³ ～9×10 ¹⁹ atom/cm ³ The second doped conductive layer has a doping element concentration of 1×10 ²⁰ atom/cm ³ ～6×10 ²⁰ atom/cm ³ 。

In addition, the third doping element concentration of the diffusion region is smaller than the third doping element concentration of the second doping conductive layer.

In addition, the first diffusion regionThe concentration of the triple-doped element is 1 multiplied by 10 ¹⁵ atom/cm ³ ～1×10 ²¹ atom/cm ³ The first doping element concentration is 1×10 ¹⁴ atom/cm ³ ～1×10 ¹⁷ atom/cm ³ 。

In addition, before the step of performing the first doping process, the method further includes: forming a first mask layer on the surface of the second polysilicon layer away from the substrate, and before the step of forming the initial doped conductive layer, further comprising: and removing the first mask layer.

In addition, the method for removing a part of the initial tunneling layer, a part of the initial doped conductive layer and a part of the initial diffusion region includes: forming a second mask layer on the surface of the first doped conductive layer far away from the substrate; forming a third mask layer on the surface of the initial doped conductive layer far away from the substrate; removing the third mask layer, the initial tunneling layer, the initial doped conductive layer and the initial diffusion region of the nonmetallic pattern region by adopting a laser process, and exposing the substrate surface of the nonmetallic pattern region; and removing the second mask layer and the rest of the third mask layer.

In addition, before the step of forming the first tunneling layer and the initial tunneling layer, the method further includes: performing a first etching process on the front surface of the substrate to form a first texture structure on the front surface of the substrate, wherein the first texture structure on the front surface of the substrate aligned with the metal pattern region comprises: the first pyramid structure and the second pyramid structure, the one-dimensional size of the bottom of the first pyramid structure is larger than the one-dimensional size of the bottom of the second pyramid structure, and the occupied area of the first pyramid structure in the metal pattern area is a first duty ratio.

In addition, before the step of removing the second mask layer and the remaining third mask layer, the method further includes: performing a second etching process on the substrate surface of the exposed nonmetallic pattern area to form a second texture structure on the substrate surface of the nonmetallic pattern area, wherein the second texture structure comprises: the one-dimensional size of the bottom of the third pyramid structure is larger than that of the bottom of the fourth pyramid structure, the occupied area of the third pyramid structure in the nonmetallic pattern area is a second duty ratio, and the second duty ratio is smaller than the first duty ratio.

In addition, before the step of forming the first tunneling layer and the initial tunneling layer, the method further includes: and forming a third texture structure on the back surface of the substrate, wherein the roughness of the third texture structure is smaller than that of the first texture structure.

In addition, the method further comprises the steps of: and simultaneously performing a second deposition process on the back surface and the front surface of the substrate to form a first passivation layer on the back surface of the substrate and a second passivation layer on the front surface of the substrate, wherein the first passivation layer covers the surface of the first doped conductive layer far away from the substrate, a first part of the second passivation layer covers the surface of the second doped conductive layer far away from the substrate, and a second part of the second passivation layer covers the front surface of the substrate.

In addition, the method further comprises the steps of: and simultaneously carrying out metallization processes on the back surface and the front surface of the substrate to form a first electrode on the surface of the first passivation layer and a second electrode on the surface of the second passivation layer, wherein the first electrode is electrically contacted with the first doped conductive layer, and the second electrode is electrically contacted with the second doped conductive layer.

In addition, the ratio of the width of the second electrode to the width of the substrate is 0.01 to 0.15.

The width of the second electrode is 20-100 μm.

In addition, the first doping element type is N-type, the second doping element type is P-type, and the third doping element type is N-type.

Correspondingly, another aspect of the embodiments of the present application further provides a solar cell, which is prepared by using the preparation method of the solar cell described in any one of the above, and includes: a substrate having an opposite front side and a back side; the first tunneling layer and the first doped conductive layer are positioned on the back surface of the substrate and are sequentially arranged in the direction away from the substrate; the second tunneling layer and the second doped conductive layer are positioned on the front surface of the substrate aligned with the metal pattern area and are sequentially arranged along the direction away from the substrate, and the doping element type of the second doped conductive layer is the same as the doping element type in the substrate and is different from the doping element type of the first doped conductive layer; and the diffusion region is positioned in the substrate aligned with the metal pattern region, the top of the diffusion region is contacted with the bottom surface of the second tunneling layer, and the doping element concentration of the diffusion region is greater than that in the substrate.

The technical scheme provided by the embodiment of the application has at least the following advantages:

in the technical scheme of the preparation method of the solar cell, the first tunneling layer and the initial tunneling layer are formed on the front surface and the back surface of the substrate at the same time, and the first polycrystalline silicon layer and the second polycrystalline silicon layer are formed on the back surface and the front surface of the substrate at the same time, so that the multi-step winding plating removing process can be avoided, the process flow can be greatly simplified, the process damage to the substrate caused by the multi-step winding plating removing process can be avoided, and the stability of the solar cell is maintained. And then, performing a first doping process on the first polysilicon layer, converting the first polysilicon layer into a first doped conductive layer, performing a second doping process on the second polysilicon layer, and forming an initial diffusion region in the substrate by the second doping process, so that the doping element concentration of the initial diffusion region is greater than that of the substrate, and thus, carriers in the substrate can be transmitted into the initial doped conductive layer through the initial diffusion region, and the initial diffusion region plays a role of a carrier transmission channel. And then removing part of the front film layer, and forming a second tunneling layer, a second doped conductive layer and a diffusion region only in the metal pattern region, so that the light absorption of the second doped conductive layer to incident light rays can be reduced. In addition, the doping element concentration of the first doping conductive layer is different from that of the substrate, so that a PN junction is formed with the substrate, that is, the second doping conductive layer on the front side does not form a PN junction with the substrate, and the problem that the formed PN junction causes serious carrier recombination in a metal pattern area on the front side can be avoided.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise.

Fig. 1 is a schematic cross-sectional structure corresponding to a step of providing a substrate in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram corresponding to a step of performing a first etching process in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional structure diagram corresponding to steps of forming a first tunneling layer and an initial tunneling layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 4 is a schematic cross-sectional structure diagram corresponding to a step of forming a first amorphous silicon layer and a second amorphous silicon layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional structure diagram corresponding to a step of forming a first doped conductive layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 6 is a schematic top view structure diagram corresponding to a step of forming an initial doped conductive layer and an initial diffusion region in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

Fig. 7 to 9 are schematic top view structures corresponding to steps of forming a second tunneling layer, a second doped conductive layer and a diffusion region in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 10 is a schematic top view corresponding to a step of performing a second etching process in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 11 is a schematic top view structure diagram corresponding to a step of forming a first passivation layer and a second passivation layer in a method for manufacturing a solar cell according to an embodiment of the present application;

fig. 12 is a schematic top view structure diagram corresponding to a step of forming a first electrode and a second electrode in a method for manufacturing a solar cell according to an embodiment of the present application.

Detailed Description

As known from the background art, the current solar cell has poor photoelectric conversion performance.

Analysis shows that one of the reasons for poor photoelectric conversion performance of the current solar cell is that in the current solar cell, a diffusion process is adopted to convert part of the substrate into an emitter on the front surface of the substrate, the emitter is used for forming a PN junction with an undiffused substrate, and a passivation contact structure is formed on the back surface of the substrate and is used for passivating the substrate. The structure not only can cause excessive carrier recombination in the metal pattern area on the front surface of the substrate, but also can influence the open-circuit voltage and the conversion efficiency of the solar cell. Also, because the front surface of the substrate is different from the structure of the back surface of the substrate, in the process of actually manufacturing the solar cell, different processes are required to be performed on the front surface and the back surface of the substrate respectively to form the passivation contact structure of the emitter and the back surface of the front surface. During processing of either the front substrate surface or the back substrate surface, the other of the front substrate surface or the back substrate surface and the side surface of the substrate are affected, for example, the doping element on the front substrate surface is diffused to the side surface of the substrate and the back substrate surface. Based on this, in a subsequent step, the doped portions of the substrate side and the substrate back need to be removed, which step is commonly referred to as de-wrap plating. However, in the process step of de-winding plating, a process damage is actually generated on the substrate, so that the stability of the substrate is affected, and the photoelectric conversion performance of the solar cell is affected.

In order to reduce the number of times of winding and plating on a substrate, the solar cell is provided with a double-sided TOPCON structure, so that a first tunneling layer and an initial tunneling layer can be formed on the front side and the back side of the substrate in the same process step, and a first polysilicon layer and a second polysilicon layer are also formed on the front side and the back side of the substrate at the same time, thereby reducing the number of times of winding and plating and reducing process damage to the substrate. And then, respectively carrying out doping process on the first polysilicon layer and the second polysilicon layer to form a first doped conductive layer and an initial doped conductive layer. During the process of forming the initially doped conductive layer, a portion of the dopant element also diffuses into the substrate to form an initially diffused region. And then removing part of the film layer on the front surface, and forming a second tunneling layer, a second doped conductive layer and a diffusion region only in the metal pattern region, so that parasitic absorption of the second doped conductive layer on incident light rays can be reduced. Meanwhile, in order to keep the concentration of the carriers transmitted in the second doped conductive layer higher, a diffusion region is formed, the diffusion region plays a role of a carrier transmission channel, the transmission efficiency of the carriers in the substrate to the second doped conductive layer can be improved, and the photoelectric conversion performance of the solar cell is further improved.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Referring to fig. 1, a substrate 100 is provided, the substrate 100 having opposite front and back surfaces, the substrate 100 having a first doping element.

The substrate 100 is used for receiving incident light and generating photo-generated carriers, and both the front and back sides of the substrate 100 can be used for receiving incident light or reflected light. In some embodiments, the substrate 100 may be a silicon substrate, and the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

In some embodiments, the first doping element type is N-type, i.e., the substrate 100 may be an N-type semiconductor substrate, and the N-type doping element may be any one of phosphorus, arsenic, or antimony.

In other embodiments, the first doping element type may be P-type, that is, the substrate 100 may be a P-type semiconductor substrate, and the P-type doping element may be any one of boron, gallium or indium.

The front surface of the substrate 100 has a metal pattern region defined as an electrode region and a non-metal pattern region defined as a region of the front surface of the substrate 100 other than the metal pattern region.

In some embodiments, prior to the step of forming the first tunneling layer and the initial tunneling layer, comprising:

referring to fig. 2, a first etching process is performed on the front surface of the substrate 100 to form a first texture structure 10 on the front surface of the substrate 100, the first texture structure 10 of the front surface of the substrate 100 aligned with the metal pattern region includes: the first pyramid structure 11 and the second pyramid structure 12, the one-dimensional size of the bottom of the first pyramid structure 11 is larger than the one-dimensional size of the bottom of the second pyramid structure 12, and the occupied area of the first pyramid structure 11 in the metal pattern area is a first duty ratio. In some embodiments, the first duty ratio may be close to 1, for example, may be 0.8 to 0.9, so that the duty ratio of the first pyramid structure 11 with a larger size in the metal pattern area is larger, not only the uniformity of the size of the first texture structure 10 in the metal pattern area can be improved, but also the deposition probability at different positions in the metal pattern area is close in the step of actually depositing the initial tunneling layer, and the uniformity of the formed initial tunneling layer and the initially doped polysilicon layer is improved, so that the passivation performance of the subsequently formed second tunneling layer and the second doped conductive layer can be improved. In addition, in the metal pattern area, the roughness of the first texture structure 10 is larger, so that the contact area between the metal electrode and the first texture structure 10 is larger when the metal electrode is formed later, the contact resistance between the metal electrode and the second doped conductive layer can be reduced, the width of the formed metal electrode can be reduced under the condition that the contact resistance is kept unchanged, the shielding of the metal electrode on incident light can be reduced, and the absorption and utilization rate of the front surface of the substrate 100 on the incident light can be further improved.

In some embodiments, the first pyramid structure 11 and the second pyramid structure 12 may be tetrahedral, approximately tetrahedral, pentahedral, or approximately pentahedral structures.

In some embodiments, a method of forming the first texture 10 may comprise: the front surface of the substrate 100 may be cleaned by chemical etching, for example, using a mixed solution of potassium hydroxide and hydrogen peroxide solution, and specifically, the first texture 10 having a morphology conforming to the expected shape may be formed by controlling the ratio of the concentrations of the potassium hydroxide and the hydrogen peroxide solution. In other embodiments, the first texture structure 10 may be formed by laser etching, mechanical etching, plasma etching, or the like. In the laser etching, only the laser process parameters need to be controlled, so that the first texture structure 10 with the shape meeting the expectations can be obtained.

In some embodiments, prior to the step of forming the first tunneling layer and the initial tunneling layer, further comprising: a third texture is formed on the back side of the substrate 100, the roughness of the third texture being less than the roughness of the first texture 10. Therefore, the uniformity of the first tunneling layer and the first doped conductive layer deposited on the back surface is higher, and the first tunneling layer and the first doped conductive layer have higher flatness, so that on one hand, the passivation performance of the first tunneling layer and the first doped conductive layer is improved, on the other hand, the contact interface between the first tunneling layer and the back surface of the substrate 100 is good, the interface defect is reduced, and the photo-generated carriers generated by the PN junction formed by the second doped conductive layer and the substrate 100 can be transmitted to the substrate 100 through the second tunneling layer more, thereby improving the concentration of carriers in the substrate 100 and reducing the open circuit voltage and the short circuit current.

It should be noted that, in some embodiments, before the third texture is formed on the back surface of the substrate 100, a protective layer is further formed on the front surface of the substrate 100 to prevent damage to the topography of the front surface of the substrate 100 during the step of forming the third texture. In some embodiments, the material of the protective layer may be silicon oxide.

Referring to fig. 2, in some embodiments, the third texture may comprise: the bottom dimension of the land relief structures 13 is greater than the bottom dimension of the first pyramid structures 11, and the height of the land relief structures 13 is less than the height of the first pyramid structures 11. The land relief structures 13 may be the base portion of the pyramid structure, i.e., the structure remaining after the pyramid structure has been tipped off. That is, the flat surface of the top of the land relief structure 13, thereby making the roughness of the third texture smaller.

In some embodiments, when the third texture feature comprises the land relief feature 13, the method of forming the third texture feature may comprise:

the back side of the substrate 100 is subjected to an etching process to form an initial texture structure including a back side pyramid structure having a bottom one-dimensional size greater than that of the first pyramid structure 11. In some embodiments, the back pyramid structures may be formed using chemical etching, laser etching, mechanical or plasma etching, or the like. It is noted that in forming the back surface pyramid structure by chemical etching, the concentration of the potassium hydroxide and hydrogen peroxide solution used may be smaller than that used in forming the first pyramid structure 11, so that the bottom dimension of the back surface pyramid structure formed is larger than that of the first pyramid structure 11.

After the formation of the rear pyramid structure, the rear surface of the substrate 100 is subjected to a polishing process, and the polishing liquid used in the polishing process may be an alkali solution, for example, any one of NaOH solution and KOH solution. Specifically, droplets of the alkaline solution may be sprayed onto the back of the substrate 100 to perform roughening treatment, and then pre-cleaned with hydrofluoric acid; the rear surface of the substrate 100 is polished with a polishing liquid to remove the tower tip portion of the rear surface pyramid structure. The topography of the backside of the substrate 100 may be made to conform to expectations by controlling the polishing time and polishing temperature.

Referring to fig. 3, after forming the first texture structure 10 on the front surface of the substrate 100 and forming the third texture structure on the back surface of the substrate 100, in the same process step, the first tunneling layer 110 is formed on the back surface of the substrate 100, and the initial tunneling layer 101 is formed on the front surface of the substrate 100. The first tunneling layer 110 and the first initial tunneling layer 101 are used for implementing interface passivation of the substrate 100, and have a chemical passivation effect.

The formation of the first tunneling layer 110 and the first initial tunneling layer 101 in the same process step not only saves the process flow, but also reduces the number of times of de-winding plating compared to the formation of the first tunneling layer 110 on the back surface of the substrate 100 and the formation of the first initial tunneling layer 101 on the front surface of the substrate 100, respectively.

Specifically, if the first tunneling layer 110 is formed on the back surface of the substrate 100, a protection layer is first formed on the front surface of the substrate 100 to prevent the first tunneling layer 110 from affecting the front surface of the substrate 100. Then during the process step of forming the first tunneling layer 110, a wrap-around plating is also formed on the side of the substrate 100, and after the first tunneling layer 110 is formed, a first wrap-around plating step is required on the side of the substrate 100. After the first initial tunneling layer 101 is formed on the front surface of the substrate 100, in order to prevent the process of forming the first initial tunneling layer 101 from affecting the front surface of the substrate 100, a protective layer is further required to be formed on the back surface of the substrate 100, and during the process of forming the first initial tunneling layer 101, a winding plating is further formed on the side surface of the substrate 100, so that after the first initial tunneling layer 101 is formed, a second winding plating removing step is further required to remove the tunneling layer on the side surface of the substrate 100.

It will be appreciated that in the de-wrap step, a wet chemical process is required to clean the wrap formed on the sides of the substrate 100. That is, the de-plating step may not only remove the plating but also damage the substrate 100 due to the chemical wet process. In the embodiment of the present application, the first tunneling layer 110 and the first initial tunneling layer 101 are formed on the back surface and the front surface of the substrate 100 at the same time, so that on one hand, the step of forming the protective layer on the front surface and the back surface of the substrate 100 respectively can be omitted, and only one time of winding removal plating step is required after the first tunneling layer 110 and the first initial tunneling layer 101 are formed, thereby greatly simplifying the process steps and improving the process efficiency. In addition, since the front surface of the substrate 100 and the back surface of the substrate 100 do not need to form a protection layer, the protection layer does not need to be removed later, so that the process damage to the substrate 100 caused by the step of removing the protection layer is avoided, and the good performance of the substrate 100 is maintained.

In some embodiments, a method of forming the first tunneling layer 110 and the first initial tunneling layer 101 may include: deposition is performed on the back surface and the front surface of the substrate 100 by using a variable temperature chamber process and a chemical vapor deposition method, so as to form a first tunneling layer 110 and a first initial tunneling layer 101 respectively. During the deposition, the heating rate is controlled to be 0.5-3 ℃ per minute, for example, 1.0 ℃ per minute, 1.5 ℃ per minute, 2.0 ℃ per minute or 2.5 ℃ per minute, the deposition temperature is 560-620 ℃ for example, 570 ℃, 590 ℃ or 610 ℃ and the deposition time is 3-10 min, for example, 4min, 6min or 8 min. In other embodiments, when the materials of the first tunneling layer 110 and the first initial tunneling layer 101 are silicon oxide, an in-situ process, such as a thermal oxidation process and a nitric acid passivation process, may be used to generate the first tunneling layer 110 and the first initial tunneling layer 101 in-situ.

In some embodiments, the thickness of the first tunneling layer 110 and the first initial tunneling layer 101 may be 0.5nm to 5nm.

In some embodiments, the material of the first tunneling layer 110 and the second tunneling layer may be a dielectric material, for example, any one of silicon oxide, magnesium fluoride, silicon oxide, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide.

Referring to fig. 4, after forming the first tunneling layer 110 and the first initial tunneling layer 101, in the same process step, a first polysilicon layer 102 is formed on the surface of the first tunneling layer 110, and a second polysilicon layer 103 is formed on the surface of the first initial tunneling layer 101. Simultaneously, the first polysilicon layer 102 and the second polysilicon layer 103 can reduce the number of times of detour plating, and simultaneously, the process steps of forming protective layers on the surface of the first tunneling layer 110 and the surface of the first tunneling layer 101 respectively can be omitted, i.e. a plurality of process steps can be omitted, thereby reducing the damage of the substrate 100 caused by the process steps, maintaining the stability of the substrate 100, and being beneficial to maintaining the better performance of the solar cell.

In some embodiments, the method of forming the first polysilicon layer 102 and the second polysilicon layer 103 includes:

a first deposition process is performed simultaneously on the back surface and the front surface of the substrate 100, so as to form a first amorphous silicon layer on the surface of the first tunneling layer 110 away from the substrate 100, and form a second amorphous silicon layer on the surface of the first tunneling layer 101 away from the substrate 100. In some embodiments, the first amorphous silicon layer and the second amorphous silicon layer may be formed using a plasma chemical vapor deposition method.

In some embodiments, the thickness of the second amorphous silicon layer formed is not greater than the thickness of the first amorphous silicon layer. Specifically, in some embodiments, the second amorphous silicon layer may be formed to a thickness of 20nm to 300nm, for example, 20nm to 50nm, 50nm to 100nm, 100nm to 150nm, 150nm to 200nm, 200nm to 250nm, or 250nm to 300nm. The thickness of the first amorphous silicon layer formed may be 50nm to 500nm, and may be, for example, 50nm to 100nm, 100nm to 150nm, 150nm to 200nm, 200nm to 250nm, 250nm to 300nm, 300nm to 350nm, 350nm to 400nm, 400nm to 450nm, or 450nm to 500nm. The first amorphous silicon layer and the second amorphous silicon layer are used for forming the first doped conductive layer and the second doped conductive layer later, so that the thicknesses of the first amorphous silicon layer and the second amorphous silicon layer are set within the range, on one hand, the thicknesses of the second doped conductive layer formed later are smaller, and therefore parasitic absorption of incident light emitted to the front surface by the second doped conductive layer can be reduced. On the other hand, because the thickness of the first amorphous silicon layer is larger, in the subsequent step of performing the first doping process on the first amorphous silicon layer, the problem that the doped elements diffused into the first amorphous silicon layer due to the fact that the first amorphous silicon layer is too thin are accumulated between the back surface of the substrate 100 and the interface of the first amorphous silicon layer to form a dead layer can be reduced, and therefore the efficiency of carrier transmission to the substrate 100 can be improved, and the generation of a carrier recombination center is reduced.

The first amorphous silicon layer and the second amorphous silicon layer are simultaneously crystallized to convert the first amorphous silicon layer into the first polysilicon layer 102 and the second amorphous silicon layer into the second polysilicon layer 103. In the embodiment of the present application, passivation contact structures are disposed on the front surface of the substrate 100 and the back surface of the substrate 100, that is, the front surface film layer is the same as the back surface film layer, so that a first amorphous silicon layer and a second amorphous silicon layer can be formed on the front surface of the substrate 100 and the back surface of the substrate 100 simultaneously, and then the first amorphous silicon layer and the second amorphous silicon layer are crystallized simultaneously, so that the number of steps of winding and plating is reduced, the stability of the substrate 100 is improved, and the cost is greatly reduced.

In some embodiments, the crystallization process includes: and carrying out annealing heat treatment on the first amorphous silicon layer and the second amorphous silicon layer, wherein the annealing temperature is 800-1200 ℃. In this temperature range, on the one hand, the annealing temperature is not too low, so that sufficient crystallization of the first amorphous silicon layer and the second amorphous silicon layer can be ensured. On the other hand, the annealing temperature is not excessively high, so that it is possible to prevent the problem of damage to the substrate 100 due to the excessively high annealing temperature.

Referring to fig. 5, after forming the first polysilicon layer 102 and the second polysilicon layer 103, a first doping process is performed on the first polysilicon layer 102 to form a first doped conductive layer 130 having a second doping element. In some embodiments, the second doping element is of a different type than the first doping element, such that the first doped conductive layer 130 forms a PN junction with the substrate 100, forming a back junction structure. The second doped conductive layer is formed on the back surface of the substrate 100, so that the area of the PN junction is larger, on one hand, the number of photo-generated carriers generated by the PN junction is larger, and on the other hand, the electrostatic field formed by the second doped conductive layer and directed to the back surface of the substrate 100 is larger, which is favorable for carrier migration and improves the open-circuit voltage and the short-circuit current. In addition, forming the PN junction at the back surface can also prevent serious carrier recombination problems in the metal pattern region of the front surface of the substrate 100 due to the formation of the PN junction at the front surface of the substrate 100, thereby improving the double-sided rate.

In some embodiments, referring to fig. 4, before the step of performing the first doping process, further comprises: forming a first mask layer 104 on a surface of the second polysilicon layer 103 remote from the substrate 100, referring to fig. 5, and before the step of forming the initially doped conductive layer, further includes: the first mask layer 104 is removed. Since the first doping process and the subsequent second doping process performed on the second polysilicon layer 103 are performed in different process steps, forming the first mask layer 104 on the surface of the second polysilicon layer 103 before performing the first doping process is beneficial to protecting the second polysilicon layer 103 from the first doping process. In some embodiments, a deposition process may be used to form the first mask layer 104 on the surface of the second polysilicon layer 103, and the material of the first mask layer 104 may be silicon oxide. In some embodiments, the thickness of the first mask layer 104 may be 40nm to 150nm.

After forming the first mask layer 104, a first doping process is performed on the first polysilicon layer 102 located on the back side of the substrate 100, which may be any one of an ion implantation process or a source diffusion process in some embodiments. In some embodiments, when the first doping element is N-type, the second doping element may be P-type, thereby forming a PN junction with the substrate 100. Specifically, in some embodiments, the second doping element may be boron, and the doping source employed in the first doping process may be any one of boron trichloride, boron tribromide, diborane.

In some embodiments, after forming the first doped conductive layer 130, the first mask layer 104 may be removed using an etching process, which may include any one of a dry etching process, a wet etching process, or a laser etching process.

Referring to fig. 6, after the first doping process, a second doping process is performed on the second polysilicon layer 103 (refer to fig. 5) to form an initially doped conductive layer 20 having a third doping element that is also diffused into a portion of the substrate 100 to form an initially diffused region 21, and the third doping element is of the same type as the first doping element and of a different type from the second doping element. Since the first doping element type of the substrate 100 is the same as the third doping element type, the third doping element is also diffused into a portion of the substrate 100 in the second doping process, so that the initial diffusion region 21 is formed with a doping element concentration greater than that of the substrate 100, i.e., the initial diffusion region 21 is a heavily doped region compared to the substrate 100, and the initial diffusion region 21 is subsequently used to form a diffusion region, i.e., the diffusion region is a heavily doped region compared to the substrate 100. The heavily doped region forms a high-low junction with the substrate 100, and the presence of the high-low junction can create a barrier effect for carriers, thereby increasing the rate and amount of carrier transport to the diffusion region in the substrate 100, so that the second doped conductive layer effectively collects carriers.

In some embodiments, the second doping process may be any one of an ion implantation process or a source diffusion process. In some embodiments, when the first doping element is N-type, the third doping element is N-type. Specifically, in some embodiments, the third doping element may be phosphorus, and the doping source used in the second doping process may be phosphorus oxychloride. It will be appreciated that the initial diffusion region 21 may be formed by adjusting the concentration of the dopant source such that the third dopant element also diffuses into a portion of the substrate 100.

The first tunneling layer 101, the initially doped conductive layer 20 and the initially diffusion region 21 are used for forming a second tunneling layer, a second doped conductive layer and a diffusion region, wherein the second tunneling layer, the second doped conductive layer and the diffusion are all located in the metal pattern region. In this way, parasitic absorption of incident light rays incident on the front surface by the second doped conductive layer can be reduced.

It is readily found that the doping element concentration of the subsequently formed second doped conductive layer and the doping element concentration of the diffusion region are determined by the doping element concentration of the initially doped conductive layer 20 formed by the second doping process. In some embodiments, the third doping element concentration of the second doped conductive layer is greater than the second doping element concentration of the first doped conductive layer 130. That is, the doping element concentration of the second doping process is greater than the doping element concentration of the first doping process. The concentration of the third doping element of the second doped conductive layer is larger, so that the sheet resistance of the second doped conductive layer is smaller, and the contact recombination loss between the second doped conductive layer and the metal electrode is reduced. The concentration of the doping element of the first doped conductive layer 130 is set to be smaller, on one hand, auger recombination of the first doped conductive layer 130 can be reduced, good passivation performance of the first doped conductive layer 130 is maintained, on the other hand, the concentration of the second doping element is set to be smaller, and the problem that the second doping element is accumulated at the contact interface between the substrate 100 and the first tunneling layer 110 can be prevented, so that a dead layer is prevented from being formed, and the mobility of photo-generated carriers is improved . Specifically, in some embodiments, the concentration of the doping element in the first doped conductive layer 130 is 4×10 ¹⁹ atom/cm ³ ～9×10 ¹⁹ atom/cm ³ For example, it may be 4X 10 ¹⁹ atom/cm ³ ～5×10 ¹⁹ atom/cm ³ 、5×10 ¹⁹ atom/cm ³ ～6×10 ¹⁹ atom/cm ³ 、6×10 ¹⁹ atom/cm ³ ～7×10 ¹⁹ atom/cm ³ 、7×10 ¹⁹ atom/cm ³ ～8×10 ¹⁹ atom/cm ³ Or 8X 10 ¹⁹ atom/cm ³ ～9×10 ¹⁹ atom/cm ³ The method comprises the steps of carrying out a first treatment on the surface of the The doping element concentration of the second doped conductive layer is 1×10 ²⁰ atom/cm ³ ～6×10 ²⁰ atom/cm ³ For example, it may be 1X 10 ²⁰ atom/cm ³ ～2×10 ²⁰ atom/cm ³ 、2×10 ²⁰ atom/cm ³ ～3×10 ²⁰ atom/cm ³ 、3×10 ²⁰ atom/cm ³ ～4×10 ²⁰ atom/cm ³ 、4×10 ²⁰ atom/cm ³ ～5×10 ²⁰ atom/cm ³ Or 5X 10 ²⁰ atom/cm ³ ～6×10 ²⁰ atom/cm ³ 。

In some embodiments, the third doping element concentration of the diffusion region is less than the third doping element concentration of the second doped conductive layer. Therefore, on one hand, the doping element concentration of the doping layer is higher, the sheet resistance of the second doping conductive layer is lower, so that a strong electrostatic field is formed on the second doping conductive layer, the field passivation effect of the second doping conductive layer is obviously improved, the recombination of carriers on the front face is further inhibited, the carrier concentration is improved, the short-circuit current and the open-circuit voltage are increased, and the photoelectric conversion performance of the solar cell is further improved. On the other hand, in the direction that the second doped conductive layer points to the substrate 100, a concentration gradient is formed among the second doped conductive layer, the diffusion region and the substrate 100, so that the second doped conductive layer and the diffusion region have a fermi level difference, and energy band bending is caused on the front surface of the substrate 100 aligned to the metal pattern region, so that the passage of minority carriers can be effectively blocked, the transmission of the majority carriers cannot be influenced, the selective collection of carriers is realized, and the collection capability of the carriers is further enhanced.

Specifically, in some embodiments, the third dopant concentration of the diffusion region is 1×10 ¹⁵ atom/cm ³ ～1×10 ²¹ atom/cm ³ For example, it may be 1X 10 ¹⁵ atom/cm ³ ～1×10 ¹⁶ atom/cm ³ 、1×10 ¹⁶ atom/cm ³ ～1×10 ¹⁷ atom/cm ³ 、1×10 ¹⁷ atom/cm ³ ～1×10 ¹⁸ atom/cm ³ 、1×10 ¹⁸ atom/cm ³ ～1×10 ¹⁹ atom/cm ³ 、1×10 ¹⁹ atom/cm ³ ～1×10 ²⁰ atom/cm ³ Or 1X 10 ²⁰ atom/cm ³ ～1×10 ²¹ atom/cm ³ . The first doping element has a concentration of 1×10 ¹⁴ atom/cm ³ ～1×10 ¹⁷ atom/cm ³ For example, it may be 1X 10 ¹⁴ atom/cm ³ ～1×10 ¹⁵ atom/cm ³ 、1×10 ¹⁵ atom/cm ³ ～1×10 ¹⁶ atom/cm ³ Or 1X 10 ¹⁶ atom/cm ³ ～1×10 ¹⁷ atom/cm. When the concentration of the third doping element in the diffusion region and the concentration of the first doping element in the substrate 100 are within this range, recombination of the second doping conductive layer on the front surface of the substrate 100 can be suppressed, and selective transmission of carriers can be better realized, so that the collection capability of carriers is enhanced.

Referring to fig. 7 to 9, in particular, a method of forming a second tunneling layer, a second doped conductive layer, and a diffusion region includes: after the second doping process is performed, a portion of the first tunneling layer 101, a portion of the initially doped conductive layer 20, and a portion of the initially diffused region 21 are removed to form the second tunneling layer 120, the second doped conductive layer 140 on the front surface of the metal pattern region-aligned substrate 100, and to form the diffused region 150 in the metal pattern region-aligned substrate 100. It is not difficult to find that in the step of diffusing the second polysilicon layer 103 to form the initially doped conductive layer 20, a portion of the substrate 100 is simultaneously doped to form the initially diffused region 21, and in the step of removing the initially doped conductive layer 20 to form the second doped conductive layer 140, a portion of the initially diffused region 21 is simultaneously removed to form the diffused region 150. It can be seen that, in the embodiment of the present application, the diffusion region 150 can be formed without using an additional step, so that the process flow can be greatly saved and the cost can be saved.

It can be understood that, in the embodiment of the present application, the second doped conductive layer 140 is formed only on the front surface of the substrate 100 aligned with the metal pattern region, so that the area of the second doped conductive layer 140 is smaller, in order to reduce the parasitic absorption of the second doped conductive layer 140 to the incident light and simultaneously maintain the stronger collection capability of the second doped conductive layer 140 to the carriers, the diffusion region 150 is disposed in the substrate 100 aligned with the metal pattern region, and the diffusion region 150 serves as a heavily doped region and plays a role of a carrier transmission channel, so that the transmission efficiency of the carriers in the substrate 100 to the second doped conductive layer 140 can be improved. And the diffusion region 150 is only arranged in the substrate 100 aligned with the metal pattern region, so that the carriers in the substrate 100 can be prevented from being transmitted to the front surface of the substrate 100 aligned with the nonmetal pattern region, and the problem of excessive carrier recombination caused by accumulation of the carriers on the front surface of the substrate 100 aligned with the nonmetal pattern region is further avoided.

In some embodiments, the method of removing a portion of the first initial tunneling layer 101, a portion of the initially doped conductive layer 20, and a portion of the initial diffusion region 15021 includes:

referring to fig. 7, a second mask layer 106 is formed on a surface of the first doped conductive layer 130 away from the substrate 100, and the second mask layer 106 is used to protect the first doped conductive layer 130 from damage during the process of removing a portion of the first tunneling layer 101, a portion of the initially doped conductive layer 20, and a portion of the initially diffusion region 15021. In some embodiments, the material of the second mask layer 106 may be silicon oxide, and the thickness of the second mask layer 106 may be 40nm to 150nm. In some embodiments, the second mask layer 106 may be formed using a deposition process, such as plasma chemical vapor deposition.

Referring to fig. 7, a third mask layer 105 is formed on a surface of the initially doped conductive layer 20 remote from the substrate 100. The third mask layer 105 is used to perform a patterning process to define the openings of the initially doped conductive layer 20 that need to be etched away.

Referring to fig. 8 and 9, the third mask layer 105, the first initial tunneling layer 101, the initially doped conductive layer 20, and the initial diffusion region 15021 of the non-metal pattern region are removed using a laser process, exposing the surface of the substrate 100 of the non-metal pattern region. Specifically, referring to fig. 8, in some embodiments, a laser process may first be employed to remove the non-metal pattern region aligned third mask layer 105 to expose the initially doped conductive layer 20 of the non-metal pattern region alignment. And the remaining part of the third mask layer 105 which is not removed still covers the surface of the initially doped conductive layer 20 aligned with the metal pattern region, so as to prevent the process damage to the initially doped conductive layer 20 in the metal pattern region in the laser process. Referring to fig. 9, the initially doped conductive layer 20, the first initial tunneling layer 101, and the initial diffusion region 15021 exposing the top surface are then etched using a laser process. The first tunneling layer 101, the initially doped conductive layer 20, and the initially diffused region 15021 in the metal pattern region serve as the second tunneling layer 120, the second doped conductive layer 140, and the diffused region 150.

The laser process can precisely remove the portion to be removed, so that the laser process is used to remove the first tunneling layer 101, the initially doped conductive layer 20 and the initially diffusion region 15021 in the non-metal pattern region, and process damage to the first tunneling layer 101, the initially doped conductive layer 20 and the initially diffusion region 15021 in the metal pattern region can be avoided, so that the formed second tunneling layer 120, second doped conductive layer 140 and diffusion region 150 maintain good stability.

The second mask layer 106 and the remaining third mask layer 105 are removed. In some embodiments, either a wet etching process or a dry etching process may be employed to remove the second mask layer 106 and the remaining third mask layer 105.

In some embodiments, before the step of removing the second mask layer 106 and the remaining third mask layer 105, further comprises:

referring to fig. 10, a second etching process is performed on the surface of the substrate 100 where the non-metal pattern region is exposed to form a second texture 14 on the surface of the substrate 100 where the non-metal pattern region is formed, the second texture 14 including: the third pyramid structure 15 and the fourth pyramid structure 16, the one-dimensional size of the bottom of the third pyramid structure 15 is larger than the one-dimensional size of the bottom of the fourth pyramid structure 16, the area occupied by the third pyramid structure 15 in the non-metal pattern area is a second duty ratio, and the second duty ratio is smaller than the first duty ratio. That is, the area of the first pyramid structures 11 with larger size is smaller in the non-metal pattern region than in the metal pattern region, so that the roughness of the second pyramid structures 14 in the non-metal pattern region is smaller than in the metal pattern region, and the reflectivity of the non-metal pattern region to the incident light is lower, so that the absorption of the incident light by the non-metal pattern region can be increased. While the first texture structures 10 in the metal pattern area are higher in size uniformity and larger in roughness. In this way, in the step of actually depositing the first tunneling layer 101 and the first amorphous silicon layer, the deposition probability at different positions of the metal pattern region is close, so as to improve the thickness uniformity of the formed second tunneling layer 120 and the second doped conductive layer 140, thereby reducing the interface defect at the junction between the second tunneling layer 120 and the front surface of the substrate 100, and improving the number of carriers in the substrate 100 transferred to the second doped conductive layer 140. Specifically, in some embodiments, the first duty cycle may be 80% to 90%, and the second duty cycle may be 50% to 70%.

The second etching process is performed on the front surface of the substrate 100 aligned to the non-metal pattern region before the step of removing the second mask layer 106 and the remaining third mask layer 105, so that the second mask layer 106 and the remaining third mask layer 105 can still protect the second doped conductive layer 140 and the first doped conductive layer 130 from being damaged by the second etching process.

In some embodiments, the third pyramid structure 15 and the fourth pyramid structure 16 may be tetrahedral, approximately tetrahedral, pentahedral, or approximately pentahedral structures, among others.

In some embodiments, a method of forming the second texture 14 may include: the front surface of the substrate 100 in the non-metal region may be cleaned by, for example, chemical etching using a mixed solution of a potassium hydroxide solution and a hydrogen peroxide solution, and the concentration of the potassium hydroxide solution and the hydrogen peroxide solution used in forming the first texture 10 may be smaller than the concentration of the potassium hydroxide solution and the hydrogen peroxide solution used in ensuring that the third pyramid structures 15 with larger sizes are smaller in the front surface of the substrate 100 in the non-metal pattern region. In other embodiments, the second texture 14 may be formed by laser etching, mechanical etching, plasma etching, or the like.

Referring to fig. 11, in some embodiments, further comprising: a second deposition process is performed simultaneously on the back surface and the front surface of the substrate 100 to form a first passivation layer 160 on the back surface of the substrate 100 and a second passivation layer 170 on the front surface of the substrate 100, wherein the first passivation layer 160 covers the surface of the first doped conductive layer 130 away from the substrate 100, a first portion of the second passivation layer 170 covers the surface of the second doped conductive layer 140 away from the substrate 100, and a second portion of the second passivation layer 170 covers the front surface of the substrate 100.

The first passivation layer 160 may have a good passivation effect on the back surface of the substrate 100, and the second passivation layer 170 may have a good passivation effect on the front surface of the substrate 100. Specifically, the first passivation layer 160 and the second passivation layer 170 can perform better chemical passivation on dangling bonds on the surface of the substrate 100, reduce the defect state density on the surface of the substrate 100, and better inhibit carrier recombination on the front surface of the substrate 100.

The first portion of the second passivation layer 170 is directly contacted with the front surface of the substrate 100, so that the second tunneling layer 120 and the second doped conductive layer 140 are not disposed between the second passivation layer 170 and the substrate 100, and thus, the parasitic absorption problem of the second doped conductive layer 140 to the incident light can be reduced. And the second tunneling layer 120 and the second doped conductive layer 140 are not disposed on the front surface of the substrate 100 in consideration of the alignment of the second passivation layer 170 of the first portion. Therefore, the diffusion region 150 is not disposed in the substrate 100 aligned with the second passivation layer 170 of the first portion, so that the carrier concentration of the front surface of the substrate 100 in contact with the second passivation layer 170 of the first portion is not too high, and more carrier recombination problem on the front surface of the substrate 100 of the first portion can be prevented.

In some embodiments, the top surface of the first portion of the second passivation layer 170 is not flush with the top surface of the second portion of the second passivation layer 170. Specifically, in some embodiments. The top surface of the first portion of the second passivation layer 170 may be lower than the top surface of the second portion of the second passivation layer 170, so that the thickness of the first portion on the front surface of the substrate 100 is not too thick, and stress damage to the front surface of the substrate 100 due to the larger thickness of the first portion is prevented, so that more interface state defects are generated on the front surface of the substrate 100, and more carrier recombination centers are caused.

In some embodiments, the first passivation layer 160 and the second passivation layer 170 may be any one of a single layer structure or a multi-layer structure. In some embodiments, the material of the first passivation layer 160 and the second passivation layer 170 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

In some embodiments, the first passivation layer 160 and the second passivation layer 170 may be formed using an atomic layer deposition process. The first passivation layer 160 and the second passivation layer 170 are formed. Specifically, taking the material of the first passivation layer 160 and the second passivation layer 170 as aluminum oxide as an example, the method for forming the first passivation layer 160 and the second passivation layer 170 may include: and introducing trimethylaluminum and water into the reaction chamber, wherein the reaction temperature is 200-300 ℃.

Referring to fig. 12, in some embodiments, further comprising: a metallization process is performed simultaneously on the back surface of the substrate 100 and the front surface of the substrate 100 to form a first electrode 180 on the surface of the first passivation layer 160 and a second electrode 190 on the surface of the second passivation layer 170, wherein the first electrode 180 is electrically contacted with the first doped conductive layer 130 and the second electrode 190 is electrically contacted with the second doped conductive layer 140. Since the doping ion type of the second doped conductive layer 140 is the same as the doping ion type of the substrate 100, the metal contact recombination loss between the second electrode 190 and the second doped conductive layer 140 is reduced, and thus the carrier contact recombination between the second electrode 190 and the second doped conductive layer 140 can be reduced, and the short-circuit current and the photoelectric conversion performance of the solar cell are improved. In some embodiments, the second electrode 190 is formed on the front side of the substrate 100 where the metal pattern region is aligned.

In some embodiments, a method of forming the first electrode 180 and the second electrode 190 may include:

a metal paste is printed on the front side of the substrate 100 and the back side of the substrate 100 in the metal pattern region, and for example, the metal paste may be printed using a screen printing process, and the metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

The metal paste on the front side of the substrate 100 and the back side of the substrate 100 is simultaneously sintered at 750-850 ℃.

In some embodiments, the ratio of the width of the second electrode 190 to the width of the substrate 100 is 0.01 to 0.15, for example, may be 0.01 to 0.05, 0.05 to 0.08, 0.08 to 0.1, 0.1 to 0.13, or 0.13 to 0.15. In this range, the width of the second electrode 190 is smaller, so that the shielding effect of the second electrode 190 on the incident light can be reduced, and the absorption and utilization rate of the substrate 100 on the incident light can be improved. It can be appreciated that, since the front surface of the substrate 100 aligned with the metal pattern area has the first texture structure 10, and the roughness of the first texture structure 10 is larger, the top surface of the second doped conductive layer 140 deposited on the front surface of the substrate 100 aligned with the metal pattern area also has the morphology of the first texture structure 10, so that the second electrode 190 formed on the front surface of the substrate 100 in the metal pattern area has a larger contact resistance with the second doped conductive layer 140, therefore, even if the width of the second electrode 190 is smaller, good ohmic contact between the second electrode 190 and the second doped conductive layer 140 can be ensured, thereby improving the collection capability of the metal electrode to carriers. On the other hand, in this range, the width of the second electrode 190 is not too small compared to the substrate 100, so that the collection capability of the second electrode 190 for carriers can be ensured.

Specifically, in some embodiments, the second electrode 190 may be formed to have a width of 20 μm to 100 μm, for example, 20 μm to 30 μm, 30 μm to 45 μm, 45 μm to 60 μm, 60 μm to 80 μm, or 80 μm to 100 μm. In this range, the width of the second electrode 190 is smaller, so that the shielding of the second electrode 190 to the incident light is reduced, the strong collection capability of the second electrode 190 to carriers is maintained, and the photoelectric conversion performance of the solar cell is improved.

In the method for manufacturing a solar cell provided in the above embodiment, in the same process step, the first tunneling layer 110 and the first initial tunneling layer 101 are formed on the front surface and the back surface of the substrate 100, and the first polysilicon layer 102 and the second polysilicon layer 103 are also formed on the front surface and the back surface of the substrate 100 at the same time, so that the number of times of stripping and plating can be reduced, and the process damage to the substrate 100 can be reduced. Then, a doping process is performed on the first polysilicon layer 102 and the second polysilicon layer 103 to form a first doped conductive layer 130 and an initially doped conductive layer 20. During the process of forming the initially doped conductive layer 20, a portion of the doping element also diffuses into the substrate 100, forming an initial diffusion region 15021. Then, a portion of the front film layer is removed, and only the second tunneling layer 120, the second doped conductive layer 140 and the diffusion region 150 are formed in the metal pattern region, so that parasitic absorption of the second doped conductive layer 140 to the incident light can be reduced. Meanwhile, in order to keep the concentration of the carriers transported in the second doped conductive layer 140 higher, a diffusion region 150 is further formed, and the diffusion region 150 plays a role of a carrier transport channel, so that the transport efficiency of the carriers in the substrate 100 to the second doped conductive layer 140 can be improved, and the photoelectric conversion performance of the solar cell can be further improved.

Correspondingly, another aspect of the embodiments of the present application further provides a solar cell, which is prepared by using the preparation method of the solar cell provided in the foregoing embodiments, referring to fig. 12, the solar cell includes: a substrate 100, the substrate 100 having an opposite front surface and a back surface; a first tunneling layer 110 and a first doped conductive layer 130 located on the back surface of the substrate 100 and sequentially disposed in a direction away from the substrate 100; the second tunneling layer 120 and the second doped conductive layer 140 are located on the front surface of the substrate 100 aligned with the metal pattern region and sequentially disposed in a direction away from the substrate 100, and the doping element type of the second doped conductive layer 140 is the same as the doping element type in the substrate 100 and is different from the doping element type of the first doped conductive layer 130; the diffusion region 150, the diffusion region 150 is located in the substrate 100 aligned with the metal pattern region, the top of the diffusion region 150 contacts the bottom surface of the second tunneling layer 120, and the doping element concentration of the diffusion region 150 is greater than the doping element concentration in the substrate 100.

The second tunneling layer 120 and the second doped conductive layer 140 are formed only on the metal pattern region on the front surface of the substrate 100, and thus, absorption of incident light irradiated to the front surface by the second doped conductive layer 140 can be reduced. The first tunneling layer 110 and the first doped conductive layer 130 are disposed on the back surface, and the doped ion concentration of the first doped conductive layer 130 is different from that of the substrate 100, so that a PN junction is formed with the substrate 100, that is, the second doped conductive layer 140 on the front surface and the substrate 100 do not form a PN junction, so that the problem that the formed PN junction causes serious carrier recombination in the metal pattern area on the front surface can be avoided. In addition, the first tunneling layer 110 and the first doped conductive layer 130 on the back surface are covered on the back surface of the substrate 100, so that the area of the PN junction formed by the first doped conductive layer 130 and the substrate 100 is larger, the number of generated hole-electron pairs is larger, and the carrier concentration of carriers in the first doped conductive layer 130 and in the substrate 100 is increased.

In addition, the diffusion region 150 is formed only in the substrate 100 where the metal pattern regions are aligned, the diffusion region 150 may serve as a heavily doped region, and carriers in the substrate 100 may be more easily transferred into the doped conductive layer through the diffusion region 150, i.e., the diffusion region 150 functions as a carrier transfer channel. It should be noted that, in the embodiment of the present application, the diffusion region 150 is not disposed in the substrate 100 aligned with the non-metal pattern region, so that the carrier concentration of the front surface of the substrate 100 aligned with the non-metal pattern region is not too high, and the problem of serious carrier recombination on the front surface of the substrate 100 aligned with the non-metal pattern region is prevented. In addition, since the diffusion region 150 is disposed only in the substrate 100 aligned with the metal pattern region, the carriers in the substrate 100 can be intensively transferred into the diffusion region 150 and then transferred into the second doped conductive layer 140 through the diffusion region 150, so that the concentration of the carriers in the second doped conductive layer 140 can be greatly improved. In addition, the carriers in the substrate 100 can be prevented from being transmitted to the front surface of the substrate 100 aligned with the non-metal pattern region, so that the problem that the carriers are excessively compounded due to the fact that the carriers are accumulated on the front surface of the substrate 100 aligned with the non-metal pattern region and a dead layer is generated on the front surface of the substrate 100 aligned with the non-metal pattern region can be avoided, and the photoelectric conversion performance of the solar cell is improved as a whole.

While the preferred embodiment has been described, it is not intended to limit the scope of the claims, and any person skilled in the art can make several possible variations and modifications without departing from the spirit of the invention, so the scope of the invention shall be defined by the claims.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the present application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.

Claims

1. A method of manufacturing a solar cell, comprising:

providing a substrate having opposite front and back surfaces, the substrate having a first doping element;

in the same process step, forming a first tunneling layer on the back surface of the substrate and forming an initial tunneling layer on the front surface of the substrate;

in the same process step, a first polysilicon layer is formed on the surface of the first tunneling layer, and a second polysilicon layer is formed on the surface of the initial tunneling layer;

Performing a first doping process on the first polysilicon layer to form a first doped conductive layer with a second doping element;

performing a second doping process on the second polysilicon layer to form an initial doped conductive layer with a third doping element, wherein the third doping element is further diffused into part of the substrate to form an initial diffusion region, and the type of the third doping element is the same as that of the first doping element and is different from that of the second doping element;

and removing part of the initial tunneling layer, part of the initial doped conductive layer and part of the initial diffusion region to form a second tunneling layer and a second doped conductive layer on the front surface of the substrate aligned with the metal pattern region, and forming a diffusion region in the substrate aligned with the metal pattern region.

2. The method of claim 1, wherein the forming the first polysilicon layer and the second polysilicon layer comprises:

simultaneously performing a first deposition process on the back surface and the front surface of the substrate to form a first amorphous silicon layer on the surface of the first tunneling layer far away from the substrate, and forming a second amorphous silicon layer on the surface of the initial tunneling layer far away from the substrate;

And simultaneously crystallizing the first amorphous silicon layer and the second amorphous silicon layer to convert the first amorphous silicon layer into a first polysilicon layer and convert the second amorphous silicon layer into a second polysilicon layer.

3. The method of manufacturing a solar cell according to claim 2, wherein the crystallization process comprises: and carrying out annealing heat treatment on the first amorphous silicon layer and the second amorphous silicon layer, wherein the annealing temperature is 800-1200 ℃.

4. The method of manufacturing a solar cell according to claim 2, wherein the thickness of the second amorphous silicon layer formed is not greater than the thickness of the first amorphous silicon layer.

5. The method of claim 1, wherein the third doping element concentration of the second doped conductive layer is greater than the second doping element concentration of the first doped conductive layer.

6. The method according to claim 5, wherein a doping element concentration in the first doped conductive layer is 4×10 ¹⁹ atom/cm ³ ～9×10 ¹⁹ atom/cm ³ The second doped conductive layer has a doping element concentration of 1×10 ²⁰ atom/cm ³ ～6×10 ²⁰ atom/cm ³ 。

7. The method of claim 5, wherein the third doping element concentration of the diffusion region is less than the third doping element concentration of the second doped conductive layer.

8. The method of manufacturing a solar cell according to claim 7, wherein the third doping element concentration of the diffusion region is 1 x 10 ¹⁵ atom/cm ³ ～1×10 ²¹ atom/cm ³ The first doping element concentration is 1×10 ¹⁴ atom/cm ³ ～1×10 ¹⁷ atom/cm ³ 。

9. The method of claim 1, further comprising, prior to the step of performing the first doping process: forming a first mask layer on the surface of the second polysilicon layer away from the substrate, and before the step of forming the initial doped conductive layer, further comprising: and removing the first mask layer.

10. The method of claim 9, wherein the removing a portion of the initial tunneling layer, a portion of the initially doped conductive layer, and a portion of the initial diffusion region comprises:

forming a second mask layer on the surface of the first doped conductive layer far away from the substrate;

forming a third mask layer on the surface of the initial doped conductive layer far away from the substrate;

removing the third mask layer, the initial tunneling layer, the initial doped conductive layer and the initial diffusion region of the nonmetallic pattern region by adopting a laser process, and exposing the substrate surface of the nonmetallic pattern region;

And removing the second mask layer and the rest of the third mask layer.

11. The method of claim 10, further comprising, prior to the step of forming the first tunneling layer and the initial tunneling layer:

performing a first etching process on the front surface of the substrate to form a first texture structure on the front surface of the substrate, wherein the first texture structure on the front surface of the substrate aligned with the metal pattern region comprises: the first pyramid structure and the second pyramid structure, the one-dimensional size of the bottom of the first pyramid structure is larger than the one-dimensional size of the bottom of the second pyramid structure, and the occupied area of the first pyramid structure in the metal pattern area is a first duty ratio.

12. The method of claim 11, further comprising, prior to the step of removing the second mask layer and the remaining third mask layer:

performing a second etching process on the substrate surface of the exposed nonmetallic pattern area to form a second texture structure on the substrate surface of the nonmetallic pattern area, wherein the second texture structure comprises: the one-dimensional size of the bottom of the third pyramid structure is larger than that of the bottom of the fourth pyramid structure, the occupied area of the third pyramid structure in the nonmetallic pattern area is a second duty ratio, and the second duty ratio is smaller than the first duty ratio.

13. The method of claim 11, further comprising, prior to the step of forming the first tunneling layer and the initial tunneling layer: and forming a third texture structure on the back surface of the substrate, wherein the roughness of the third texture structure is smaller than that of the first texture structure.

14. The method of manufacturing a solar cell according to claim 1, 12 or 13, further comprising: and simultaneously performing a second deposition process on the back surface and the front surface of the substrate to form a first passivation layer on the back surface of the substrate and a second passivation layer on the front surface of the substrate, wherein the first passivation layer covers the surface of the first doped conductive layer far away from the substrate, a first part of the second passivation layer covers the surface of the second doped conductive layer far away from the substrate, and a second part of the second passivation layer covers the front surface of the substrate.

15. The method of manufacturing a solar cell according to claim 14, further comprising: and simultaneously carrying out metallization processes on the back surface and the front surface of the substrate to form a first electrode on the surface of the first passivation layer and a second electrode on the surface of the second passivation layer, wherein the first electrode is electrically contacted with the first doped conductive layer, and the second electrode is electrically contacted with the second doped conductive layer.

16. The method of claim 15, wherein the ratio of the width of the second electrode to the width of the substrate is 0.01 to 0.15.

17. The method of claim 16, wherein the second electrode has a width of 20 μm to 100 μm.

18. The method of claim 1, wherein the first doping element type is N-type, the second doping element type is P-type, and the third doping element type is N-type.

19. A solar cell prepared by the method of any one of claims 1 to 18, comprising:

a substrate having an opposite front side and a back side;

the first tunneling layer and the first doped conductive layer are positioned on the back surface of the substrate and are sequentially arranged in the direction away from the substrate;

the second tunneling layer and the second doped conductive layer are positioned on the front surface of the substrate aligned with the metal pattern area and are sequentially arranged along the direction away from the substrate, and the doping element type of the second doped conductive layer is the same as the doping element type in the substrate and is different from the doping element type of the first doped conductive layer;

And the diffusion region is positioned in the substrate aligned with the metal pattern region, the top of the diffusion region is contacted with the bottom surface of the second tunneling layer, and the doping element concentration of the diffusion region is greater than that in the substrate.