CN116314372A

CN116314372A - Solar cell, preparation method thereof and photovoltaic module

Info

Publication number: CN116314372A
Application number: CN202310184211.4A
Authority: CN
Inventors: 金井升; 张彼克; 杨楠楠
Original assignee: Zhejiang Jinko Solar Co Ltd; Jinko Solar Haining Co Ltd
Current assignee: Zhejiang Jinko Solar Co Ltd; Jinko Solar Haining Co Ltd
Priority date: 2023-02-23
Filing date: 2023-02-23
Publication date: 2023-06-23

Abstract

The embodiment of the application relates to a solar cell, a preparation method thereof and a photovoltaic module, wherein the solar cell comprises: the first surface of the substrate comprises first parts and second parts which are alternately arranged, and the first parts are recessed towards the second surface of the substrate relative to the second parts; the first tunneling layer covers the first part, the surface of the first tunneling layer facing the first part is provided with a first texture structure, the surface of the first tunneling layer far away from the first part is provided with a second texture structure, the flatness of the second texture structure is larger than that of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced protruding structures positioned on the polishing surface, and the occupied area of the protruding structures on the polishing surface is not larger than 1/2 of the area of the polishing surface; the first doped conductive layer covers the surface of the first tunneling layer far away from the substrate; a first electrode in electrical contact with the first doped conductive layer. The embodiment of the application is beneficial to improving the photoelectric conversion efficiency of the solar cell.

Description

Solar cell, preparation method thereof and photovoltaic module

Technical Field

The embodiment of the application relates to the field of solar cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module.

Background

The solar cell has better photoelectric conversion capability, and at present, a tunneling layer and a doped conductive layer are prepared on the surface of the substrate and are used for inhibiting carrier recombination on the surface of the substrate in the solar cell and enhancing passivation effect on the substrate. The tunneling layer has a good chemical passivation effect, and the doped conductive layer has a good field passivation effect. In addition, in order to transport and collect photo-generated carriers generated from the solar cell, an electrode in electrical contact with the doped conductive layer is also prepared for collecting the photo-generated carriers.

The number of photo-generated carriers is related to the absorption and utilization rate of the substrate to the incident light, and the higher the absorption and utilization rate of the substrate to the incident light is, the more photo-generated carriers are generated, so that the photoelectric conversion performance of the solar cell can be improved.

However, the photoelectric conversion performance of the solar cell is poor.

Disclosure of Invention

The embodiment of the application provides a solar cell, a preparation method thereof and a photovoltaic module, which are at least beneficial to improving the photoelectric conversion efficiency of the solar cell.

The embodiment of the application provides a solar cell, which comprises: a substrate having opposed first and second surfaces, the first surface comprising alternating first and second portions, the first portion being recessed relative to the second portion in a direction toward the second surface; the first tunneling layer covers the first part, the surface of the first tunneling layer facing the first part is provided with a first texture structure, the surface of the first tunneling layer far away from the first part is provided with a second texture structure, the flatness of the second texture structure is larger than that of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced protruding structures positioned on the polishing surface, and the occupied area of the protruding structures on the polishing surface is not larger than 1/2 of the area of the polishing surface; a first doped conductive layer covering a surface of the first tunneling layer remote from the substrate; a first electrode in electrical contact with the first doped conductive layer.

In addition, the raised structures include either a first pyramid structure or a first land raised structure.

In addition, the ratio of the occupied area of the plurality of protruding structures on the polishing surface to the area of the polishing surface is 1:11-1:2.

In addition, the protruding structure is first pyramid structure, and the second texture structure includes: and a second platform bulge structure.

In addition, the recess depth of the first portion is 1 μm to 5 μm.

In addition, a width of the first electrode in a first direction is smaller than a width of the first doped conductive layer in the first direction, the first direction is parallel to the first portion and perpendicular to an extending direction of the first electrode.

In addition, a ratio of a width of the first doped conductive layer in the first direction to a width of the first electrode in the first direction is 3 or less.

In addition, a first passivation layer covers the first doped conductive layer and a second portion of the first surface, the first electrode penetrating the first passivation layer and being in electrical contact with the first doped conductive layer.

In addition, the second portion of the first surface has a third texture comprising a second pyramid structure.

In addition, the doping element type of the first doping conductive layer is different from the doping element type of the substrate.

In addition, the material of the first doped conductive layer includes: at least one of amorphous silicon, polysilicon, and silicon carbide.

In addition, the solar cell further includes: the emitter layer is positioned in the substrate and opposite to the second part, the substrate exposes the top surface of the emitter layer, the top surface of the emitter layer is contacted with the surface of the first passivation layer, which faces the substrate, and the doping element type of the emitter layer is different from the doping element type of the substrate.

In addition, the solar cell further includes: a second tunneling layer located on the second surface; the second doped conductive layer is positioned on the surface of the second tunneling layer, which is far away from the substrate.

In addition, the doping element type of the second doping conductive layer is the same as the doping element type of the substrate.

In addition, the material of the second doped conductive layer includes: at least one of amorphous silicon, polysilicon, and silicon carbide.

Correspondingly, the embodiment of the application also provides a photovoltaic module, which comprises a battery string, wherein the battery string is formed by connecting a plurality of solar cells; the packaging layer is used for covering the surface of the battery string, and the cover plate is used for covering the surface, far away from the battery string, of the packaging layer.

Correspondingly, the embodiment of the application also provides a preparation method of the solar cell, which comprises the following steps: providing an initial substrate having an initial first surface and a second surface opposite to the first surface; etching the initial substrate from the initial first surface to convert the initial first surface into a first surface, wherein the first surface is provided with first parts and second parts which are alternately arranged, the first parts are recessed towards the second surface relative to the second parts, and the rest of the initial substrate forms a substrate; forming a first tunneling layer, wherein the first tunneling layer covers the first part, the surface of the first tunneling layer facing the first part is provided with a first texture structure, the surface of the first tunneling layer away from the first part is provided with a second texture structure, the flatness of the second texture structure is larger than that of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced protruding structures positioned on the polishing surface, and the occupied area of the protruding structures on the polishing surface is not larger than 1/2 of the area of the polishing surface; forming a first doped conductive layer, wherein the first doped conductive layer covers the surface of the first tunneling layer, which is far away from the substrate; a first electrode is formed in electrical contact with the first doped conductive layer.

In addition, the method of forming the first portion and the second portion includes: forming a mask layer on the initial first surface, wherein the mask layer is provided with a first opening, and part of the initial first surface is exposed out of the first opening; etching the initial first surface along the first opening to form an initial first groove in the initial substrate and converting the initial first surface into the first surface; polishing the side wall and the bottom wall of the initial first groove to enable the side wall and the bottom wall of the initial first groove to have polishing surfaces so as to form an initial second groove; performing a texturing process on the bottom wall and the side wall of the initial second groove to form a groove, wherein the bottom wall and the side wall of the groove are provided with the first texture structure; and removing the mask layer, wherein the first surface corresponding to the groove is the first part, and the part except the groove is the second part.

In addition, the initial second groove bottom wall and the side wall are subjected to a texturing process to form the first texture structure, and the method comprises the following steps: cleaning the bottom wall and the side wall of the initial second groove; preparing a wool making additive mother solution, wherein the wool making additive mother solution comprises sodium dodecyl benzene sulfonate and polyvinylpyrrolidone, and the mass ratio of the sodium dodecyl benzene sulfonate to the polyvinylpyrrolidone is 0.1-20; providing deionized water, and adding the wool making additive mother liquor and sodium hydroxide into the deionized water to prepare etching liquid, wherein the volume ratio of the wool making additive mother liquor to the deionized water is 0.002-0.003, and the mass ratio of the sodium hydroxide to the deionized water is 0.03-0.1; and cleaning the bottom wall and the side wall of the initial second groove by adopting the etching liquid to form the first texture structure.

In addition, the method for forming the first tunneling layer includes: forming an initial first tunneling layer on the side wall and the bottom wall of the groove by adopting a deposition process, wherein two opposite surfaces of the initial first tunneling layer are provided with the first texture structure with the same shape as the side wall and the bottom wall of the groove; and polishing the surface of the initial first tunneling layer, which is far away from the substrate, wherein the surface of the initial first tunneling layer, which is treated by the polishing process, is far away from the substrate, and the surface of the initial first tunneling layer, which is far away from the substrate, is provided with the second texture structure, so that the first tunneling layer is formed.

The technical scheme provided by the embodiment of the application has at least the following advantages:

in the technical scheme of the solar cell provided by the embodiment of the application, the first part provided with the first surface is recessed towards the second surface relative to the second part, namely, a groove is formed on the first surface of the substrate. The first tunneling layer and the first doped conductive layer covering the first portion are equivalent to the sidewalls and the bottom wall of the recess. The grooves have larger surface areas, so that the surface areas of the formed tunneling layer and the doped conductive layer can be increased, the first electrode is in electrical contact with the doped conductive layer, the tunneling layer and the doped conductive layer surround the first electrode, a good passivation effect is achieved on high recombination loss caused by contact between the first electrode and the doped conductive layer, the filling factor is improved, and further the photoelectric conversion performance of the solar cell can be improved. The first tunneling layer and the first doped conductive layer are not arranged on the second part, so that parasitic absorption of the first doped conductive layer on the second part to incident light rays can be avoided, and the absorption and utilization rate of the incident light rays is further improved.

In addition, the first tunneling layer and the first doped conductive layer which are positioned on the side wall of the groove formed by the first part are not directly irradiated by incident light, so that excessive parasitic absorption cannot be caused, high recombination loss of the first electrode is passivated, high absorption and utilization rate of the incident light can be ensured, the number of carriers is increased, and the photoelectric conversion capability of the solar cell is further improved.

In addition, the flatness of the second texture structure is larger than that of the first texture structure, that is, the flatness of the surface of the first tunneling layer far away from the first part is larger than that of the surface of the first tunneling layer towards the first part, so that the contact interface between the first doped conductive layer and the first tunneling layer is relatively flat, and the field passivation effect of the first doped conductive layer can be improved. The surface of the first tunneling layer facing the first part is a composite morphology of a polishing surface and a small number of protruding structures located on the polishing surface, the protruding structures are beneficial to increasing the contact area of the tunneling layer and the substrate, increasing the tunneling interface and facilitating the tunneling of carriers, the area of the polishing surface is large, the interface between the first tunneling layer and the first part can be ensured to be flat, and the passivation capability of the first tunneling layer is enhanced.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise.

Fig. 1 is a schematic cross-sectional structure of a solar cell according to an embodiment of the present disclosure;

fig. 2 is an electron microscope image of a first texture structure in a solar cell according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional structure of another solar cell according to an embodiment of the disclosure;

fig. 4 is a schematic diagram illustrating carrier transport in a solar cell according to another embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional structure of a photovoltaic module according to another embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional structure corresponding to a step of providing a substrate in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure corresponding to a step of forming an emitter in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional structure corresponding to a step of forming a mask layer in the method for manufacturing a solar cell provided in the present application;

Fig. 9 is a schematic cross-sectional structure corresponding to a step of forming an initial first groove in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 10 is a schematic cross-sectional structure corresponding to a step of forming an initial second groove in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional structure diagram corresponding to a step of forming a groove in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 12 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial first tunneling layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 13 is a schematic cross-sectional structure corresponding to a step of forming a first tunneling layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 14 is a schematic cross-sectional structure corresponding to a step of forming a first doped conductive layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 15 is a schematic cross-sectional structure diagram corresponding to a step of forming a second tunneling layer and a second doped conductive layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;

fig. 16 is a schematic cross-sectional structure corresponding to a step of forming a first passivation layer in another method for manufacturing a solar cell according to an embodiment of the present disclosure;

Fig. 17 is a schematic cross-sectional structure corresponding to a step of forming a second passivation layer in another method for manufacturing a solar cell according to an embodiment of the present application.

Detailed Description

As known from the background art, the current solar cell has a problem of low photoelectric conversion efficiency.

The embodiment of the application provides a solar cell, the first part of setting first surface is sunken towards the second surface direction for the second part for the surface area that covers tunneling layer and doped conducting layer in first part surface is great, and first electrode and doped conducting layer electrical contact makes tunneling layer and doped conducting layer surround first electrode, and the high recombination loss that leads to first electrode and doped conducting layer contact plays better passivation effect. The flatness of the surface of the first tunneling layer far away from the first part is larger than that of the surface of the first tunneling layer facing the first part, so that the contact interface between the first doped conductive layer and the first tunneling layer is flat, and the field passivation effect of the first doped conductive layer can be improved. The surface of the first tunneling layer facing the first part is a composite morphology of a polishing surface and a small number of protruding structures located on the polishing surface, the protruding structures are beneficial to increasing the contact area of the tunneling layer and the substrate, increasing the tunneling interface and facilitating the tunneling of carriers, the area of the polishing surface is large, the interface between the first tunneling layer and the first part can be ensured to be flat, and the passivation capability of the first tunneling layer is enhanced.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic cross-sectional structure of a solar cell according to an embodiment of the present disclosure.

Referring to fig. 1, a solar cell includes: the substrate 100 has opposite first and second surfaces, the first surface including first portions 10 and second portions 11 alternately arranged, the first portions 10 being recessed toward the second surface with respect to the second portions 11. The solar cell further includes: the first tunneling layer 110 covers the first portion 10, the surface of the first tunneling layer 110 facing the first portion 10 has a first texture structure, the surface of the first tunneling layer 110 facing away from the first portion 10 has a second texture structure, the flatness of the second texture structure is greater than that of the first texture structure, the first texture structure comprises a polishing surface 1 and a plurality of spaced protruding structures 2 located on the polishing surface 1, and the occupied area of the protruding structures 2 on the polishing surface 1 is not greater than 1/2 of the area of the polishing surface 1. The solar cell further includes: the first doped conductive layer 120 covers a surface of the first tunneling layer 110 away from the substrate 100. The solar cell further includes: the first electrode 130 is in electrical contact with the first doped conductive layer 120.

The first electrode 130 penetrates through a portion of the thickness of the first doped conductive layer 120, is in electrical contact with the first doped conductive layer 120, and photo-generated carriers generated in the substrate 100 are transferred from the substrate 100 to the first doped conductive layer 120 and then transferred to the first electrode 130, where the first electrode 130 is used for collecting the photo-generated carriers.

The first portion 10 of the first surface is recessed toward the second surface with respect to the second portion 11 to form a groove, and the first tunneling layer 110 and the first doped conductive layer 120 covering the first portion 10 correspond to the sidewalls and the bottom wall of the groove. Because the grooves have larger surface areas, the tunneling layers and the doped conductive layers which cover the side walls of the grooves have larger surface areas, the first electrode 130 is in electric contact with the doped conductive layers, the tunneling layers and the doped conductive layers surround the first electrode 130, a better passivation effect is achieved on high recombination losses caused by contact between the first electrode 130 and the doped conductive layers, the filling factor is improved, and further the photoelectric conversion performance of the solar cell can be improved. Since the first tunneling layer 110 and the first doped conductive layer 120 are not disposed on the second portion 11, the problem of parasitic absorption of the incident light by the first doped conductive layer 120 on the second portion 11 can be avoided, and the absorption and utilization rate of the substrate 100 on the incident light can be improved.

The first tunneling layer 110 and the first doped conductive layer 120 positioned on the side walls and the bottom wall of the groove formed by the first portion 10 are not directly irradiated by incident light, so that excessive parasitic absorption of the incident light is avoided, the high recombination loss of the first electrode 130 is improved by increasing the surface areas of the first tunneling layer 110 and the first doped conductive layer 120, the higher absorption and utilization rate of the substrate 100 to the incident light is ensured, the number of carriers can be increased, the filling factor is increased, the open-circuit voltage and the short-circuit current are increased, and the photoelectric conversion performance of the solar cell is improved.

The surface of the first tunneling layer 110 facing the first portion 10 has a first texture, and the surface of the first tunneling layer 110 facing away from the first portion 10 has a second texture. That is, the surface of the first tunneling layer 110 facing the first portion 10 has the shape of the first texture, and the surface of the first tunneling layer 110 facing away from the first portion 10 has the shape of the second texture. The flatness of the second texture structure is greater than that of the first texture structure, i.e., the flatness of the surface of the first tunneling layer 110 away from the first portion 10 is greater than that of the surface of the first tunneling layer 110 toward the first portion 10.

That is, the surface smoothness of the first tunneling layer 110 far from the first portion 10 is higher, and the contact interface between the first doped conductive layer 120 and the first tunneling layer 110 is smoother due to the contact between the first doped conductive layer 120 and the surface of the first tunneling layer 110 far from the first portion 10, so that the field passivation effect of the first doped conductive layer 120 can be improved. The surface of the first tunneling layer 110 facing the first portion 10 is a composite morphology of the polishing surface 1 and a small number of raised structures 2 located on the polishing surface 1, the presence of the raised structures 2 is beneficial to increasing the contact area between the tunneling layer and the substrate 100, increasing the tunneling interface, facilitating the tunneling of carriers, ensuring that the interface between the first tunneling layer 110 and the first portion 10 is relatively flat due to the larger area of the polishing surface 1, and enhancing the passivation capability of the first tunneling layer 110. In some embodiments, the material of the first tunneling layer 110 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polysilicon.

It will be appreciated that the flatness of the first texture structure refers to the difference in distance between the peaks of the relatively raised structures and the relatively flat surface on the surface of the first tunneling layer 110 facing the first portion 10, the smaller the difference, the higher the flatness; the flatness of the second texture structure means that the smaller the difference distance between the peak of the relatively convex structure and the relatively flat surface on the surface of the second tunneling layer remote from the first portion 10, the higher the flatness.

The substrate 100 is used to receive incident light and generate photo-generated carriers, and in some embodiments, the substrate 100 may be a silicon substrate, and the material of the silicon substrate may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In some embodiments, the material of the substrate 100 may also be silicon carbide, an organic material, or a multi-compound. The multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenium, and the like.

In some embodiments, both the first surface and the second surface may be configured to receive incident light or reflected light. In some embodiments, the second surface may be a light receiving surface and the first surface may be a backlight surface. In some embodiments, the first surface may be a light receiving surface and the second surface may be a backlight surface. The light receiving surface refers to a surface that directly receives incident light.

In some embodiments, the solar cell may be a TOPCON (Tunnel Oxide Passivated Contact, tunnel oxide passivation contact) cell.

In some embodiments, the substrate 100 has a doping element therein, where the doping element is of an N-type or a P-type, the N-type element may be a group v element such As a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, and the P-type element may be a group iii element such As a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or a gallium (In) element. For example, when the substrate 100 is a P-type substrate, the internal doping element type is P-type. Alternatively, when the substrate 100 is an N-type substrate, the internal doping element type is N-type.

Referring to fig. 2, fig. 2 is an electron microscope image of a first texture structure in a solar cell according to an embodiment of the present application. In some embodiments, the ratio of the occupied area of the plurality of protruding structures 2 on the polishing surface 1 to the area of the polishing surface 1 is 1:11-1:2, for example, may be 1:4-1:3, 1:5-1:4, 1:6-1:5, 1:7-1:6, 1:8-1:7, 1:9-1:8, 1:10-1:9, or 1:11-1:10.

In the above range, the total area occupied by the plurality of raised structures 2 on the polishing surface 1 is smaller, so that the roughness of the first texture structure is not too large, and further, the flatness of the surface of the first tunneling layer 110 facing the first portion 10 is not too small, and the problem that the chemical passivation capability of the first tunneling layer 110 to the first portion 10 is weakened due to uneven contact interface between the first tunneling layer 110 and the first portion 10 is avoided. On the other hand, in the above range, the total area occupied by the plurality of raised structures 2 on the polishing surface 1 is not too small, so that the specific surface area of the surface of the first tunneling layer 110 facing the first portion 10 can be properly increased, the contact area between the first tunneling layer 110 and the first portion 10 is increased, the tunneling interface of carriers is increased, and the collection capability of the first electrode 130 on the carriers is enhanced.

The polishing surface 1 in the embodiment of the present application refers to a flat surface.

Referring to fig. 1 and 3, in some embodiments, the raised structures 2 comprise either a first pyramid structure or a first platform raised structure.

Referring to fig. 1 and fig. 2, in some embodiments, the bump structure 2 includes a first pyramid structure, where the first pyramid structure has a larger specific surface area, and the bump structure 2 is configured as the first pyramid structure, which can increase the specific surface area of the first tunneling layer 110 towards the surface of the first portion 10, and further can increase the contact area between the first tunneling layer 110 and the first portion 10, and increase the tunneling channel of the carrier.

In some embodiments, the first pyramid structure may be a tetrahedral, approximately tetrahedral, pentahedral, or approximately pentahedral structure, or the like.

Referring to fig. 3, in some embodiments, the raised structures 2 are first land raised structures that are the base portions of the pyramid structures, i.e., the bottom structures that remain after the pyramid structures have had the tip portions removed. In this way, the top of the bump structure 2 is relatively flat, which not only can increase the contact area between the first tunneling layer 110 and the first portion 10, but also can ensure that the contact interface between the first tunneling layer 110 and the first portion 10 is relatively flat.

In some embodiments, the protruding structures 2 may also be platform-like protruding structures, the top surfaces of which may be flat or inclined surfaces, and the bottom surfaces of which may be polygonal flat surfaces, for example, quadrangular flat surfaces or pentagonal flat surfaces.

In some embodiments, the raised structures 2 may be located only on the bottom wall of the groove formed by the first portion 10, and the side wall of the groove formed by the first portion 10 may be the polishing surface 1. In some embodiments, the raised structures 2 may also be located on the bottom wall and side walls of the recess formed by the first portion 10.

In some embodiments, the raised structures 2 are first pyramid structures, and the second texture structures comprise: and a second platform bulge structure. The second platform protruding structure can be the tower footing structure that the first pyramid structure removed the tower tip part and then remained, that is to say, compare in first pyramid structure, the phase difference distance of the top surface of second platform protruding structure is less than the bottom surface for the planarization of second texture structure is higher, and the bottom surface one-dimensional size of second platform protruding structure is greater than the bottom surface one-dimensional size of protruding structure 2, makes the protruding degree of second platform protruding structure be unlikely to too high, is favorable to the second texture structure to form higher planarization.

It is understood that the area of the second texture structure other than the second land relief structure may be a polished surface, and the total area of the bottom surfaces of all the second land relief structures is not greater than the total area of the polished surface, further increasing the flatness of the second texture structure.

In some embodiments, the second texture may also be entirely polished, i.e., entirely flat, surfaces.

Referring to FIG. 1, in some embodiments, the recess depth d of the first portion 10 is 1 μm to 5 μm, which may be, for example, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, or 4.5 μm to 5 μm. The recess depth d of the first portion 10 refers to the recess depth of the first portion 10 toward the second surface as compared to the second portion 11. In the above range, the recess depth of the first portion 10 is made larger, so that the first portion 10 has a larger surface area, and the first tunneling layer 110 and the first doped conductive layer 120 formed on the first portion 10 have a larger area, so that the effect of passivating the high recombination loss of the first electrode 130 can be improved to a certain extent. It is also possible to increase the tunneling interface between the first tunneling layer 110 and the substrate 100. In addition, in the above range, the deep portion of the recess of the first portion 10 is not too large, so that on one hand, the substrate 100 is prevented from being damaged greatly, and excessive defects in the substrate 100 are avoided. On the other hand, it is possible to prevent the problem that the thickness of the first doped conductive layer 120 formed on the first portion 10 is excessively large due to the excessively large recess depth of the first portion 10, so that parasitic absorption of incident light by the first doped conductive layer 120 is excessively large.

The first part 10 is recessed towards the second surface relative to the second part 11 to form a recess having an opening remote from the second surface. In some embodiments, the groove bottom wall may be planar, with the groove side walls being perpendicular relative to the groove bottom wall. In some embodiments, the bottom of the recess may also have an arc, i.e. the first portion 10 may be an elliptic paraboloid.

In some embodiments, the width of the first electrode 130 in the first direction X is smaller than the width of the first doped conductive layer 120 in the first direction X, the first direction X being parallel to the first portion 10 and perpendicular to the extension direction of the first electrode 130. In this way, the first electrode 130 is wrapped by the first doped conductive layer 120, so as to increase the contact area between the first electrode 130 and the first doped conductive layer 120, further reduce the contact resistance between the first electrode 130 and the first doped conductive layer 120, and increase the transmission rate of carriers to the first electrode 130.

In some embodiments, the material of the first electrode 130 may be a metallic material, for example, any of silver, nickel, aluminum, or copper.

In some embodiments, the ratio of the width of the first doped conductive layer 120 in the first direction X to the width of the first electrode 130 in the first direction X is less than or equal to 3, for example, may be 1.1, 1.3, 1.5, 1.7, 2, 2.2, 2.5, 2.8, or 3. Within the above range, the ratio of the width of the first doped conductive layer 120 to the width of the first electrode 130 is made large in the first direction X, so that the first electrode 130 can be ensured to be covered by the first doped conductive layer 120. In addition, the width of the first doped conductive layer 120 is set to be larger, so that the problem that when the material forming the first electrode 130 is burnt into the first doped conductive layer 120 due to process deviation, the material diffuses in the first direction X in the first doped conductive layer 120, and the actual width of the formed first electrode 130 is larger than that of the first doped conductive layer 120, and a process window for forming the first electrode 130 is increased.

In addition, in the above-mentioned range, so that the width of the first doped conductive layer 120 is not excessively large compared to the first electrode 130 in the first direction X, it is possible to prevent the first doped conductive layer 120 from receiving too much incident light due to the excessively large width of the first doped conductive layer 120, thereby causing a problem that parasitic absorption of the first doped conductive layer 120 is large.

In some embodiments, the doping element type of the first doped conductive layer 120 is different from the doping element type of the substrate 100. That is, the first doped conductive layer 120 forms a PN junction with the substrate 100. In some embodiments, the doping element type of the substrate 100 is P-type, and the doping element type of the first doped conductive layer 120 is N-type, and the N-type doping element may be a v-group element such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element. In some embodiments, the doping element type of the substrate 100 is N-type, and the doping element type of the first doped conductive layer 120 is P-type, and the P-type doping element may be a group iii element such as boron (B) element, aluminum (Al) element, gallium (Ga) element, or gallium (In) element.

In some embodiments, the material of the first doped conductive layer 120 includes: at least one of amorphous silicon, polysilicon, and silicon carbide.

Referring to fig. 1, in some embodiments, further comprising a first passivation layer 150, the first passivation layer 150 covering the first doped conductive layer 120 and the second portion 11 of the first surface, the first electrode 130 penetrating the first passivation layer 150 to be in electrical contact with the first doped conductive layer 120. The first passivation layer 150 may directly contact the second portion 11, and the first passivation layer 150 may have a better passivation effect on the first surface, for example, may perform better chemical passivation on dangling bonds of the first surface, reduce the defect state density of the first surface, and inhibit carrier recombination on the first surface.

In some embodiments, the first passivation layer 150 is a single layer structure, and then the material of the first passivation layer 150 may be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first passivation layer 150 is a multi-layer structure, and the material of the first passivation layer 150 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

Referring to fig. 4, in some embodiments, the solar cell further comprises: and an emitter layer 140, the emitter layer 140 being located in the substrate 100 opposite to the second portion 11, and the substrate 100 exposing an emitter layer top surface, the emitter layer 140 top surface being in contact with a surface of the first passivation layer 150 facing the substrate 100, the emitter layer 140 having a doping element type different from that of the substrate 100. The emitter layer 140 forms a PN junction with the substrate 100 in cooperation with a doping element of the substrate 100. In some embodiments, the doping element type of the substrate 100 is P-type, the doping element type of the emitter is N-type, and the N-type doping element may be a v-group element such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element. In some embodiments, the doping element type of the substrate 100 is N-type, the doping element type of the emitter is P-type, and the P-type doping element may be a group iii element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

In some embodiments, the material of the emitter layer 140 may be the same as the material of the substrate 100. For example, it may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon, or may also be silicon carbide, an organic material, or a multi-component compound. The multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenium, and the like.

In some embodiments, the doping element type of the first doped conductive layer 120 is different from the doping element type of the substrate 100 to form a PN junction, and the emitter and the substrate 100 also form the PN junction, so that the area of the PN junction is larger, and more incident light can be converted into photo-generated carriers.

In some embodiments, the second portion 11 of the first surface has a third texture comprising a second pyramid structure. The second pyramid structure may be a tetrahedron, a near tetrahedron, a pentahedron, or a near pentahedron, among others.

In some embodiments, the number of second pyramid structures is a plurality, and the plurality of second pyramid structures are spaced apart. The second pyramid structure gives the second portion 11 of the first surface a textured structure. The second pyramid structure is a tetrahedron structure or a pentahedron structure, which makes the second pyramid structure have a better reflection capability for incident light. When the light irradiates the second surface, the incident light reflected by the second pyramid structures is reflected between two adjacent second pyramid structures for multiple times, and finally, most of the reflected light is absorbed and utilized by the substrate 100 again, so that the utilization rate of the substrate 100 on the incident light is enhanced.

Referring to fig. 1, 3, and 4, in some embodiments, the solar cell further comprises: a second tunneling layer 160 disposed on the second surface; the second doped conductive layer 170 is located on a surface of the second tunneling layer 160 away from the substrate 100. The second tunneling layer 160 has a chemical passivation effect on the second surface, reduces the defect state density of the second surface, and inhibits carrier recombination of the second surface.

In some embodiments, the material of the second tunneling layer 160 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polysilicon.

In some embodiments, the doping element type of the second doped conductive layer 170 is the same as the doping element type of the substrate 100. In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are P-type, and the P-type doping element may be a group iii element such as boron (B) element, aluminum (Al) element, gallium (Ga) element, or gallium (In) element. In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are both N-type, and the N-type doping element type may be a v-group element such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element.

In some embodiments, the concentration of the doping element of the second doped conductive layer 170 is greater than that of the substrate 100, so that a high-low junction can be formed between the second doped conductive layer 170 and the substrate 100, and a concentration gradient of the same kind of element is formed, which generates a barrier effect on carriers, and realizes selective transmission of carriers.

In some embodiments, the material of the second doped conductive layer 170 includes: at least one of amorphous silicon, polysilicon, and silicon carbide.

In some embodiments, further comprising: the second passivation layer 180, the second passivation layer 180 is located on the surface of the second doped conductive layer 170 away from the substrate 100. The second passivation layer 180 is used for performing a good passivation effect on the second surface of the substrate 100, reducing the defect state density of the second surface, and better inhibiting carrier recombination on the back surface of the substrate 100. The second passivation layer 180 may also have a better anti-reflection effect, which is beneficial to reducing reflection of incident light and improving utilization rate of the incident light.

In some embodiments, the second passivation layer 180 is a single layer structure, and then the material of the second passivation layer 180 may be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the second passivation layer 180 is a multi-layered structure, and the material of the second passivation layer 180 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

In some embodiments, further comprising: the second electrode 190 is disposed on the second surface of the substrate 100, and the second electrode 190 penetrates the second passivation layer 180 to electrically contact the second doped conductive layer 170.

In some embodiments, the material of the second electrode 190 may be a metal, such as copper, silver, nickel, or aluminum.

In the solar cell provided in the above embodiment, the first portion 10 is recessed toward the second surface direction relative to the second portion 11, so that the surface areas of the tunneling layer and the doped conductive layer covered on the surface of the first portion 10 are larger, the tunneling layer and the doped conductive layer can surround the first electrode 130, and a better passivation effect is achieved on high recombination loss caused by the contact between the first electrode 130 and the doped conductive layer. The flatness of the surface of the first tunneling layer 110 away from the first portion 10 is greater than the flatness of the surface of the first tunneling layer 110 facing the first portion 10, so that the contact interface between the first doped conductive layer 120 and the first tunneling layer 110 is relatively flat, and the field passivation effect of the first doped conductive layer 120 can be improved. The surface of the first tunneling layer 110 facing the first portion 10 is a composite morphology of the polishing surface 1 and a small number of raised structures 2 located on the polishing surface 1, the presence of the raised structures 2 is beneficial to increasing the contact area between the tunneling layer and the substrate 100, increasing the tunneling interface, facilitating the tunneling of carriers, ensuring that the interface between the first tunneling layer 110 and the first portion 10 is relatively flat, and enhancing the passivation capability of the first tunneling layer 110.

Accordingly, another aspect of the embodiments of the present application further provides a photovoltaic module, referring to fig. 5, the photovoltaic module includes: a cell string formed by connecting a plurality of solar cells 101 provided in the above embodiments; the packaging layer 102, the packaging layer 102 is used for covering the surface of the battery string; and a cover plate 103, wherein the cover plate 103 is used for covering the surface of the encapsulation layer 102 away from the battery strings. The solar cells 101 are electrically connected in whole or multiple pieces to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and/or parallel.

In some embodiments, the plurality of battery strings may be electrically connected by a conductive strap 104. The encapsulant layer 102 covers the surface and the back of the substrate 100 of the solar cell 101, and the encapsulant layer 102 may be an organic encapsulant film such as an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene co-elastomer (POE) film, a polyethylene terephthalate (PET) film, or a polyvinyl butyral (PVB). In some embodiments, the cover 103 may be a cover 103 having a light transmitting function, such as a glass cover, a plastic cover, or the like. The surface of the cover plate 103 facing the encapsulation layer 102 may be a concave-convex surface, thereby increasing the utilization of incident light.

Correspondingly, the embodiment of the application also provides a preparation method of the solar cell, which comprises the following steps:

referring to fig. 6, an initial substrate 20 is provided having opposing initial first and second surfaces 3, 4.

The initial substrate 20 is used for receiving incident light and generating photo-generated carriers. In some embodiments, the initial substrate 20 may be a silicon substrate, and the material of the initial substrate 20 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

In some embodiments, the initial substrate 20 may be an N-type semiconductor substrate, and the doping element of the substrate 100 may be any one of phosphorus element, arsenic element, or antimony element.

In some embodiments, the initial substrate 20 may also be a P-type semiconductor substrate, and the doping element of the initial substrate 20 may be any one of boron, gallium or indium.

In some embodiments, the initial substrate 20 may be subjected to a doping process, such as an ion implantation process, to diffuse the doping element into the initial substrate 20.

In some embodiments, the initial first surface 3 may be subjected to a texturing process to form a textured structure on the initial first surface 3. In some embodiments, the initial first surface 3 may comprise a pyramidal structure. Forming a textured structure on the first surface of the substrate 100 may enhance the parasitic absorption of the incident light by the first surface.

In some embodiments, the solar cell formed is a TOPCON cell.

Referring to fig. 7, in some embodiments, a method of fabricating a solar cell includes: an emitter layer 140 is formed in the substrate 100, the substrate 100 exposes a top surface of the emitter layer 140, and the top surface of the emitter layer 140 coincides with the initial first surface 3. The doping element type of the emitter layer 140 is opposite to that of the substrate 100, and forms a PN junction with the substrate 100.

In some embodiments, a method of forming the emitter layer 140 may include: a diffusion process is performed on the initial first surface 3 of the initial substrate 20 to diffuse the doping element into a portion of the initial substrate 20, forming an emitter layer 140. In some embodiments, the diffusion process may be an ion implantation process.

In some embodiments, the initial first surface 3 may be subjected to a boron diffusion treatment when the initial substrate 20 is an N-type substrate, and the initial first surface 3 may be subjected to a phosphorus diffusion treatment when the initial substrate 20 is a P-type substrate.

Referring to fig. 8 to 11, the initial substrate 20 is etched from the initial first surface 3 to convert the initial first surface 3 into a first surface having first portions 10 and second portions 11 alternately arranged, the first portions 10 being recessed toward the second surface 4 with respect to the second portions 11, and the remaining initial substrate 20 forming the substrate 100.

That is, the initial first surface 3 is etched to remove a portion of the initial substrate 20, and the remaining portion of the initial substrate 20 forms the substrate 100, and the etched initial first surface 3 forms the first surface.

In some embodiments, the method of forming the first portion 10 and the second portion 11 includes:

referring to fig. 8, a mask layer 30 is formed on the initial first surface 3, and the mask layer 30 has a first opening 31, and the first opening 31 exposes a portion of the initial first surface 3. The mask layer 30 may protect the initial first surface 3 that does not need to be etched.

In some embodiments, a method of forming mask layer 30 may include: the initial masking layer 30 is formed on the initial first surface 3 using a deposition process, which may be any of atomic layer deposition or chemical vapor deposition. In some embodiments, the material of the initial mask layer 30 may be silicon oxide.

In some embodiments, the initial mask layer 30 may be etched using a photolithography process to form the first opening 31 in the initial mask layer 30.

Referring to fig. 9, after forming the first opening 31, the initial first surface 3 is etched along the first opening 31 to form initial first grooves 21 in the initial substrate 20 and convert the initial first surface 3 into a first surface. In some embodiments, the initial first grooves 21 may be formed in the initial substrate 20 using a mechanical etching, chemical etching, or laser etching method.

In some embodiments, the initial first recess 21 may be formed in the initial substrate 20 using a chemical etching method, which may include: the initial first surface 3 exposed by the first opening 31 is cleaned with an etching liquid, and the initial substrate 20 is etched from the initial first surface 3. In some embodiments, the etching solution may include a hydrofluoric acid solution, and the etching time is controlled within 0.5min to 5 min. In some embodiments, the hydrofluoric acid solution may be 2% -5% by mass.

In some embodiments, the emitter layer 140 is also formed in the initial substrate 20 before the initial first recess 21 is formed. The emitter layer 140 facing the first opening 31 is also removed and the emitter layer 140 facing the mask layer 30 is left in the step of forming the initial first recess 21.

Referring to fig. 10, the initial first recess 21 side walls and bottom wall are subjected to a polishing process so that the initial first recess 21 side walls and bottom wall have polished surfaces, forming an initial second recess 22. It will be appreciated that the bottom wall and the side walls of the initial first recess 21, which are formed by etching the initial first surface 3 along the first opening 31, will have an uneven topography. In order to form the composite morphology of the polishing surface 1 and the bump structure 2 on the bottom wall and the side wall of the initial first groove 21 later, a polishing process is required to be performed on the side wall and the bottom wall of the initial first groove 21 to form a polished surface preliminarily, and the polished surface is a flat surface.

In some embodiments, the method of the polishing process is an alkaline polishing process. In some embodiments, the alkali polishing process may include: washing the side wall and the bottom wall of the initial first groove 21 by adopting alkali solution; the micro-droplets of the alkali solution are dripped to the side wall and the bottom wall of the initial first groove 21 in a spraying mode to carry out roughening treatment, and then the pre-cleaning is carried out by hydrofluoric acid; the side walls and the bottom wall of the initial first recess 21 are polished with a polishing liquid. In some embodiments, the concentration of the polishing solution is 0.5-5%, the polishing temperature is 50-80 ℃, and the polishing time is 20-1000 s. By controlling the polishing time and the polishing temperature within the above ranges, the topography of the side walls and bottom walls of the initial second groove 22 can be made to conform to the expectations. In some embodiments, the polishing solution may be a NaOH solution, and in some embodiments, the polishing solution may also be a KOH solution. Finally, the polished side walls and bottom wall of the initial second groove 22 are subjected to water washing and drying treatment.

Referring to fig. 11, after forming the initial second groove 22, a texturing process is performed on the bottom wall and the side wall of the initial second groove 22 to form a groove 23, the bottom wall and the side wall of the groove 23 have a first texture structure including a polishing surface 1 and a plurality of spaced protruding structures 2 located on the polishing surface 1, and the occupied area of the plurality of protruding structures 2 on the polishing surface 1 is not more than 1/2 of the area of the polishing surface 1.

In some embodiments, the bottom wall and the side walls of the initial second recess 22 are subjected to a texturing process to form a first texture, the method comprising:

first, a cleaning process is performed on the bottom wall and the side walls of the initial second recess 22. In some embodiments, the entire substrate 100 may be immersed in deionized water and treated with an ultrasonic process for 2 to 5 minutes to remove dirt from the surface of the substrate 100.

Next, a texturing additive mother liquor is prepared, and the texturing additive mother liquor includes sodium dodecyl benzene sulfonate and polyvinylpyrrolidone, and the mass ratio of the sodium dodecyl benzene sulfonate to the polyvinylpyrrolidone is 0.1 to 20, for example, may be 0.1 to 0.5, 0.5 to 1, 1 to 3, 3 to 5, 5 to 8, 8 to 10, 10 to 12, 12 to 15, 15 to 17, 17 to 18, 18 to 19 or 19 to 20. In some embodiments, based on the mass ratio of sodium dodecyl benzene sulfonate to polyvinylpyrrolidone, 0.2 g-2 g of sodium dodecyl benzene sulfonate and 0.1 g-2 g of polyvinylpyrrolidone can be selectively added into 1000ml of deionized water to prepare the wool making additive mother solution.

Then, deionized water is provided, and the etching solution is prepared by adding the wool making additive mother liquor and sodium hydroxide into the deionized water, wherein the volume ratio of the wool making additive mother liquor to the deionized water is 0.002-0.003, such as 0.002-0.0021, 0.0021-0.0023, 0.0023-0.0024, 0.0024-0.0025, 0.0025-0.0026, 0.0026-0.0027, 0.0027-0.0028, 0.0028-0.0029 or 0.0029-0.003; the mass ratio of the sodium hydroxide to the deionized water is 0.03-0.1, and can be, for example, 0.03-0.04, 0.04-0.05, 0.05-0.06, 0.06-0.07, 0.07-0.08, 0.08-0.09 or 0.09-0.1. In some embodiments, 1L to 1.5L of the texturing additive mother liquor may be selected to be added to 500L of deionized water based on the volume ratio of the texturing additive mother liquor to deionized water. In some embodiments, 35kg of sodium hydroxide may be optionally added to 500L of deionized water based on the mass ratio of sodium hydroxide to deionized water.

The bottom wall and the side wall of the initial second groove 22 are cleaned by the etching liquid to form a first texture structure, and the first texture structure obtained by etching by the etching liquid with the proportion has a polishing surface 1 and a first pyramid structure positioned on the polishing surface 1.

In some embodiments, the polished surface of the initial second grooves 22 can be etched into the first texture by using the etching solution of the above-described proportioning arrangement. In some embodiments, the bottom wall and the side walls of the initial second recess 22 may be cleaned with an etching solution at 75-90 ℃ for 2-50 min to ensure the composite expectation of the formed first texture.

In some embodiments, if the bump structure 2 is a first land bump structure, after the step of cleaning the bottom wall and the side wall of the initial second groove 22 with the etching solution to form a first pyramid structure, a polishing process may be used to remove the tip of the first pyramid structure, and the remaining base portion of the first pyramid structure forms the first land bump structure. In some embodiments, a method of removing a toe of a first pyramid structure using a polishing process may include: polishing is carried out on the bottom wall and the side wall of the groove 23 by using polishing liquid. In some embodiments, the concentration of the polishing solution is 0.5-3%, the polishing temperature is 50-80 ℃, and the polishing time is 10-500 s. By controlling the polishing time and the polishing temperature within the above ranges, the tips of the first pyramid structure can be removed. In some embodiments, the polishing solution may be a NaOH solution, and in some embodiments, the polishing solution may also be a KOH solution.

Referring to fig. 12 to 13, in some embodiments, after forming the groove 23, the first tunneling layer 110 is formed, the first tunneling layer 110 covers the first portion 10, a surface of the first tunneling layer 110 facing the first portion 10 has a first texture, a surface of the first tunneling layer 110 facing away from the first portion 10 has a second texture, and the flatness of the second texture is greater than that of the first texture.

In some embodiments, a method of forming the first tunneling layer 110 includes:

referring to fig. 12, an initial first tunneling layer 32 is formed on the sidewall and bottom wall of the recess 23 by using a deposition process, and two opposite surfaces of the initial first tunneling layer 32 have a first texture structure with the same morphology as the sidewall and bottom wall of the recess 23.

In some embodiments, mask layer 30 may not be removed prior to forming initial first tunneling layer 32, enabling prevention of forming initial first tunneling layer 32 on second portion 11.

In some embodiments, the initial first tunneling layer 32 is formed on the surface of the mask layer 30, and in a subsequent step, the initial first tunneling layer 32 on the surface of the mask layer 30 may be removed, and the initial first tunneling layer 32 is formed only in the recess 23. In some embodiments, the initial first tunneling layer 32 may be formed using a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process. Since the deposition process is used to form the initial first tunneling layer 32, the surface of the initial first tunneling layer 32 facing the first portion 10 and the surface facing away from the first portion 10 have the same topography as the first texture.

In some embodiments, the material of the initial first tunneling layer 32 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polysilicon.

Referring to fig. 13, a polishing process is performed on a surface of the initial first tunneling layer 32 away from the substrate 100, and the surface of the initial first tunneling layer 32 away from the substrate 100 processed by the polishing process has a second texture structure, so as to form a first tunneling layer 110. Since the polishing process is not performed on the surface of the initial first tunneling layer 32 facing the substrate 100, the surface of the first tunneling layer 110 facing the substrate 100 has the same first texture as the bottom wall and the sidewalls of the groove 23.

In some embodiments, the second texture formed may be a second mesa relief structure, and the region of the second texture other than the second mesa relief structure may be a polished surface. In some embodiments, the method for forming the second bump structure 2 may refer to the above-mentioned process method for forming the first bump structure, and will not be described in detail below.

In some embodiments, the second texture formed may also be entirely polished, i.e., entirely flat, surfaces. In some embodiments, the method of forming the second texture structure as a polished surface may refer to the above-mentioned process of forming the initial second grooves 22 by using a polishing process, and will not be described in detail.

Referring to fig. 14, after the first tunneling layer 110 is formed, a first doped conductive layer 120 is formed, and the first doped conductive layer 120 covers a surface of the first tunneling layer 110 away from the substrate 100.

In some embodiments, the first tunneling layer 110 on the surface of the mask layer 30 is not removed before the step of forming the first doped conductive layer 120, so that the formed first doped conductive layer 120 is not located on the second portion 11.

In some embodiments, a method of forming the first doped conductive layer 120 may include: a first dopable layer is formed on the surface of the first tunneling layer 110 and the surface of the first tunneling layer 110 on the mask layer 30 by using a deposition process, and during the deposition process, a doping element is implanted into the first dopable layer by using an in-situ deposition process, so as to form the original first doped conductive layer 120. The deposition process and the doping element injection process are performed simultaneously, so that the process time can be saved, and the process efficiency can be improved.

After the first dopable layer is implanted with the doping element, an annealing process is performed on the original first doped conductive layer 120 to form the first doped conductive layer 120. The doping element in the original first doped conductive layer 120 may be activated by an annealing process to form an activated doping element.

In some embodiments, during the implantation of the doping element into the first dopable layer, the concentration of the implanted doping element is controlled to be 1×10 ²⁰ atom/cm ³ ～1×10 ²¹ atom/cm ³ 。

In some embodiments, the first dopable layer is implanted with a doping element type different from that of the substrate 100 to form a PN junction with the substrate 100. In some embodiments, the doping element type of the substrate 100 is P-type, the doping element type of the emitter is N-type, and the N-type doping element may be a v-group element such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element. In some embodiments, the doping element type of the substrate 100 is N-type, the doping element type of the emitter is P-type, and the P-type doping element may be a group iii element such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

In some embodiments, the material of the first dopable layer may be any of amorphous silicon, polysilicon, microcrystalline silicon, or silicon carbide.

It is not difficult to find that the first doping layer is formed on the surface of the first tunneling layer 110 far away from the substrate 100, and since the surface of the first tunneling layer 110 far away from the substrate 100 has the second texture structure, the flatness of the second texture structure is higher, so that the first doping layer is formed on a flatter surface, the uniformity of the formed first doping layer can be improved, and the passivation capability of the formed first doping conductive layer 120 is improved.

It is noted that the first doped conductive layer 120 is also formed on the surface of the first tunneling layer 110 on the mask layer 30. In some embodiments, after forming the first doped conductive layer 120, the first doped conductive layer 120 on the mask layer 30, the first tunneling layer 110 on the mask layer 30, and the mask layer 30 are removed, so that the formed first tunneling layer 110 and the first doped conductive layer 120 are carried into the recess 23. In some embodiments, an acid washing process may be used to remove the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30, for example, a hydrofluoric acid solution or a hydrochloric acid solution may be used to wash the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30, to remove the first doped conductive layer 120 located on the mask layer 30, the first tunneling layer 110 located on the mask layer 30, and the mask layer 30.

Referring to fig. 15, in some embodiments, the method of fabricating a solar cell further includes: the second tunneling layer 160 is formed on the second surface 4 of the substrate 100, and in some embodiments, the second tunneling layer 160 may be formed on the second surface 4 using a deposition process, which may be any one of an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the second tunneling layer 160 may be at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polysilicon.

In some embodiments, after forming the second tunneling layer 160, a second doped conductive layer 170 is formed on a surface of the second tunneling layer 160 remote from the substrate 100,

the method of forming the second doped conductive layer 170 may include: a second dopable layer is formed on the surface of the second tunneling layer 160 using a deposition process, and a doping element is implanted into the second dopable layer during the deposition process using an in situ deposition process, forming an original second doped conductive layer 170.

After the second dopable layer is implanted with the doping element, an annealing process is performed on the original second doped conductive layer 170 to form the second doped conductive layer 170.

In some embodiments, the second dopable layer is implanted with the same doping element type as the substrate 100. In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are P-type, and the P-type doping element may be a group iii element such as boron (B) element, aluminum (Al) element, gallium (Ga) element, or gallium (In) element. In some embodiments, the doping element type of the second doped conductive layer 170 and the doping element type of the substrate 100 are both N-type, and the N-type doping element type may be a v-group element such As phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element.

In some embodiments, the material of the second dopable layer may be any of amorphous silicon, polysilicon, microcrystalline silicon, or silicon carbide.

Referring to fig. 16, in some embodiments, the method of fabricating a solar cell further includes: a first passivation layer 150 is formed, the first passivation layer 150 covering the first doped conductive layer 120 and the second portion 11 of the first surface. In some embodiments, an emitter layer 140 is also formed in the substrate 100, the emitter layer 140 top surface is coincident with the second portion 11, and then the first passivation layer 150 is located on the emitter layer 140 top surface and the first doped conductive layer 120 top surface.

In some embodiments, the emitter layer 140 may not be formed in the substrate 100, and the first passivation layer 150 is in direct contact with the second portion 11.

In some embodiments, the first passivation layer 150 may be a single layer structure. In some embodiments, the first passivation layer 150 may also be a multi-layer structure.

In some embodiments, a method of forming the first passivation layer 150 may include: a first passivation layer 150 is formed on the surface of the doped conductive layer using a PECVD (Plasma Enhanced Chemical Vapor Deposition ) method.

Referring to fig. 17, in some embodiments, further comprising: a second passivation layer 180 is formed on the surface of the second doped conductive layer 170, and the second passivation layer 180 can have a better passivation effect. In some embodiments, the second passivation layer 180 may have a single layer structure. In some implementations, the second passivation layer 180 may also be a multi-layer structure.

In some embodiments, the second passivation layer 180 may be formed on the emitter surface using a PECVD process.

Referring to fig. 3, the method of manufacturing a solar cell further includes: the first electrode 130 is formed, and the first electrode 130 is in electrical contact with the first doped conductive layer 120. In some embodiments, the first electrode 130 penetrates the first passivation layer 150 to electrically contact the first doped conductive layer 120.

In some embodiments, the method of forming the first electrode 130 includes: a conductive paste, which may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel, may be printed on a surface of the first passivation layer 150 opposite the first doped conductive layer 120, for example, using a screen printing process. The sintering process is performed on the conductive paste on the surface of the first passivation layer 150, so that the conductive paste penetrates through the first passivation layer 150 and part of the doped conductive layer to form electrical contact with the doped conductive layer.

In some embodiments, further comprising: a second electrode 190 is formed, and the second electrode 190 penetrates the second passivation layer 180 to be in electrical contact with the second doped conductive layer 170. In some embodiments, the process of forming the second electrode 190 may be the same as the process of forming the first electrode 130, and reference may be made to the above description of the method of forming the first electrode 130.

While the preferred embodiment has been described, it is not intended to limit the scope of the claims, and any person skilled in the art can make several possible variations and modifications without departing from the spirit of the invention, so the scope of the invention shall be defined by the claims.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the present application and that various changes in form and details may be made therein without departing from the spirit and scope of the present application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.

Claims

1. A solar cell, comprising:

a substrate having opposed first and second surfaces, the first surface comprising alternating first and second portions, the first portion being recessed relative to the second portion in a direction toward the second surface;

the first tunneling layer covers the first part, the surface of the first tunneling layer facing the first part is provided with a first texture structure, the surface of the first tunneling layer far away from the first part is provided with a second texture structure, the flatness of the second texture structure is larger than that of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced protruding structures positioned on the polishing surface, and the occupied area of the protruding structures on the polishing surface is not larger than 1/2 of the area of the polishing surface;

A first doped conductive layer covering a surface of the first tunneling layer remote from the substrate;

a first electrode in electrical contact with the first doped conductive layer.

2. The solar cell of claim 1, wherein the raised structures comprise either a first pyramid structure or a first mesa raised structure.

3. The solar cell according to claim 1 or 2, wherein a ratio of a occupied area of the plurality of protruding structures on the polished surface to an area of the polished surface is 1:11 to 1:2.

4. The solar cell of claim 1, wherein the raised structures are first pyramid structures and the second texture structures comprise: and a second platform bulge structure.

5. The solar cell according to claim 1, wherein the first portion has a recess depth of 1 μm to 5 μm.

6. The solar cell of claim 1 or 5, wherein a width of the first electrode in a first direction is smaller than a width of the first doped conductive layer in the first direction, the first direction being parallel to the first portion and perpendicular to an extension direction of the first electrode.

7. The solar cell according to any one of claims 6, wherein a ratio of a width of the first doped conductive layer in the first direction to a width of the first electrode in the first direction is 3 or less.

8. The solar cell of claim 1, further comprising a first passivation layer covering the first doped conductive layer and a second portion of the first surface, the first electrode penetrating the first passivation layer and being in electrical contact with the first doped conductive layer.

9. The solar cell of claim 8, wherein the second portion of the first surface has a third texture, the third texture comprising a second pyramid structure.

10. The solar cell of claim 8, wherein a doping element type of the first doped conductive layer is different from a doping element type of the substrate.

11. The solar cell of claim 10, wherein the material of the first doped conductive layer comprises: at least one of amorphous silicon, polysilicon, and silicon carbide.

12. The solar cell according to claim 8 or 10, further comprising: the emitter layer is positioned in the substrate and opposite to the second part, the substrate exposes the top surface of the emitter layer, the top surface of the emitter layer is contacted with the surface of the first passivation layer, which faces the substrate, and the doping element type of the emitter layer is different from the doping element type of the substrate.

13. The solar cell according to claim 1 or 10, characterized in that the solar cell further comprises:

a second tunneling layer located on the second surface;

the second doped conductive layer is positioned on the surface of the second tunneling layer, which is far away from the substrate.

14. The solar cell of claim 13, wherein the doping element type of the second doped conductive layer is the same as the doping element type of the substrate.

15. The solar cell of claim 14, wherein the material of the second doped conductive layer comprises: at least one of amorphous silicon, polysilicon, and silicon carbide.

16. A photovoltaic module, comprising:

a battery string formed by connecting a plurality of solar cells according to any one of claims 1 to 15;

an encapsulation layer for covering the surface of the battery string;

and the cover plate is used for covering the surface, far away from the battery strings, of the packaging layer.

17. A method of manufacturing a solar cell, comprising:

providing an initial substrate having an initial first surface and a second surface opposite to the first surface;

etching the initial substrate from the initial first surface to convert the initial first surface into a first surface, wherein the first surface is provided with first parts and second parts which are alternately arranged, the first parts are recessed towards the second surface relative to the second parts, and the rest of the initial substrate forms a substrate;

Forming a first tunneling layer, wherein the first tunneling layer covers the first part, the surface of the first tunneling layer facing the first part is provided with a first texture structure, the surface of the first tunneling layer away from the first part is provided with a second texture structure, the flatness of the second texture structure is larger than that of the first texture structure, the first texture structure comprises a polishing surface and a plurality of spaced protruding structures positioned on the polishing surface, and the occupied area of the protruding structures on the polishing surface is not larger than 1/2 of the area of the polishing surface;

forming a first doped conductive layer, wherein the first doped conductive layer covers the surface of the first tunneling layer, which is far away from the substrate;

a first electrode is formed in electrical contact with the first doped conductive layer.

18. The method of claim 17, wherein forming the first portion and the second portion comprises:

forming a mask layer on the initial first surface, wherein the mask layer is provided with a first opening, and part of the initial first surface is exposed out of the first opening;

etching the initial first surface along the first opening to form an initial first groove in the initial substrate and converting the initial first surface into the first surface;

Polishing the side wall and the bottom wall of the initial first groove to enable the side wall and the bottom wall of the initial first groove to have polishing surfaces so as to form an initial second groove;

performing a texturing process on the bottom wall and the side wall of the initial second groove to form a groove, wherein the bottom wall and the side wall of the groove are provided with the first texture structure;

and removing the mask layer, wherein the first surface corresponding to the groove is the first part, and the part except the groove is the second part.

19. The method of claim 18, wherein the texturing the bottom wall and the side walls of the initial second groove to form the first texture comprises:

cleaning the bottom wall and the side wall of the initial second groove;

preparing a wool making additive mother solution, wherein the wool making additive mother solution comprises sodium dodecyl benzene sulfonate and polyvinylpyrrolidone, and the mass ratio of the sodium dodecyl benzene sulfonate to the polyvinylpyrrolidone is 0.1-20;

providing deionized water, and adding the wool making additive mother liquor and sodium hydroxide into the deionized water to prepare etching liquid, wherein the volume ratio of the wool making additive mother liquor to the deionized water is 0.002-0.003, and the mass ratio of the sodium hydroxide to the deionized water is 0.03-0.1;

And cleaning the bottom wall and the side wall of the initial second groove by adopting the etching liquid to form the first texture structure.

20. The method of claim 19, wherein the method of forming the first tunneling layer comprises:

forming an initial first tunneling layer on the side wall and the bottom wall of the groove by adopting a deposition process, wherein two opposite surfaces of the initial first tunneling layer are provided with the first texture structure with the same shape as the side wall and the bottom wall of the groove;

and polishing the surface of the initial first tunneling layer, which is far away from the substrate, wherein the surface of the initial first tunneling layer, which is treated by the polishing process, is far away from the substrate, and the surface of the initial first tunneling layer, which is far away from the substrate, is provided with the second texture structure, so that the first tunneling layer is formed.