CN112885924A - Solar cell and manufacturing method thereof - Google Patents
Solar cell and manufacturing method thereof Download PDFInfo
- Publication number
- CN112885924A CN112885924A CN202110163667.3A CN202110163667A CN112885924A CN 112885924 A CN112885924 A CN 112885924A CN 202110163667 A CN202110163667 A CN 202110163667A CN 112885924 A CN112885924 A CN 112885924A
- Authority
- CN
- China
- Prior art keywords
- amorphous silicon
- layer
- region
- solar cell
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 179
- 239000000758 substrate Substances 0.000 claims abstract description 72
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
- 239000010703 silicon Substances 0.000 claims abstract description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 230000005641 tunneling Effects 0.000 claims abstract description 50
- 238000002161 passivation Methods 0.000 claims abstract description 35
- 238000012545 processing Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 149
- 230000008569 process Effects 0.000 claims description 120
- 238000010438 heat treatment Methods 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 37
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 19
- 238000010884 ion-beam technique Methods 0.000 claims description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000010894 electron beam technology Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000003795 chemical substances by application Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 description 37
- 229910021419 crystalline silicon Inorganic materials 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 230000006798 recombination Effects 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 238000007669 thermal treatment Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000013082 photovoltaic technology Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000010668 complexation reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000007530 organic bases Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a solar cell and a manufacturing method thereof, relates to the technical field of photovoltaics, and aims to reduce the manufacturing difficulty of a local passivation contact structure and improve the manufacturing efficiency. The manufacturing method of the solar cell comprises the following steps: providing a silicon substrate; forming a tunneling layer on the front side of the silicon substrate; forming an amorphous silicon layer on the tunneling layer; processing a target part of the amorphous silicon layer to form a doped polycrystalline silicon region and an amorphous silicon region; and removing the amorphous silicon region to obtain a local passivation contact structure positioned on the front surface of the silicon substrate. The solar cell is manufactured by the manufacturing method of the solar cell. The solar cell and the manufacturing method thereof provided by the invention are used for manufacturing the solar cell.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a solar cell and a manufacturing method thereof.
Background
With the continuous development of photovoltaic technology, crystalline silicon solar cell technology is mature day by day, and the conversion efficiency of the crystalline silicon solar cell technology is close to the theoretical limit. At present, the main factor influencing the open circuit voltage and conversion efficiency of the crystalline silicon solar cell is the recombination of carriers in the contact area between a metal electrode and crystalline silicon surface.
In order to reduce the carrier recombination of the metal electrode on the front side of the solar cell and the contact area of the crystalline silicon surface, a local passivation contact structure can be manufactured in the contact area of the crystalline silicon surface and the metal electrode. However, the manufacturing process of the local passivation contact structure is difficult and the efficiency is low.
Disclosure of Invention
The invention aims to provide a solar cell and a manufacturing method thereof, which aim to reduce the manufacturing difficulty of a local passivation contact structure and improve the manufacturing efficiency.
In a first aspect, the present invention provides a method for fabricating a solar cell. The manufacturing method of the solar cell comprises the following steps:
providing a silicon substrate;
forming a tunneling layer on the front side of the silicon substrate;
forming an amorphous silicon layer on the tunneling layer;
processing a target part of the amorphous silicon layer to form a doped polycrystalline silicon region and an amorphous silicon region;
and removing the amorphous silicon region to obtain a local passivation contact structure positioned on the front surface of the silicon substrate.
When the technical scheme is adopted, only the target part of the amorphous silicon layer is processed, so that the target part is converted into doped polycrystalline silicon, namely the amorphous silicon layer forms a doped polycrystalline silicon area and an amorphous silicon area. And then, the amorphous silicon region can be conveniently removed and the doped polycrystalline silicon region is reserved by utilizing the difference of the etching rates between the amorphous silicon and the doped polycrystalline silicon. The doped polysilicon region is located at a local position on the tunneling layer. At this time, a local passivation contact structure on the front surface of the silicon substrate may be formed. Based on the method, the amorphous silicon area is removed by utilizing the difference of the etching rate between the amorphous silicon and the doped polycrystalline silicon. On one hand, the amorphous silicon region is removed without using auxiliary means such as a mask and the like, and the local doped polycrystalline silicon region is reserved, so that the process steps are reduced, the process materials are reduced, the process can be simplified, the process difficulty is reduced, and the cost is reduced. On the other hand, the etching rate of the amorphous silicon is high, and the working efficiency of manufacturing the local passivation contact structure can be improved. Therefore, the manufacturing method of the solar cell can reduce the manufacturing difficulty of the local passivation contact structure on the front surface of the silicon substrate and improve the manufacturing efficiency.
In some implementations, the amorphous silicon layer is an intrinsic amorphous silicon layer or a doped amorphous silicon layer. The intrinsic amorphous silicon layer or the doped amorphous silicon layer has obvious etching rate difference with the doped polycrystalline silicon layer, and can be conveniently removed.
In some implementations, when the amorphous silicon layer is a doped amorphous silicon layer, processing the target portion of the amorphous silicon layer includes: a target portion of the amorphous silicon layer is heat treated. The target portion of the amorphous silicon layer is converted to doped polysilicon and the remainder of the amorphous silicon layer remains amorphous silicon. At this time, a doped polysilicon region and an amorphous silicon region of different materials can be formed for the heat treatment operation of the target portion of the amorphous silicon layer, thereby facilitating the removal of the amorphous silicon region therein.
In some implementations, when the amorphous silicon layer is an intrinsic amorphous silicon layer, processing the target portion of the amorphous silicon layer includes: doping a target part of the amorphous silicon layer; then, carrying out heat treatment on the target part of the amorphous silicon layer; wherein, the doping treatment process is an ion implantation process or a doping source coating advancing process.
When the technical scheme is adopted, the doped polycrystalline silicon region and the amorphous silicon region with different materials can be formed aiming at the doping treatment and the heat treatment operation of the target part of the amorphous silicon layer, so that the amorphous silicon region can be conveniently removed. And the ion implantation process and the doping source coating advancing process can locally dope the amorphous silicon layer.
In some implementations, the thermal treatment is a laser thermal treatment, an ion beam thermal treatment, or an electron beam thermal treatment. The laser, the ion beam and the electron beam can accurately position the target part of the amorphous silicon layer, so that only the target part is processed, and the amorphous silicon layer part except the target part is not processed. Therefore, when the laser, the ion beam or the electron beam is adopted for heat treatment, a mask process is not needed, so that the process steps can be simplified, the processing efficiency of local heat treatment can be improved, and the cost increase caused by the mask process can be avoided.
In some implementations, the laser used for the laser heat treatment is any one of an infrared laser, a green laser, and an ultraviolet laser.
In some implementations, the laser power used for the laser heat treatment is 5W to 100W. The laser power in the range can ensure that the laser used for laser heat treatment has enough heat to convert the amorphous silicon of the target part into polysilicon; and can avoid the damage to the surface of the target part of the amorphous silicon layer caused by excessive heat.
In some implementations, the energy implantation value of the laser heat treatment is 50mJ/cm2～1000mJ/cm2. This range of energy implantation may ensure that the targeted portion of amorphous silicon is converted to polysilicon.
In some implementations, the atmospheric environment of the above-described heat treatment contains water vapor. The flow rate of the water vapor is 1sccm to 500 sccm. At this time, the water vapor may provide an oxygen source so that the surface of the target portion of the amorphous silicon layer that is laser-heat treated, that is, the surface of the doped polysilicon region, generates an oxide layer. In the subsequent etching processes of removing the amorphous silicon region and the like, the oxide layer can protect the doped polycrystalline silicon region from being damaged, so that the integrity of the local passivation contact structure is ensured.
In some implementations, the process of removing the amorphous silicon region is a trench process or a chained single-sided process. When the chain type single-sided process is adopted, only the front side of the silicon substrate can be treated, so that the damage of the removal process to the back side of the silicon substrate is avoided.
In some implementations, the process of removing the amorphous silicon region is an etching process. The etching agent adopted by the etching process is an alkaline etching agent, the etching temperature is 25-80 ℃, and the etching time is 1-60 min; wherein the alkaline etchant comprises one or more of NaOH, KOH or an organic alkaline agent. Under the etching parameters, the amorphous silicon region can be removed quickly and efficiently, and the doped polycrystalline silicon region can be well reserved under the difference of the etching rates.
In some implementations, after removing the amorphous silicon region, the method for manufacturing a solar cell further includes: and (5) cleaning with deionized water. The deionized water cleaning can reduce the residual etchant and the adverse effect of the residual etchant on the subsequent process.
In some implementations, the tunneling layer is made of one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide.
In some implementations, after removing the amorphous silicon region, the method for manufacturing a solar cell further includes: removing the part of the tunneling layer covered by the amorphous silicon area; the process for removing the part of the tunneling layer covered by the amorphous silicon area is the same as the process for removing the amorphous silicon area. At this time, the amorphous silicon region and the tunneling layer portion covered by the amorphous silicon region can be removed by using the same process, so that the process can be simplified, and the efficiency can be improved.
In some implementations, after forming the locally passivated contact structure, the method of fabricating a solar cell further includes: an electrode is formed on the locally passivated contact structure. At this time, on one hand, the electrode is directly contacted with the doped polycrystalline silicon region instead of the silicon substrate, so that the carrier recombination of the semiconductor and the electrode can be reduced; on the other hand, the doped polycrystalline silicon region is only formed at the local position corresponding to the electrode on the front surface of the silicon substrate, so that the strong absorption of the doped polycrystalline silicon to sunlight can be reduced, and the absorption rate of the solar cell to the sunlight can be ensured.
In a second aspect, the present invention provides a solar cell. The solar cell is manufactured by the manufacturing method of the solar cell described in the first aspect or any possible implementation manner of the first aspect.
The advantages of the solar cell provided by the second aspect may refer to the advantages of the method for manufacturing a solar cell described in the first aspect or any possible implementation manner of the first aspect, which will not be further described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present invention;
fig. 2 to fig. 10 are schematic diagrams illustrating states of various stages of a method for manufacturing a solar cell according to an embodiment of the present invention.
In fig. 1-10, 10-substrate, 101-textured structure, 11-doped layer, 12-tunneling layer, 13-amorphous silicon layer, 130-target portion, 131-doped polysilicon region, 132-amorphous silicon region, 14-first passivation layer, 15-first electrode, 21-second passivation layer, and 22-second electrode.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
With the development of the solar photovoltaic market, people have more and more urgent demands on high-efficiency crystalline silicon solar cells. Moreover, with the continuous development of photovoltaic technology, the manufacturing cost of the crystalline silicon solar cell is continuously reduced. At present, the trend of photovoltaic industry is to manufacture high-quality and low-cost crystalline silicon solar cells.
For crystalline silicon solar energy, the surface passivation technology is mature day by day, and the passivation effect tends to be saturated. At this time, the main factor limiting the improvement of the open circuit voltage and the conversion efficiency of the crystalline silicon solar cell is that the recombination current of the metal electrode and the crystalline silicon surface contact area is too large. The contact recombination current is two orders of magnitude higher than the non-contact region recombination current.
The tunneling layer passivation contact technology can reduce the composite current of the contact area between the metal electrode and the crystalline silicon surface, and meanwhile, in order to reduce the absorption of the doped polycrystalline silicon film in the passivation contact structure to sunlight, a local passivation contact structure can be arranged on the front side of the crystalline silicon solar cell. However, in the prior art, the manufacturing process of the local passivation contact structure is difficult, the efficiency is low, and the cost of the crystalline silicon solar cell is increased.
In order to solve the above technical problems, embodiments of the present invention provide a solar cell. As shown in fig. 1, the front side of the solar cell is provided with a locally passivated contact structure on which the electrodes of the front side of the solar cell are formed.
The embodiment of the invention also provides a manufacturing method of the solar cell. As shown in fig. 2 to 10, the method for manufacturing the solar cell includes the following steps:
as shown in fig. 2, a substrate 10 is provided. The substrate 10 may be an n-type semiconductor substrate or a p-type semiconductor substrate. The material of the substrate 10 is silicon, which may be monocrystalline silicon or polycrystalline silicon. The front and back surfaces of the substrate 10 are identical to those of the solar cell, the front surface is a surface facing sunlight, and the back surface is a backlight surface. The method for manufacturing the solar cell will be described below by taking an n-type substrate as an example.
As shown in fig. 3, the substrate 10 is subjected to a texturing process. Specifically, the single-sided texturing process may be performed on the substrate 10, or the double-sided texturing process may be performed on the substrate 10.
In practice, the substrate 10 is first subjected to a de-marring and polishing process, and then the substrate 10 is treated with an alkaline solution having an additive. After the treatment, a textured structure 101 with a pyramid shape is formed on the surface of the substrate 10. The texture structure 101 can play a role in trapping light, so that the reflection of the solar cell to sunlight is reduced, and the performance of the solar cell is improved. Of course, in some methods for manufacturing solar cells, the texturing process may be omitted.
As shown in fig. 4, the front surface of the substrate 10 is subjected to doping treatment to form a first conductivity-type doped layer 11.
The first conductivity type may be either p-type or n-type. When the first conductivity type is n-type, the doped layer 11 is n-type doped. The doping source of the doped layer 11 may be a group VA element such As phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb). When the first conductivity type is p-type, the doped layer 11 is p-type doped. The doping source of the doping layer 11 may be a group iiia element such as boron (B), aluminum (Al), gallium (Ga), and indium (In).
The process of forming the first conductive-type doping layer 11 may be any one of a thermal diffusion process, an ion implantation process, and a dopant source coating drive-in process.
The substrate 10, on which the doped layer 11 is formed, may be defined as a silicon substrate. The front and back surfaces of the silicon substrate correspond to the front and back surfaces of the substrate 10 one by one. It should be understood that, when manufacturing a solar cell, the substrate 10 may be used as a starting point for the process, or the silicon substrate defined in the embodiment of the present invention may be used as a starting point for the process.
As shown in fig. 5, a tunneling layer 12 is formed on the front side of the silicon substrate. The tunneling layer 12 is formed entirely on the doped layer 11. The tunneling layer 12 may create a tunneling effect, allowing majority carriers to pass while blocking minority carriers. Also, the tunneling layer 12 may also serve to prevent the dopant in the doped polysilicon region 131 from diffusing into the silicon substrate.
The material of the tunneling layer 12 may include various materials through which the majority carriers can tunnel. Such as oxides, nitrides, semiconductors, and conductive polymers. Specifically, the material of the tunneling layer 12 may be one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide. Silicon oxide is preferred as the tunneling layer 12, which has better passivation characteristics and carriers easily tunnel through the silicon oxide layer. The thickness of the tunneling layer 12 may be 0.5nm to 5 nm.
The process of forming the tunneling layer 12 may be a physical vapor deposition process, or may be a chemical vapor deposition process such as Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or plasma chemical vapor deposition (PECVD). When the tunneling layer 12 is a silicon oxide layer, the process of forming the tunneling layer 12 may also be a thermal oxidation process or a chemical oxidation process.
In practical applications, the pressure at which the tunneling layer 12 is formed may be set to be lower than the atmospheric pressure to reduce the growth rate of the tunneling layer 12. For example, when the tunnel layer 12 is formed on the surface of the doped layer 11 by using a thermal oxidation process, the operating pressure of the thermal oxidation process may be set to be lower than the atmospheric pressure. At this time, although the operating temperature of the thermal oxidation process is high (600 ℃ or higher), the thickness of the tunneling layer 12 can be significantly reduced because the operating pressure is low, so that the growth rate of the tunneling layer 12 can be maintained low. Specifically, the operating temperature of the thermal oxidation process may be set to 600 ℃ to 800 ℃, and the operating pressure may be set to 600 Torr (Torr) or less, in order to effectively control the thickness of the tunneling layer 12.
It should be appreciated that after the formation of the thinner tunneling layer 12, the thickness, density of the tunneling layer 12 may also be increased by heat treatment. After increasing the thickness, the thickness of the tunneling layer 12 still does not exceed 5 nm.
The deposition process or the thermal oxidation process for forming the tunneling layer 12 described above may be performed in a deposition apparatus. In view of the low pressure environment required by the process of forming the tunneling layer 12, the tunneling layer 12 can be fabricated in a low pressure chemical vapor deposition apparatus.
As shown in fig. 6, an amorphous silicon layer 13 is formed on the tunneling layer 12.
The amorphous silicon layer 13 may be an intrinsic amorphous silicon layer or a doped amorphous silicon layer. The doped amorphous silicon layer is of the first conductivity type and has the same doping type as the doped layer 11. The intrinsic amorphous silicon layer or the doped amorphous silicon layer has obvious etching rate difference with a doped polycrystalline silicon layer formed subsequently, and can be removed conveniently. The thickness of the amorphous silicon layer 13 may be 20nm to 200 nm.
The process of forming the amorphous silicon layer 13 may be a physical vapor deposition Process (PVD), a low pressure chemical vapor deposition process (LPCVD), a plasma chemical vapor deposition Process (PECVD), or the like. When the amorphous silicon layer 13 is a doped amorphous silicon layer, the doped amorphous silicon layer may be formed by in-situ doping.
The apparatus for forming the amorphous silicon layer 13 may be an LPCVD device. At this time, the tunneling layer 12 and the amorphous silicon layer 13 may be formed continuously by the same LPCVD apparatus. In this case, the same apparatus is used to complete two processes, thereby simplifying the process flow, reducing the manufacturing time, and reducing the manufacturing cost.
When the tunneling layer 12 and the amorphous silicon layer 13 are formed by the LPCVD apparatus, the difference between the operating temperature for forming the tunneling layer 12 and the operating temperature for forming the amorphous silicon layer 13 may be set to be in the range of 0 to 200 ℃. Preferably, the temperature difference may be in the range of 0 ℃ to 100 ℃. At this time, the difference between the operating temperatures of the two processes is small, and the time required for changing the operating temperature can be reduced, so that the efficiency of continuously forming the tunneling layer 12 and the amorphous silicon layer 13 can be further improved. And, when the temperature difference is small, the two process parameters change less, and a relatively difficult-to-control temperature can be maintained more easily.
As shown in fig. 7, the target portion 130 of the amorphous silicon layer 13 is processed to form doped polysilicon regions 131 and amorphous silicon regions 132.
The target portion 130 of the amorphous silicon layer 13 is a region intended to contact an electrode. The area of the target portion 130 may be equal to or larger than the projected area of the electrode on the silicon substrate. It should be understood that the area of the target portion 130 should be as close as possible to the projected area of the electrode on the silicon substrate to reduce the area of the target portion 130 and reduce the absorption of sunlight by the doped polysilicon formed by the target portion 130.
After processing the target portion 130 of the amorphous silicon layer 13, the target portion 130 is converted into a doped polysilicon region 131, and the portion of the amorphous silicon layer 13 other than the target portion 130 remains as an amorphous silicon region 132. That is, the process causes the amorphous silicon of the target portion 130 to be converted to doped polysilicon.
When the amorphous silicon layer 13 is a doped amorphous silicon layer, the processing of the target portion 130 of the amorphous silicon layer 13 includes: the target portion 130 of the amorphous silicon layer 13 is heat treated. After the heat treatment, the target portion 130 is converted into doped polysilicon, and the portion of the amorphous silicon layer 13 outside the target portion 130 is doped amorphous silicon. At this time, for the heat treatment operation of the target portion 130 of the amorphous silicon layer 13, the doped polysilicon region 131 and the amorphous silicon region 132 with different materials may be formed, thereby facilitating the subsequent process to remove the amorphous silicon region 132 therein.
When the amorphous silicon layer 13 is an intrinsic amorphous silicon layer, the above-mentioned processing of the target portion 130 of the amorphous silicon layer 13 includes: performing a doping process on the target portion 130 of the amorphous silicon layer 13; the target portion 130 of the amorphous silicon layer 13 is then heat treated. After the doping treatment, the target portion 130 is converted into doped amorphous silicon of the first conductivity type, and after the heat treatment, the target portion 130 is converted into doped polycrystalline silicon; the portion of the amorphous silicon layer 13 outside the target portion 130 is intrinsic amorphous silicon. For the doping treatment and the thermal treatment operation of the target portion 130 of the amorphous silicon layer, the doped polysilicon region 131 and the amorphous silicon region 132 having different materials may be formed, thereby facilitating the removal of the amorphous silicon region 132 therein.
The doping treatment and the heat treatment are both treatment processes for a part of the amorphous silicon layer 13, not the entire amorphous silicon layer 13.
The doping process may be an ion implantation process or a dopant source coating process. Illustratively, an ion implantation process may be employed using elemental boron, B2H6、BF3Or BCl3The dopant source is isodoped to perform a doping process on the target portion 130 of the intrinsic amorphous silicon layer. The ion implantation process has implantation energy of 0.5 keV-15 keV and impurity implantation dosage of 1 × 1014/cm2～1×1016/cm2The temperature can be 300-700 ℃. Specifically, when implanting boron ions into the target portion 130, a barrier layer (or a mask) having a hollowed-out region may be disposed between a silicon substrate to be processed and the boron ion beam. The hollowed-out region corresponds to a target portion 130 of the amorphous silicon layer 13. And the boron ion beam current and the barrier layer (mask) are partially overlapped, and in the process that the silicon substrate moves and passes through the boron ion beam current, the target part 130 in the amorphous silicon layer 13 forms a doped amorphous silicon part under the shielding of the barrier layer, so that the local doping of the amorphous silicon layer 13 is realized.
The heat treatment may be laser heat treatment, electron beam heat treatment, or ion beam heat treatment. When the heat treatment is performed using the laser, the electron beam, and the ion beam, the target portion 130 of the amorphous silicon layer 13 may be precisely positioned, thereby achieving the treatment of only the target portion 130 and the non-treatment of the portion of the amorphous silicon layer 13 other than the target portion 130. Therefore, when the laser, the electron beam or the ion beam is adopted for heat treatment, a mask process is not needed, so that the process steps can be simplified, the processing efficiency of local heat treatment can be improved, and the cost increase caused by the mask process can be avoided.
The laser used for the laser heat treatment may be any one of infrared laser, green laser, and ultraviolet laser. The lasers may be made of CO2Any one of a laser, an excimer laser, a titanium sapphire laser, a semiconductor laser, a copper vapor laser, or a Nd: YAG laser.
The laser power used for the laser heat treatment may be 5W to 100W. For example, the laser power of the laser heat treatment may be 5W, 10W, 25W, 30W, 44W, 56W, 78W, 80W, 95W, 100W, or the like. The laser power in this range can ensure that the laser used for the laser heat treatment has enough heat to convert the amorphous silicon of the target portion 130 into polysilicon; and damage to the surface of the target portion 130 of the amorphous silicon layer 13 due to excessive heat can be avoided.
The energy injection value of the laser heat treatment may be 50mJ/cm2～1000mJ/cm2. For example, the energy implantation value of the laser heat treatment may be 50mJ/cm2、100mJ/cm2、250mJ/cm2、460mJ/cm2、580mJ/cm2、720mJ/cm2、950mJ/cm2Or 1000mJ/cm2. This range of energy implantation may ensure that the amorphous silicon of the target portion 130 is converted to polysilicon.
The atmosphere for the heat treatment may contain water vapor. Specifically, the flow rate of the water vapor may be 1sccm to 500 sccm. For example: the flow rate of the water vapor can be 1sccm, 10sccm, 80sccm, 100sccm, 150sccm, 200sccm, 300sccm, 400sccm, 500sccm, or the like. At this time, the water vapor may provide an oxygen source, so that the surface of the target portion 130, i.e., the surface of the doped polysilicon region 131, which is laser-heat treated, is oxidized. The oxide layer can protect the doped polysilicon region 131 from being damaged during subsequent etching processes such as removing the amorphous silicon region 132, thereby ensuring the integrity of the local passivation contact structure.
It is noted that, for the intrinsic amorphous silicon layer, the heat treatment may not only crystallize the amorphous silicon of the target portion 130 into polycrystalline silicon, but also activate impurities implanted by the ion implantation process of the target portion 130 or drive the dopant source coated by the target portion 130. Of course, an annealing process may be added before the heat treatment to activate the impurities implanted by the ion implantation process in the target portion 130 or to drive in the dopant source coated by the target portion 130.
As shown in fig. 8, amorphous silicon region 132 is removed.
The process of removing the amorphous silicon region 132 is an etching process. The etchant used in the etching process can be alkaline etchant, and the alkaline etchant comprises one or more of NaOH, KOH or organic alkaline reagent; the organic base may be tetramethylammonium hydroxide (TMAH) or the like. The ratio of the etching rate of the alkaline etchant to the doped polysilicon region 131 and the amorphous silicon region 132 is 1 (5-100). That is, the etch rate of the amorphous silicon region 132 is 5-100 times the etch rate of the doped polysilicon region 131, and the etchant etches the amorphous silicon region 132 at a much greater rate than the doped polysilicon region 131. In the process of removing the amorphous silicon region 132 using the alkaline etchant, the amorphous silicon may be completely removed, while the thickness of the doped polysilicon region 131 is only slightly reduced.
The etching temperature of the etching process may be 25 ℃ to 80 ℃, such as 25 ℃, 34 ℃, 45 ℃, 56 ℃, 68 ℃, 75 ℃ or 80 ℃. The etching time can be 1min to 60min, such as 1min, 10min, 25min, 38min, 44min, 55min or 60 min. Under the etching parameters, the amorphous silicon region 132 can be removed quickly and efficiently, and the doped polysilicon region 131 can be well remained under the difference of the etching rates.
In terms of the process, the process of removing the amorphous silicon region 132 may be a trench process or a chain type single-sided process.
When the amorphous silicon region 132 is removed using the trench process, the silicon substrate treated by the above process may be immersed in a trench apparatus containing an etchant. During processing, the amorphous silicon region 132 on the front side of the silicon substrate is removed. Meanwhile, the doped polysilicon region 131 is not damaged due to the slow etching rate of the doped polysilicon region 131 and the protection of the oxide layer on the surface of the doped polysilicon region 131. For the back surface of the silicon substrate, a mask such as an oxide layer or a nitride layer can be disposed to prevent the semiconductor structure on the back surface of the silicon substrate from being damaged.
When the chain type single-sided process is adopted, the crawler type etching equipment can be utilized, and the roller type etching equipment can also be utilized for carrying out the removal process. At this time, only the front surface of the silicon substrate may be processed, thereby avoiding damage to the back surface of the silicon substrate by the removal process. Illustratively, the track-type etching apparatus includes one or more tanks, each tank containing an alkaline etchant therein. In the process of removing the amorphous silicon region 132 by using the crawler-type etching device, the front surface of the silicon substrate faces the tank body, and the amorphous silicon region 132 is in contact with the liquid level of the etchant in the tank body. The amorphous silicon regions 132 remain in contact with the etchant and pass through the tank such that the amorphous silicon regions 132 are removed without damaging the semiconductor structure on the backside of the silicon substrate. Preferably, water may be sprayed on the back surface of the silicon substrate by a water film device to form a water film to protect the back surface of the silicon substrate.
During the etching process, although the doped polysilicon region 131 is also in contact with the etchant, the etchant etches the doped polysilicon very slowly and has an oxide layer on its surface to protect it, so that it can be retained.
In practical applications, after removing the amorphous silicon region 132, a deionized water cleaning process may be performed. The deionized water cleaning can reduce the residual etchant and the adverse effect of the residual etchant on the subsequent process.
It should be noted that before the amorphous silicon region 132 is removed, a chain type single-sided film removal process may be performed on the back surface of the silicon substrate to remove the spin-on-plated oxide layer on the back surface of the silicon substrate during the process of forming the amorphous silicon layer 13 and the doped polysilicon region 131. For example, when the winding-plated oxide layer on the back surface of the silicon substrate is removed by using a chain type single-side stripping process, the roller type etching device is provided with one or more tank bodies, and each tank body contains an etchant such as hydrofluoric acid. A water film is formed on the front surface of the silicon substrate to protect the structure on the front surface of the silicon substrate. Then, the back surface of the silicon substrate faces the tank body, and the winding and plating oxide layer is in contact with the liquid level of the etchant in the tank body. The plating oxide layer is kept in contact with the etchant and passes through the tank body, so that the plating oxide layer is removed without damaging the front surface of the silicon substrate.
After removing the plating oxide layer, the plating oxide layer can be cleaned by HCl solution and water. Cl in HCl solution-The complexation of ions can greatly reduce the content of metal ions, thereby reducing the metal ion residues on the surface of the silicon substrate.
After removing the amorphous silicon region 132, the portion of the tunneling layer 12 covered by the amorphous silicon region 132 may also be removed. Of course, the step of removing the portion of the tunneling layer 12 covered by the amorphous silicon region 132 may be omitted in view of the fact that the tunneling layer 12 has a small thickness and less absorption of sunlight.
The process of removing the portion of the tunneling layer 12 covered by the amorphous silicon region 132 is the same as the process of removing the amorphous silicon region 132. At this time, the tunneling layer 12 may be removed at the same time as the amorphous silicon region 132 is removed. The amorphous silicon region 132 and the portion of the tunneling layer 12 covered by the amorphous silicon region 132 are removed by the same process, thereby simplifying the process and improving the efficiency.
After the process, the local passivation contact structure positioned on the front surface of the silicon substrate can be obtained. Based on the above manufacturing process, only the target portion 130 of the amorphous silicon layer 13 is processed, so that the doped polysilicon region 131 and the amorphous silicon region 132 are formed in the amorphous silicon layer 13. Subsequently, the amorphous silicon region 132 can be conveniently removed by utilizing the difference of the etching rates between the amorphous silicon and the doped polysilicon, and the doped polysilicon region 131 is remained. The doped polysilicon region 131 is located at a local position on the tunneling layer 12. At this time, a local passivation contact structure on the front surface of the silicon substrate may be formed. Based on this, the present invention utilizes the difference in etching rate between amorphous silicon and doped polysilicon to remove the amorphous silicon region 132. On one hand, the amorphous silicon region 132 is not required to be removed by using auxiliary means such as a mask and the like, and the local doped polysilicon region 131 is reserved, so that the process steps are reduced, the process materials are reduced, the process can be simplified, the process difficulty is reduced, and the cost is reduced. On the other hand, the etching rate of the amorphous silicon is high, and the working efficiency of manufacturing the local passivation contact structure can be improved. Therefore, the manufacturing method of the solar cell provided by the embodiment of the invention can not only reduce the manufacturing difficulty of the local passivation contact structure on the front surface of the silicon substrate, but also improve the manufacturing efficiency.
As shown in fig. 9, the front surface of the silicon substrate is passivated to form a first passivation layer 14; the back surface of the silicon substrate is passivated to form a second passivation layer 21.
The material of the first passivation layer 14 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The material of the second passivation layer 21 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The first passivation layer 14 and the second passivation layer 21 may be made of the same material or different materials.
The process of forming the first passivation layer 14 and the second passivation layer 21 may be one of an enhanced plasma chemical vapor deposition process and an atomic layer deposition process.
As shown in fig. 10, a first electrode 15 is formed on the front surface of the silicon substrate, the first electrode 15 being in electrical contact with the doped polysilicon region 131. That is, the first electrode 15 is formed on the above-described local passivation structure. A second electrode 22 is formed on the back side of the silicon substrate, the second electrode 22 being in electrical contact with the silicon substrate. The material of the first electrode 15 and the second electrode 22 may each comprise one or more of silver, copper, aluminum, nickel, titanium, tungsten, tin.
In practice, the first electrode 15 and the second electrode 22 may be formed using a metallization process. Specifically, the metallization process may be one or more of a PVD process, a screen printing process, an electroplating process, an electroless plating process, a laser transfer process, and a spraying process.
The process of forming the electrode may or may not include a thermal annealing treatment. For example, when a silver electrode is formed by screen printing, thermal annealing at 700-1000 ℃ is required for sintering and molding. For another example, when a metal electrode layer is formed by electroplating, thermal annealing at 300-700 ℃ is required to form an ohmic contact of metal silicide.
It should be noted that, in the embodiment of the present invention, a specific structure of the back surface of the silicon substrate is not limited. Besides the structure formed by the manufacturing method of the solar cell, a passivation contact structure, a point contact structure, a back local diffusion structure and the like can also be formed on the back surface of the silicon substrate. When the front surface of the silicon substrate is doped in an n-type manner, the back surface of the silicon substrate can also form a back aluminum alloy contact structure.
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (14)
1. A manufacturing method of a solar cell is characterized by comprising the following steps:
providing a silicon substrate;
forming a tunneling layer on the front side of the silicon substrate;
forming an amorphous silicon layer on the tunneling layer;
processing a target part of the amorphous silicon layer to form a doped polycrystalline silicon region and an amorphous silicon region;
and removing the amorphous silicon region to obtain a local passivation contact structure positioned on the front surface of the silicon substrate.
2. The method of claim 1, wherein the amorphous silicon layer is an intrinsic amorphous silicon layer or a doped amorphous silicon layer.
3. The method of claim 2, wherein when the amorphous silicon layer is a doped amorphous silicon layer, the processing the target portion of the amorphous silicon layer comprises:
and performing heat treatment on the target part of the amorphous silicon layer.
4. The method of claim 2, wherein when the amorphous silicon layer is an intrinsic amorphous silicon layer, the processing the target portion of the amorphous silicon layer comprises: doping a target part of the amorphous silicon layer; then carrying out heat treatment on the target part of the amorphous silicon layer; wherein, the doping treatment process is an ion implantation process or a doping source coating advancing process.
5. The method of claim 3 or 4, wherein the heat treatment is a laser heat treatment, an ion beam heat treatment or an electron beam heat treatment.
6. The method for manufacturing the solar cell according to claim 5, wherein the laser used for the laser heat treatment is any one of an infrared laser, a green laser and an ultraviolet laser; and/or the laser power adopted by the laser heat treatment is 5W-100W; and/or the energy injection value of the laser heat treatment is 50mJ/cm2～1000mJ/cm2。
7. The method according to claim 5, wherein the atmosphere of the heat treatment comprises water vapor, and the flow rate of the water vapor is 1sccm to 500 sccm.
8. The method of claim 1, wherein the amorphous silicon region is removed by a trench process or a chain single-sided process.
9. The method for manufacturing the solar cell according to claim 8, wherein the process for removing the amorphous silicon region is an etching process, an etchant adopted by the etching process is an alkaline etchant, the etching temperature is 25-80 ℃, and the etching time is 1-60 min;
wherein the alkaline etchant comprises one or more of NaOH, KOH or an organic alkaline agent.
10. The method of claim 1, wherein after removing the amorphous silicon region, the method further comprises: and (5) cleaning with deionized water.
11. The method of claim 1, wherein the tunneling layer is made of one or more of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide.
12. The method of claim 1, wherein after removing the amorphous silicon region, the method further comprises: removing the part of the tunneling layer covered by the amorphous silicon area; and the process for removing the part of the tunneling layer covered by the amorphous silicon region is the same as the process for removing the amorphous silicon region.
13. The method of claim 1, wherein after obtaining the locally passivated contact structure, the method further comprises: forming an electrode on the locally passivated contact structure.
14. A solar cell manufactured by the method for manufacturing a solar cell according to any one of claims 1 to 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110163667.3A CN112885924A (en) | 2021-02-05 | 2021-02-05 | Solar cell and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110163667.3A CN112885924A (en) | 2021-02-05 | 2021-02-05 | Solar cell and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112885924A true CN112885924A (en) | 2021-06-01 |
Family
ID=76057483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110163667.3A Pending CN112885924A (en) | 2021-02-05 | 2021-02-05 | Solar cell and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112885924A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020533A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of POLO-IBC battery |
| US11791426B1 (en) | 2022-09-08 | 2023-10-17 | Zhejiang Jinko Solar Co., Ltd. | Photovoltaic cell and photovoltaic module |
| US11848397B1 (en) | 2022-06-15 | 2023-12-19 | Zhejiang Jinko Solar Co., Ltd. | Method for preparing solar cell and solar cell, photovoltaic module |
| US11923468B1 (en) | 2022-09-08 | 2024-03-05 | Zhejiang Jinko Solar Co., Ltd. | Photovoltaic cell and photovoltaic module |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574225A (en) * | 2003-05-20 | 2005-02-02 | Lg.飞利浦Lcd有限公司 | Method of fabricating polycrystalline silicon and switching device using polycrystalline silicon |
| CN1577772A (en) * | 2003-06-25 | 2005-02-09 | Lg.菲利浦Lcd株式会社 | Method of fabricating bottom-gated polycrystalline silicon thin film transistor |
| CN1577022A (en) * | 2003-06-30 | 2005-02-09 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
| CN107195699A (en) * | 2017-07-12 | 2017-09-22 | 泰州中来光电科技有限公司 | One kind passivation contact solar cell and preparation method |
| CN110098279A (en) * | 2018-01-30 | 2019-08-06 | 上海凯世通半导体股份有限公司 | The production method of solar battery |
| CN209232797U (en) * | 2018-10-17 | 2019-08-09 | 晶澳太阳能有限公司 | Silica-based solar cell and photovoltaic module |
| CN110610997A (en) * | 2019-09-17 | 2019-12-24 | 泰州中来光电科技有限公司 | Preparation method of local passivation contact structure |
| CN110634996A (en) * | 2019-09-27 | 2019-12-31 | 浙江晶科能源有限公司 | Manufacturing method of passivation structure, passivation structure and photovoltaic cell |
| CN111063761A (en) * | 2018-10-17 | 2020-04-24 | 晶澳太阳能有限公司 | Preparation process of solar cell |
| CN111063760A (en) * | 2018-10-17 | 2020-04-24 | 晶澳太阳能有限公司 | Preparation process of solar cell |
| CN111628049A (en) * | 2020-06-11 | 2020-09-04 | 常州时创能源股份有限公司 | Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof |
| CN111725359A (en) * | 2020-06-17 | 2020-09-29 | 泰州中来光电科技有限公司 | Preparation method of passivated contact solar cell |
-
2021
- 2021-02-05 CN CN202110163667.3A patent/CN112885924A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574225A (en) * | 2003-05-20 | 2005-02-02 | Lg.飞利浦Lcd有限公司 | Method of fabricating polycrystalline silicon and switching device using polycrystalline silicon |
| CN1577772A (en) * | 2003-06-25 | 2005-02-09 | Lg.菲利浦Lcd株式会社 | Method of fabricating bottom-gated polycrystalline silicon thin film transistor |
| CN1577022A (en) * | 2003-06-30 | 2005-02-09 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
| CN107195699A (en) * | 2017-07-12 | 2017-09-22 | 泰州中来光电科技有限公司 | One kind passivation contact solar cell and preparation method |
| CN110098279A (en) * | 2018-01-30 | 2019-08-06 | 上海凯世通半导体股份有限公司 | The production method of solar battery |
| CN209232797U (en) * | 2018-10-17 | 2019-08-09 | 晶澳太阳能有限公司 | Silica-based solar cell and photovoltaic module |
| CN111063761A (en) * | 2018-10-17 | 2020-04-24 | 晶澳太阳能有限公司 | Preparation process of solar cell |
| CN111063760A (en) * | 2018-10-17 | 2020-04-24 | 晶澳太阳能有限公司 | Preparation process of solar cell |
| CN110610997A (en) * | 2019-09-17 | 2019-12-24 | 泰州中来光电科技有限公司 | Preparation method of local passivation contact structure |
| CN110634996A (en) * | 2019-09-27 | 2019-12-31 | 浙江晶科能源有限公司 | Manufacturing method of passivation structure, passivation structure and photovoltaic cell |
| CN111628049A (en) * | 2020-06-11 | 2020-09-04 | 常州时创能源股份有限公司 | Method for realizing local hole passivation contact, crystalline silicon solar cell and preparation method thereof |
| CN111725359A (en) * | 2020-06-17 | 2020-09-29 | 泰州中来光电科技有限公司 | Preparation method of passivated contact solar cell |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020533A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of POLO-IBC battery |
| US11848397B1 (en) | 2022-06-15 | 2023-12-19 | Zhejiang Jinko Solar Co., Ltd. | Method for preparing solar cell and solar cell, photovoltaic module |
| US11791426B1 (en) | 2022-09-08 | 2023-10-17 | Zhejiang Jinko Solar Co., Ltd. | Photovoltaic cell and photovoltaic module |
| US11923468B1 (en) | 2022-09-08 | 2024-03-05 | Zhejiang Jinko Solar Co., Ltd. | Photovoltaic cell and photovoltaic module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112885925B (en) | Solar cell and manufacturing method thereof | |
| US11721783B2 (en) | Solar cell and method for manufacturing the same | |
| CN112885924A (en) | Solar cell and manufacturing method thereof | |
| US8309446B2 (en) | Hybrid heterojunction solar cell fabrication using a doping layer mask | |
| US10840395B2 (en) | Deposition approaches for emitter layers of solar cells | |
| JP2011503910A (en) | Solar cell contact formation process using patterned etchant | |
| CN110610997B (en) | Preparation method of local passivation contact structure | |
| CN112510105A (en) | High-efficiency solar cell and preparation method thereof | |
| CN112635592A (en) | Solar cell and manufacturing method thereof | |
| CN112599616A (en) | Solar cell and manufacturing method thereof | |
| CN112349798A (en) | Solar cell and method for manufacturing same | |
| CN112133793A (en) | Back-junction back-contact solar cell and manufacturing method thereof | |
| CN115172481A (en) | Heterojunction solar cell | |
| CN112582485B (en) | Solar cell and manufacturing method thereof | |
| KR100992483B1 (en) | Solar cell and fabrication method thereof | |
| CN112466960A (en) | Solar cell structure and preparation method thereof | |
| KR102049604B1 (en) | Solar cell and Method of manufacturing the same | |
| US20120270365A1 (en) | Method for manufacturing solar cell | |
| CN112582484A (en) | Solar cell and manufacturing method thereof | |
| CN114256361A (en) | Solar cell and photovoltaic module | |
| US10923618B2 (en) | Method for manufacturing a photovoltaic device | |
| CN112599618A (en) | Solar cell and manufacturing method thereof | |
| JP5843734B2 (en) | Photoelectric conversion element and manufacturing method thereof | |
| JP2001068709A (en) | Thin-film solar battery | |
| CN117712219A (en) | Solar cell and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |