CN117674853A

CN117674853A - Sample hold circuit and time digital converter

Info

Publication number: CN117674853A
Application number: CN202311512245.8A
Authority: CN
Inventors: 李榜添; 王辰阳; 曹凌峰; 贾耀仓; 孔庆凯
Original assignee: Beijing Zhongke Haixin Technology Co ltd
Current assignee: Beijing Zhongke Haixin Technology Co ltd
Priority date: 2023-11-14
Filing date: 2023-11-14
Publication date: 2024-03-08

Abstract

The present disclosure relates to a sample-and-hold circuit and a time-to-digital converter, the circuit comprising: the reset circuit is used for resetting the comparison circuit by utilizing a local reset signal before the preset edge of the time signal arrives; the comparison circuit is used for outputting a first sampling result of the time signal based on the first control signal when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, and outputting a second sampling result of the time signal based on the second control signal when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal. The circuit can ensure that the sample and hold can be completed quickly and accurately, and is convenient for integrating the time-to-digital converter.

Description

Sample hold circuit and time digital converter

Technical Field

The present disclosure relates to the field of electronic circuits, and in particular, to a sample-and-hold circuit and a time-to-digital converter.

Background

A Time-to-Digital Converters, TDC) is a high precision timing circuit that converts the Time difference between two digital pulses into digital values with picosecond resolution. Compared with an Analog-to-Digital Converter (ADC), the TDC can conveniently and directly convert time signals, has high reliability and is suitable for an on-chip integrated system.

In the related art, a TDC structure based on a ring oscillator may sample and hold signals corresponding to phase edges on a delay chain circuit by a sample and hold circuit when time signals are temporary. At present, a sample-hold circuit adopts a D trigger to sample and hold, but the trigger time triggered by the edge of the D trigger is unstable, and the time signal inversion transmitted to the sample-hold circuit is limited by the gate delay of a delay chain circuit (namely, rising delay from low level to high level and falling delay from high level to low level exist), so that the D trigger is difficult to accurately sample and hold the time signal.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a sample-and-hold circuit including: the device comprises a comparison circuit and a reset circuit, wherein a first control end of the comparison circuit is used for being connected with a first control signal, a second control end of the comparison circuit is used for being connected with a second control signal, a control end of the reset circuit is used for being connected with a reset signal, an input end of the comparison circuit is electrically connected with a power supply end, an output end of the comparison circuit is electrically connected with an input end of the reset circuit, and an output end of the reset circuit is electrically connected with a grounding end;

The reset circuit is used for resetting the comparison circuit by utilizing the reset signal before the preset edge of the time signal arrives; the comparison circuit is used for outputting a first sampling result of the time signal based on the first control signal when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, and outputting a second sampling result of the time signal based on the second control signal when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal.

According to another aspect of the present disclosure, there is provided a time-to-digital converter including: the delay chain circuit is used for generating a preset clock signal and is provided with a multi-stage delay signal interface;

the time-to-digital converter further comprises a plurality of sampling and holding circuits according to the exemplary embodiments of the present disclosure, a first input end of each sampling and holding circuit is used for accessing a preset edge trigger signal of a start time signal, each stage of delay signal interface is electrically connected with a second input end of the corresponding sampling and holding circuit, and each sampling and holding circuit is electrically connected with the data processing circuit.

In one or more technical schemes provided in exemplary embodiments of the present disclosure, a control end of a reset circuit is used for accessing a reset signal, a first control end of a comparison circuit is used for accessing a first control signal, a second control end of the comparison circuit is used for accessing a second control signal, an output end of the comparison circuit is electrically connected with an input end of the reset circuit, and an output end of the reset circuit is electrically connected with a ground end, so that the reset circuit can reset the comparison circuit by using the reset signal before a preset edge of a time signal arrives. On the basis, the comparison circuit outputs a first sampling result of the time signal based on the first control signal when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, and outputs a second sampling result of the time signal based on the second control signal when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal.

As can be seen, the sample-hold circuit of the exemplary embodiment of the present disclosure cooperates with the reset circuit by the comparison circuit, according to the sequence of the preset edge of the time signal and the preset edge arrival time of the delay signal, the sampling results of different types of time signals are output, and the preset edge arrival time of the delay signal is related to the delay position included in the delay chain circuit, so when the sample-hold circuit of the exemplary embodiment of the present disclosure is applied to the time-to-digital converter, the sampling results of the time signals corresponding to different delay signals can be obtained by using a plurality of sample-hold circuits, and then the delay position of the delay chain circuit class at the arrival time of the preset edge of the time signal is captured by the type of the sampling results corresponding to different delay signals, so as to obtain the fine count result of the time signal.

In summary, when the sample-hold circuit of the exemplary embodiment of the present disclosure is applied to a time-to-digital converter, on one hand, the sample-hold circuit determines a sampling result of a time signal under a corresponding delay signal according to a sequence of a preset edge of the delay signal and a preset edge arrival time of the time signal, which does not need to delay the time signal, and gets rid of a problem that the time signal is limited by a gate delay of a delay chain circuit, and on the other hand, the sample-hold circuit does not need to sample and hold a D trigger, which can reduce a problem that an edge trigger time is unstable and a resulting sampling and holding result is inaccurate. In addition, the sample-hold circuit of the exemplary embodiment of the present disclosure does not need to sample and hold through a capacitor, so that the sample-hold circuit can complete sample and hold relatively quickly, and the area of the sample-hold circuit is small, which can facilitate the integration of the time-to-digital converter.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

Fig. 1 is a schematic exemplary diagram showing a structure of a time-to-digital converter according to an exemplary embodiment of the present disclosure;

FIG. 2 illustrates an internal signal transmission schematic of a time-to-digital converter of an exemplary embodiment of the present disclosure;

FIG. 3 illustrates an example schematic diagram of the operational timing of a time to digital converter according to an example embodiment of the present disclosure;

FIG. 4 illustrates an exemplary schematic diagram of data processing principles of an exemplary embodiment of the present disclosure;

FIG. 5 illustrates an exemplary schematic diagram of sample-and-hold circuit principles of an exemplary embodiment of the present disclosure;

FIG. 6 illustrates an example schematic diagram of the control principles of a comparison circuit of an example embodiment of the present disclosure;

fig. 7 is a schematic diagram showing a schematic structural example of a comparison circuit of an exemplary embodiment of the present disclosure;

fig. 8 is a schematic diagram showing a structural example of an output sub-circuit according to an exemplary embodiment of the present disclosure;

fig. 9 shows an example schematic diagram of the output-terminal potential control principle of the comparison circuit of the exemplary embodiment of the present disclosure;

fig. 10 shows an example timing diagram of a transient simulation of a sample-and-hold circuit of an example embodiment of the present disclosure.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present disclosure more clear, the present disclosure is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present disclosure and are not intended to limit the present disclosure.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.

In the description of the present disclosure, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

In the description of the present disclosure, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

LiDAR (Light Detection and Ranging, liDAR), for example: the laser radar measuring system based on Direct TOF (dTOF) can measure the Time of flight of a light beam in space through a Time-to-Digital Converter (TDC) converter to calculate the object distance, and is applied to the fields of target recognition, consumer electronics, automatic driving, remote sensing, virtual Reality (VR), augmented Reality (Augmented Reality) and the like due to the advantages of high TDC response speed, high precision, large measuring range and the like.

In a ring oscillator based TDC architecture, it may obtain a minimum fine resolution by means of delay chain interpolation, which may hold the delay signal at that moment on the delay chain by means of a sample and hold circuit when a time signal, such as a start time signal start, a stop time signal stop, etc., arrives.

The inventors have found that current sample and hold circuits can sample and hold by either a capacitor or a D flip-flop. When the sampling and holding are realized through the capacitor, the area of the sampling and holding circuit is larger, the area of the capacitor which is difficult to be accurate is small, the charging and discharging speed is low, so that the sampling and holding circuit cannot accurately realize the sampling and holding, when the sampling and holding are carried out through the D trigger, the triggering time of the D trigger is unstable, the time signal inversion transmitted to the sampling and holding circuit is limited by the gate delay of the delay chain circuit (namely, the rising delay from low level to high level and the falling delay from high level to low level exist), and therefore, the D trigger is difficult to accurately sample and hold the time signal.

In view of the above problems, the exemplary embodiments of the present disclosure provide a time-to-digital converter, where a sample-and-hold circuit used in the time-to-digital converter can effectively avoid a sample-and-hold mismatch problem caused by unstable delay time of edges (rising edges and falling edges) of a time signal, so that the time signal can be accurately sampled, and the time-to-digital converter has a smaller area, thereby facilitating integration of the time-to-digital converter.

Fig. 1 shows a schematic exemplary diagram of a structure of a time-to-digital converter according to an exemplary embodiment of the present disclosure. As shown in fig. 1, a time-to-digital converter 100 provided by an exemplary embodiment of the present disclosure may include: a delay chain circuit 101, a sample hold circuit 102, and a data processing circuit 103.

As shown in fig. 1, the delay chain circuit 101 may be used to generate a predetermined clock signal. The delay chain circuit 101 may be various possible delay chain circuits 101, and the delay chain circuit 101 has multiple stages of delay signal interfaces, and each stage of delay signal interface may be used to output a delay signal. The delay chain circuit 101 may perform delay chain interpolation on one coarse count period corresponding to the coarse resolution, so as to obtain a plurality of delay signals of the target resolution, and draw the delay signals from the delay signal interfaces of the corresponding stages through the interpolation delay chain. For example: when the delay signals of M levels of fine resolutions are obtained through a delay chain interpolation mode, the delay signals of M levels of fine resolutions correspond to M levels of delay signal interfaces, and the delay signals of each level of fine resolutions can be led out through the corresponding level of delay signal interfaces.

When the number of stages of the delay signal interfaces is multiple, as shown in fig. 1, the number of the sample-hold circuits 102 is also multiple, and the number of stages of the sample-hold circuits 102 corresponds to the number of delay signal interfaces. The first input terminal of each sample-and-hold circuit 102 is used for accessing a preset edge trigger signal of a start time signal, each stage of delay signal interface is electrically connected with the second input terminal of the corresponding sample-and-hold circuit 102, and each sample-and-hold circuit 102 is electrically connected with the data processing circuit 103.

In particular, as shown in fig. 1, each stage of delay signal interface may transmit delay signals to the corresponding sample-and-hold circuit 102, where delay time periods of delay signals transmitted by different delay signal interfaces are different. The sample-hold circuits 102 may compare the preset edge of the delay signal with the preset edge arrival time of the time signal under the condition of accessing the preset edge trigger signal of the delay signal and the time signal, output sampling results of different time signals according to the comparison structure, each sample-hold circuit 102 may transmit the sampling results of the time signals corresponding to the different delay signals to the data processing circuit 103, and the data processing circuit 103 determines the time difference signal based on the sampling results of the time signals output by each sample-hold circuit 102.

In practical applications, as shown in fig. 1, the time-to-digital converter 100 of the exemplary embodiment of the present disclosure may further include a counter 104, where an input terminal of the counter 104 is electrically connected to the clock signal output interface of the delay chain circuit 101, and an output terminal of the counter 104 is electrically connected to the data processing circuit 103.

When the time signal includes a start time signal and an end time signal, the counter 104 is configured to start counting a coarse count period of the delay chain circuit 101 when a preset edge of the start time signal arrives, transmit the coarse count result to the data processing circuit 103, and the data processing circuit 103 may determine a time difference between the start time signal and the stop time signal, even if the time difference signal, based on the coarse count result, the fine count result of the start time signal, and the fine count result of the stop time signal.

In one alternative, as shown in FIG. 1, the data processing circuit 103 of an exemplary embodiment of the present disclosure may be electrically connected to a multi-stage delay signal interface. In this case, the time signal includes a start time signal and an end time signal.

As shown in fig. 1, the data processing circuit 103 is configured to obtain a fine count result of the start time signal based on the time signal sampling results output by the output terminals of the plurality of sample-and-hold circuits 102 when the preset edge trigger signal of the start time signal arrives, obtain a fine count result of the stop time signal based on the electric potential of the multi-stage delay signal interface when the preset edge trigger signal of the stop time signal arrives, and determine the time difference between the start time signal and the stop time signal based on the fine count result of the start time signal and the fine count result of the stop time signal.

Illustratively, as shown in fig. 1, the delay chain circuit 101 of the exemplary embodiment of the present disclosure is configured to start generating the preset clock signal before the preset edge of the start time signal arrives, and stop generating the preset clock signal when the preset edge of the stop time signal arrives. In this case, the delay chain circuit 101 does not need to be in an operating state all the time, and power consumption can be effectively reduced.

The inventors have found that when the preset edge of the stop time signal arrives, as shown in fig. 1, the delay chain circuit 101 stops generating the clock signal, and the potential of each stage of delay signal interface is maintained, so that by such a characteristic of the delay chain circuit 101, the data processing circuit 103 can capture the fine count result corresponding to the preset edge of the stop signal at the delay chain circuit 101 when the preset edge of the stop signal arrives.

In practical application, fig. 2 shows a schematic diagram of internal signal transmission of a time-to-digital converter according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the time-to-digital converter of the exemplary embodiments of the present disclosure may further include a preprocessing circuit 105, and an input of the preprocessing circuit 105 may be used to access the start time signal, the stop time signal, and the global reset signal. An output of the preprocessing circuit 105 is electrically connected to a control terminal of the delay chain circuit 101 and a first input of each sample-and-hold circuit 102, respectively.

As shown in fig. 2, when the output terminal of the preprocessing circuit 105 is electrically connected to the control terminal of the delay chain circuit 101, it is configured to transmit a delay start signal to the delay chain circuit 101 when the arrival of the preset edge of the global reset signal is detected before the arrival of the preset edge of the start time signal, and the delay chain circuit 101 is configured to start generating the preset clock signal under the control of the delay start signal. And when the arrival of the preset edge of the stop time signal is detected, transmitting a delay stop signal to the delay chain circuit 101, wherein the delay chain circuit 101 is further used for stopping generating the preset clock signal under the control of the delay stop signal.

As shown in fig. 2, when the output terminal of the preprocessing circuit 105 is electrically connected to the first input terminal of each sample-and-hold circuit 102, the preprocessing circuit 105 is further configured to transmit, when detecting that the preset edge of the start time signal arrives, the preset edge trigger signal of the start time signal to each sample-and-hold circuit 102, so that each sample-and-hold circuit 102 can compare the sequence of the preset edge arrival time of the start time signal and the preset edge arrival time of the delay signal, so as to output the sampling result of different start time signals according to the comparison result.

As shown in fig. 2, the preprocessing circuit 105 of the exemplary embodiment of the present disclosure may be further electrically connected to the counter 104, where the preprocessing circuit 105 is configured to transmit a count trigger signal to the counter 104 when detecting that a preset edge of the start time signal arrives, and the counter 104 is configured to start counting a coarse count period of the delay chain circuit 101 under control of the count trigger signal, obtain a coarse count result, and transmit the coarse count result to the data processing circuit 103.

In order to reduce power consumption, as shown in fig. 2, the preprocessing circuit 105 of the exemplary embodiment of the present disclosure may be electrically connected to a control terminal of the processing circuit, and is configured to transmit a data processing start signal to the data processing circuit 103 when a preset edge of the start time signal is detected, where the processing circuit may start processing the sampling result of the start time signal output by each sample hold circuit 102 and the sampling result of the stop time signal output by the multi-stage delay signal interface under the control of the data processing start signal.

As shown in fig. 1, when the data processing circuit 103 according to the exemplary embodiment of the present disclosure may include an encoder 1031 and a serial-to-parallel converter 1032, an output terminal of each sample-and-hold circuit 102 and each stage of delay signal interface are electrically connected to an input terminal of the encoder 1031, an output terminal of the encoder 1031 is electrically connected to the serial-to-parallel converter 1032, and the serial-to-parallel converter 1032 may be connected to an external clock signal.

As shown in fig. 1, the number of the encoders 1031 may be one or two, and when the number of the encoders 1031 is one, the encoder 1031 may be configured to obtain the fine count result of the start time signal based on the time signal sampling results output from the output terminals of the plurality of sample-and-hold circuits 102 when the preset edge trigger signal of the start time signal arrives, and obtain the fine count result of the stop time signal based on the electric potential of the multi-stage delay signal interface when the preset edge trigger signal of the stop time signal arrives.

As shown in fig. 1, when the number of encoders 1031 is two, the input terminal of the first encoder 1031A may be electrically connected to the output terminal of each sample-and-hold circuit 102, and the input terminal of the second encoder 1031B may be electrically connected to each stage of the delay signal interface, and the first encoder 1031A and the second encoder 1031B are electrically connected to the serial-to-parallel converter 1032. In particular, the first encoder 1031A is configured to obtain a fine count result of the start time signal based on the time signal sampling results output by the output terminals of the plurality of sample-and-hold circuits 102 when the preset edge trigger signal of the start time signal arrives, and transmit the fine count result of the start time signal to the serial-to-parallel converter 1032, and the second encoder 1031B is configured to obtain a fine count result of the stop time signal based on the electric potential of the multi-stage delay signal interface when the preset edge trigger signal of the stop time signal arrives, and transmit the fine count result of the stop time signal to the serial-to-parallel converter 1032.

In order to reduce power consumption, as shown in fig. 1, the first encoder 1031A of the exemplary embodiment of the disclosure may start to start the encoding operation when a preset edge trigger signal of the start time signal arrives, that is, obtain a fine count result of the start time signal based on the time signal sampling results output from the output terminals of the plurality of sample-and-hold circuits 102. The second encoder 1031B may start the encoding operation when the preset edge trigger signal of the stop time signal arrives, that is, acquire the fine count result of the stop time signal based on the electric potential of the multi-stage delay signal interface.

In practical applications, as shown in fig. 1, when a preset edge of the stop time signal arrives, the preprocessing circuit 105 may transmit the data processing start signal to the first encoder 1031A and the second encoder 1031B, so as to further reduce the power consumption. As for the above-described encoder 1031, after transmitting the fine count result of the start time signal and the fine count result of the stop time signal to the serial-parallel converter 1032, the serial-parallel converter 1032 may be configured to determine the time difference of the start time signal and the stop time signal based on the fine count result of the start time signal and the fine count result of the stop time signal, regardless of the number of the encoders 1031 being one or two.

As shown in fig. 1, when the delay chain circuit 101 is a ring oscillator that starts vibrating at a high level, the first encoder 1031A and the second encoder 1031B are both low-level started encoders, and the timer is a low-level started timer, fig. 3 illustrates an example schematic diagram of the operation timing of the time-to-digital converter according to the exemplary embodiment of the present disclosure. As shown in fig. 3, before the rising edge of the start time signal start arrives, the preprocessing circuit 105 may control the delay control signal R to switch from a low level to a high level when the rising edge of the global reset signal a-reset arrives, at this time, the delay control signal R acts as a delay start signal, and controls the ring oscillator to start vibrating, until the rising edge of the stop time signal stop arrives, the delay control signal R switches from a high level to a low level. At this time, the delay control signal R is used as a delay stop signal to control the ring oscillator to stop oscillating, thereby saving energy consumption.

Considering that the encoder 1031 may not be operated before the stop time signal ends, as shown in fig. 1 and 3, in order to reduce power consumption, the preprocessing circuit 105 may keep the encoding control signal R1 in a high level state before the rising edge of the stop time signal stop arrives, and may control the encoding control signal R1 to be turned from a high level to a low level when the rising edge of the stop time signal stop arrives. At this time, the encoding control signal R1 may be used as a data processing start signal or an encoding start signal, and controls the first encoder 1031A to start encoding the sampling result of the start time signal output by each sample-and-hold circuit 102, and controls the second encoder 1031B to start encoding the sampling result of the stop time signal output by each stage of delay signal interface.

To count the coarse count result, as shown in fig. 1 and 3, the preprocessing circuit 105 of the exemplary embodiment of the present disclosure may keep the local reset signal R2 in a high level state before the rising edge of the start time signal start arrives, so that the counter 104 is in a non-operating state, and when the rising edge of the start time signal start arrives, control the local reset signal R2 to turn from a high level to a low level, and start controlling the counter 104 as a count trigger signal to count the coarse count period of the ring oscillator, thereby obtaining the coarse count result. Considering that the ring oscillator stops oscillating when the rising edge of the stop time signal stop arrives, the coarse count period of the ring oscillator is not increasing when the rising edge of the stop time signal stop arrives, and thus, although the preprocessing circuit 105 does not control the counter 104 to stop counting the coarse count period of the ring oscillator by the local reset signal R2, the counter 104 can accurately acquire the coarse count result of the ring oscillator.

As shown in fig. 1 and 3, when the sample-and-hold circuit 102 of the exemplary embodiment of the present disclosure is reset at a high level, the preprocessing circuit 105 may maintain the local reset signal R2 in a high level state when the rising edge of the global reset signal a-reset arrives before the rising edge of the start time signal start arrives, to reset the sample-and-hold circuit 102 in a high level state.

As shown in fig. 1 and 3, when the sample-and-hold circuit 102 of the exemplary embodiment of the present disclosure arrives at the rising edge of the start time signal, the preprocessing circuit 105 may ensure that the trigger control signal R3 goes from the low level to the high level. At this time, the trigger control signal R3 may indicate the rising edge of the start time signal as a rising edge trigger signal of the start time signal.

In an alternative, to achieve remote measurements, as shown in fig. 1, the delay chain circuit 101 of an exemplary embodiment of the present disclosure may be a ring delay circuit, which may include a plurality of delay cells, which may constitute a ring circuit. The delay chain circuit 101 can continuously generate a preset clock signal in a smaller delay unit, so that the linearity of the time-to-digital converter is improved, and the remote measurement time difference is achieved.

The above-mentioned ring delay circuit may be a ring oscillator, where each delay unit may be an inverter, and the number of delay units may be an odd number, for example. The output end of each delay unit can be introduced with a delay signal interface. In this case, the coarse count period of the ring delay circuit may be one oscillation period of the ring delay circuit. The delay time length of each stage of delay unit included in the annular delay circuit is T _delay The number of delay units is M, and the oscillation period or coarse count period (hereinafter referred to as coarse count period) of the ring oscillator can be equal to MT _delay 。

To facilitate adjusting the clock frequency of the ring delay circuit, as shown in fig. 1, the time-to-digital converter of the exemplary embodiments of the present disclosure may further include a clock frequency adjusting circuit 106, which may be composed of a PMOS transistor, where a source of the PMOS transistor is connected to the power supply signal and a source is connected to the clock signal input interface of the ring delay circuit.

For example, when the delay chain circuit is a ring delay circuit, the ring delay circuit includes M stages of delay units, and if the clock frequency of the preset clock signal generated by the ring delay circuit is f, the period corresponding to the clock frequency may be a coarse count period. In this case, the fine resolution of the preset clock signal is 1/Mf.

To ensure sample-and-hold accuracy, exemplary embodiments of the present disclosure preset the clock frequency f of the clock signal to be greater than the preset frequency f ₀ The preset frequency may be set according to actual conditions. For example: for the 16-stage delay signal interface, the coarse count frequency can be 625MHz, the corresponding coarse count period is 1.6ns, and the fine resolution is 100ps. In this case, the sample-hold accuracy of the sample-hold circuit may reach 2ps or even 1ps or less.

As shown in fig. 1, when the data processing circuit 103 includes an encoder 1031 and a serial-to-parallel converter 1032, the encoder 1031 may receive a sampling result of a start time signal represented by a 16-bit thermally encoded signal, each of which is transmitted by a corresponding sample-and-hold circuit 102 or a corresponding stage delay signal interface. The following description will take the fine count result determining process of the start time signal as an example, and it should be understood that the fine count result of the end time signal may refer to the following, and will not be repeated.

When the preset edge arrival time of the start signal is earlier than the preset edge arrival time of the delay signal, the sampling result of the start time signal is represented by 1, whereas when the preset edge arrival time of the start signal is later than the preset edge arrival time of the delay signal, the sampling result of the start time signal is represented by 0. In this case, the 16-bit thermal encoding signal of the sampling result of the start time signal is a binarized encoding signal, and as long as the transition position from 1 to 0 in the 16-bit thermal encoding signal is queried, the position in the delay chain circuit corresponding to the arrival time of the preset edge of the start signal can be found, so that the fine counting result of the start time signal is obtained, and the fine counting result of the start time signal can be used as 4-bit binary data. For example: when the 16-bit thermal encoded signal of the start time signal is 111111110000000, its corresponding 4-bit binary data is 1000.

The following description will take the rough count frequency of the ring oscillator as 625MHz, and the corresponding rough count period t=1.6ns as an example with reference to the accompanying drawings. It should be understood that the preset edge of the start time signal and the preset edge of the stop time signal in the exemplary embodiments of the present disclosure may be both rising edges and may also be both falling edges, and may be specifically designed in combination with the actual situation of the circuit structure and the device type.

Fig. 4 shows an exemplary schematic diagram of the data processing principle of an exemplary embodiment of the present disclosure. As shown in fig. 4, the counter 104 may perform coarse counting on the preset constant signal of the ring oscillator to obtain a coarse counting period number m, where the corresponding coarse counting duration tc=m×t=1.6 m.

As shown in fig. 4, the sample-and-hold circuit can hold the position in the fine counter of the ring delay circuit corresponding to the rising edge of the start time signal strat, so as to obtain the fine resolution result of the start time signal, and the stable potential output by the 16-stage delay signal interface can obtain the position in the fine counter of the ring delay circuit corresponding to the rising edge of the stop signal, so as to obtain the fine resolution result of the stop time signal.

When the 4-bit two-level system data of the fine resolution result of the start time signal is 1000, the corresponding rising edge arrival time of the start time signal corresponds to the 8 th delay signal interface of the fine resolution result, and the fine resolution time t1=8x100ps=0.8ns of the start time signal. When the 4-bit two-level system data of the fine resolution result of the stop time signal is 1010, the corresponding rising edge arrival time of the stop time signal corresponds to the 10 th delay signal interface of the fine resolution result, and the fine resolution time length t1=10×100ps=1 ns of the stop time signal. In this case, when tc=1.6m, the time difference Δt=1ns+0.8ns+1.6m=1.8ns+1.6m between the start time signal and the stop time signal.

The exemplary embodiments of the present disclosure also disclose a sample-and-hold circuit that may be applied to the time-to-digital converter of the exemplary embodiments of the present disclosure, and that may sample-and-hold a time signal such as a start time signal, a stop time signal, and the like.

Fig. 5 shows an exemplary schematic diagram of a sample-and-hold circuit principle of an exemplary embodiment of the present disclosure. As shown in fig. 5, the sample-and-hold circuit 200 of the exemplary embodiment of the present disclosure may include: a comparison circuit 201 and a reset circuit 202.

As shown in fig. 5, the first control terminal of the comparison circuit is used for accessing the first control signal Pulse-a, the second control terminal of the comparison circuit is used for accessing the second control signal Pulse-B, the control terminal of the reset circuit 202 is used for accessing the local reset signal B-reset, the input terminal of the comparison circuit is electrically connected with the power supply terminal VDD, the output terminal Out of the comparison circuit 201 can be used as the output terminal of the sample-and-hold circuit, the output terminal Out of the comparison circuit 201 is electrically connected with the input terminal of the reset circuit 202, and the output terminal of the reset circuit 202 is electrically connected with the ground terminal.

As shown in fig. 5, the reset circuit 202 may be configured to reset the comparison circuit 201 using the local reset signal B-reset before the preset edge of the time signal arrives. At this time, since the output terminal of the comparison circuit 201 is electrically connected to the input terminal of the reset circuit 202, the output terminal of the reset circuit 202 is electrically connected to the ground terminal, and thus, the reset circuit 202 can control the potentials of the input terminal and the output terminal of the reset circuit to be the same under the control of the local reset signal B-reset, so that the potential of the output terminal of the comparison circuit is pulled to zero potential, thereby realizing the reset of the comparison circuit.

Illustratively, when the sample-and-hold circuit of the exemplary embodiments of the present disclosure is applied to a time-to-digital converter, as shown in fig. 2 and 5, the control terminal of the reset circuit 202 may be electrically connected to the output terminal of the preprocessing circuit 105. When the reset circuit 202 is a high-potential triggered reset circuit, since the preprocessing circuit 105 can keep the local reset signal R2 in a high-level state until the rising edge of the start time signal start arrives when the rising edge of the global reset signal a-reset arrives. In this case, when the rising edge of the global reset signal a-reset arrives, the local reset signal B-reset may be the local reset signal R2 generated by the preprocessing circuit, so that the reset circuit may pull the output terminal potential of the comparison circuit to the zero potential under the control of the local reset signal B-reset in a period between the rising edge arrival time of the global reset signal a-reset and the rising edge arrival time of the start time signal start, thereby implementing the reset of the comparison circuit.

As shown in fig. 5, the comparison circuit 201 is configured to output a first sampling result of the time signal based on the first control signal Pulse-a when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, and output a second sampling result of the time signal based on the second control signal Pulse-B when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal.

In summary, when the sample-hold circuit of the exemplary embodiment of the present disclosure is applied to a time-to-digital converter, on one hand, the sample-hold circuit determines a sampling result of a time signal under a corresponding delay signal according to a sequence of a preset edge of the delay signal and a preset edge arrival time of the time signal, which does not need to delay the time signal, and gets rid of a problem that the time signal is limited by a gate delay of the delay chain circuit, and on the other hand, the sample-hold circuit does not need to sample and hold a D trigger, which can reduce an unstable triggering timing of edge triggering of the D trigger, and thus, the sample-hold result is inaccurate. In addition, the sample-hold circuit of the exemplary embodiment of the present disclosure does not need to sample and hold through a capacitor, so that the sample-hold circuit can complete sample and hold relatively quickly, and the area of the sample-hold circuit is small, which can facilitate the integration of the time-to-digital converter.

Fig. 6 shows an exemplary schematic diagram of the control principle of the comparison circuit of the exemplary embodiment of the present disclosure. As shown in fig. 6, the sample-and-hold circuit of the exemplary embodiment of the present disclosure further includes a first trigger control circuit 203A and a second trigger control circuit 203B, wherein an input end of the first trigger control circuit 203A is used for accessing a preset edge trigger signal of a time signal, an output end of the first trigger control circuit 203A is electrically connected to a first control end of the comparison circuit 201, an input end of the second trigger control circuit 203B is used for accessing a delay signal, and an output end of the second trigger control circuit 203B is electrically connected to a second control end of the comparison circuit 201. It can be seen that the input of the first trigger control circuit 203A can be seen as a first input of the sample-and-hold circuit, while the input of the second trigger control circuit 203B can be seen as a second input of the sample-and-hold circuit.

As shown in fig. 6, the first trigger control circuit 203A is configured to transmit the first control signal to the first control terminal of the comparison circuit 201 based on the preset edge trigger signal of the time signal when the preset edge of the time signal arrives. When the sample-and-hold circuit of the exemplary embodiments of the present disclosure is applied to a time-to-digital converter, the preprocessing circuit may be electrically connected to an input terminal of the first trigger control circuit 203A.

As shown in fig. 6, the second trigger control circuit 203B is configured to transmit the second control signal to the second control terminal of the comparison circuit 201 based on the delay signal when a preset edge of the delay signal arrives. When the sample-and-hold circuit of the exemplary embodiment of the present disclosure is applied to a time-to-digital converter, as shown in fig. 1 and 6, the delay signal interface of the delay chain circuit 101 may be electrically connected to the input terminal of the second trigger control circuit 203B to transmit the delay signal to the input terminal of the first trigger control circuit 203A.

In practical applications, as shown in fig. 6, the first trigger control circuit 203A and the second trigger control circuit 203B may have the same circuit configuration or may have different circuit configurations. When the circuit structures of the first trigger control circuit 203A and the second trigger control circuit 203B are the same, as illustrated in fig. 7, the first trigger control circuit 203A and the second trigger control circuit 203B of the exemplary embodiment of the disclosure each include an inverter and a nand gate, an input terminal of the inverter is used for accessing the local reset signal, and an output terminal of the inverter is electrically connected to the first input terminal of the nand gate.

As shown in fig. 6, for the first trigger control circuit 203A, a second input terminal a of the nand gate included therein may be used for accessing a preset edge trigger signal of a time signal, and an output terminal of the nand gate is electrically connected to a first control terminal of the comparison circuit 201. When the sample-and-hold circuit of the exemplary embodiment of the present disclosure is applied to a time-to-digital converter, as shown in fig. 2 and 6, the output terminal of the preprocessing circuit 105 may be electrically connected to the input terminal of the inverter and the second input terminal a of the nand gate, respectively.

When the first control end of the comparison circuit is triggered by a low level, the local reset signal is a high level signal when the comparison circuit is reset by the reset circuit, the local reset signal is a low level signal when the preset edge of the time signal arrives, the preset edge trigger signal of the time signal is a low level signal before the preset edge of the time signal arrives, and the preset edge trigger signal of the time signal is a high level signal when the preset edge of the time signal arrives.

In specific implementation, when the reset circuit resets the comparison circuit, the local reset signal can transmit a low-level signal to the nand gate after being inverted by the inverter, and meanwhile, a preset edge trigger signal of a time signal input to the nand gate is low-level, so that the nand gate can input a high-level signal to the first control end of the comparator when the reset circuit resets the comparison circuit, and the first control end of the comparator is in a non-trigger state.

When the preset edge of the time signal arrives, the local reset signal can transmit a high-level signal to the NAND gate after being inverted by the inverter, and meanwhile, the preset edge trigger signal of the time signal input to the NAND gate is high-level, so that the NAND gate can input a low-level signal to the first control end of the comparator when the preset edge of the time signal arrives, the first control end of the comparator is in a trigger state, and the power supply signal enters the comparator.

As shown in fig. 6, for the second trigger control circuit 203B, the second input terminal B of the nand gate is used for accessing the delay signal, and the output terminal of the nand gate included in the second trigger control circuit 203B is electrically connected to the second control terminal of the comparison circuit 201. When the sample-and-hold circuit of the exemplary embodiment of the present disclosure is applied to a time-to-digital converter, as shown in fig. 2 and 6, an output terminal of the preprocessing circuit may be electrically connected to an input terminal of an inverter, and a delay signal interface of the delay chain circuit 101 may be electrically connected to a second input terminal of the nand gate.

When the first control end of the comparison circuit is triggered by a low level, the local reset signal is a high level signal when the comparison circuit is reset by the reset circuit, and is a low level signal when the preset edge of the time signal comes. Based on this, when the reset circuit resets the comparison circuit, the local reset signal is inverted by the inverter, and then a low-level signal can be transmitted to the nand gate. Meanwhile, no matter whether the preset edge of the delay signal input into the NAND gate comes or not, the NAND gate can input a high-level signal to the second control end of the comparator when the comparison circuit is reset by the reset circuit.

When the preset edge of the delay signal arrives, the local reset signal can transmit a high-level signal to the NAND gate after being inverted by the inverter, and meanwhile, the preset edge trigger signal of the delay signal input to the NAND gate is high-level, so that the NAND gate can input a low-level signal to the second control end of the comparator when the preset edge of the delay signal arrives, the second control end of the comparator is in a trigger state, and the power supply signal enters the comparator.

In an alternative manner, fig. 7 shows a schematic structural example schematic diagram of a comparison circuit of an exemplary embodiment of the present disclosure. As shown in fig. 7, the comparison circuit 201 of the exemplary embodiment of the present disclosure may include a first transistor M1, a second transistor M2, a potential adjustment sub-circuit 2011, and an output sub-circuit 2012. The control electrode of the first transistor M1 is used for accessing the first control signal Pulse-A, and the control electrode of the second transistor M2 is used for accessing the second control signal Pulse-B.

As shown in fig. 7, the first electrode of the first transistor M1 and the first electrode of the second transistor M2 are electrically connected to the power supply terminal VDD, the second electrode of the first transistor M1 and the second electrode of the second transistor M2 are electrically connected to the input terminal of the output sub-circuit 2012, the potential adjusting sub-circuit 2011 is electrically connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2, respectively, and the output terminal of the output sub-circuit 2012 is electrically connected to the input terminal of the reset circuit 202 shown in fig. 6.

For example, as shown in fig. 7, when the comparator is used for determining the sequence of the arrival time of the falling edge of the time signal and the arrival time of the falling edge of the delay signal, the first transistor M1 and the second transistor M2 may be NMOS transistors that are triggered to be turned on at a high level, and when the comparator is used for determining the sequence of the arrival time of the rising edge of the time signal and the arrival time of the rising edge of the delay signal, the first transistor M1 and the second transistor M2 may be PMOS transistors that are triggered to be turned on at a low level.

When the preset edge arrival time of the time signal is earlier than the preset edge arrival time of the delay signal, as shown in fig. 7, the second electrode potential of the first transistor M1 is higher than the second electrode potential of the second transistor M2, and when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal, the second electrode potential of the first transistor M1 is lower than the second electrode potential of the second transistor M2.

As illustrated in fig. 7, the potential adjusting sub-circuit 2011 of the exemplary embodiment of the present disclosure may include a third transistor M3, a first electrode of the third transistor M3 is electrically connected to a second electrode of the first transistor M1, a second electrode of the third transistor M3 is electrically connected to a second electrode of the second transistor M2, and the third transistor M3 is in a normally-on state. I.e. the third transistor M3 remains on all the time. For example: the third transistor M3 is a PMOS transistor with a low-level conductive state, and the control electrode of the third transistor M3 is grounded, so that the third transistor M3 can be always kept in a conductive state.

As shown in fig. 7, if the arrival time of the preset edge of the time signal is earlier than the arrival time of the preset edge of the delay signal, the first transistor M1 may be turned on under the control of the first control signal Pulse-a, and the preset edge of the delay signal is not at this time, so that the second transistor M2 is maintained in an off state under the control of the second control signal Pulse-B, and thus, the power signal may be transmitted to the first node a at the second electrode of the first transistor M1 through the first transistor M1 such that the potential of the first node a is equal to the potential vdd of the power signal. Meanwhile, the third transistor M3 is in a normal on state, when the electric signal of the first node a passes through the third transistor M3, there is a certain voltage drop, so that the electric potential of the first node a is slightly higher than the electric potential of the second node b, and then the output sub-circuit 2012 is ensured to output the first sampling result of the preset edge of the time signal based on the electric potential of the first node a and the electric potential of the second node b.

If the arrival time of the preset edge of the time signal is later than the arrival time of the preset edge of the delay signal, as shown in fig. 7, the second transistor M2 may be turned on under the control of the second control signal Pulse-B, and the preset edge of the time signal is not arrived at this moment, so that the first transistor M1 is kept in an off state under the control of the first control signal Pulse-a, and thus, the power signal may be transmitted to the second node B at the second electrode of the second transistor M2 through the second transistor M2, so that the potential of the first node B is vdd. Meanwhile, the third transistor M3 is in a normal on state, when the electric signal of the second node b passes through the third transistor M3, there is a certain voltage drop, so that the electric potential of the second node b is slightly higher than the electric potential of the first node a, and then the output sub-circuit 2012 is ensured to output the second sampling result of the preset edge of the time signal based on the electric potential of the first node a and the electric potential of the second node b.

The sampling hold circuit of the exemplary embodiment of the disclosure has symmetrical structure, presents an arbiter structure, and can ensure the accuracy of the output sampling result. Fig. 8 shows a schematic diagram of a structural example of an output sub-circuit of an exemplary embodiment of the present disclosure. As shown in fig. 8, the output subcircuit 2012 of the exemplary embodiment of the present disclosure may include: the fourth transistor M4 and the fifth transistor M5 may be NMOS transistors triggered to be turned on at a high level, or PMOS transistors triggered to be turned on at a low level.

As shown in fig. 8, the first electrode of the fourth transistor M4 is electrically connected to the second electrode of the first transistor M1, the second electrode of the fourth transistor M4 is electrically connected to the input terminal of the reset circuit 202, the first electrode of the fifth transistor M5 is electrically connected to the second electrode of the second transistor M2, the second electrode of the fifth transistor M5 is electrically connected to the input terminal of the reset circuit, the control electrode of the fourth transistor M4 is electrically connected to the second electrode of the fifth transistor M5, and the control electrode of the fifth transistor M5 is electrically connected to the second electrode of the fourth transistor M4. At this time, the second electrode of the fourth transistor M4 and the second electrode of the fifth transistor M5 may each output a sampling result of the time signal.

As shown in fig. 8, when the output terminals of the plurality of sample-and-hold circuits are all electrically connected to the input terminal of the data processing circuit, the second electrode of the fourth transistor included in each sample-and-hold circuit may be electrically connected to the input terminal of the data processing circuit as the first output terminal Out-a of the sample-and-hold circuit, or the second electrode of the fifth transistor included in each sample-and-hold circuit may be electrically connected to the input terminal of the data processing circuit as the second output terminal Out-B of the sample-and-hold circuit, so as to ensure that the sampling results of the time signals output by each sample-and-hold circuit are compared with each other in the same dimension.

In practical application, as shown in fig. 8, the second electrode of the first transistor M1 and the first electrode of the fourth transistor M4 are both connected to the first node a, and the second electrode of the second transistor M2 and the first electrode of the fifth transistor M5 are both connected to the second node b. Meanwhile, the second electrode of the fourth transistor M4 and the input terminal of the reset circuit 202 are both connected to the third node c, and the second electrode of the fifth transistor M5 and the input terminal of the reset circuit are both connected to the fourth node d.

As shown in fig. 8, considering that the output terminal of the reset circuit 202 is grounded, the reset circuit may pull the potentials of the third node c and the fourth node d to zero potential under the control of the reset signal when the reset circuit 202 resets the comparison circuit. At this time, the fourth transistor M4 and the fifth transistor M5 may be designed as PMOS transistors, and when the potentials of the third node c and the fourth node d are pulled to zero potential by the reset circuit, the third transistor M3 and the fourth transistor M4 are turned on, so that the potentials of the first node a and the second node b are also pulled to zero potential, thereby achieving the overall reset of the comparison circuit.

As shown in fig. 8, when the arrival time of the preset edge of the time signal is earlier than or equal to the arrival time of the preset edge of the time signal, the reset circuit 202 has reset the comparison circuit as a whole so that the potential of the third node c and the potential of the fourth node d are both zero, and therefore, when the preset edge of the time signal arrives, the fourth transistor M4 and the fifth transistor M5 are in the on state. In this case, the power signal may reach the third node c through the first transistor M1 and the fourth transistor M4, the potential of the third node c is rapidly pulled up to vdd, and since the second electrode of the fourth transistor M4 is electrically connected to the gate electrode of the fifth transistor M5 and the fifth transistor M5 is a low-level on, high-level off transistor, the fifth transistor M5 is turned off under the control of the high-level signal of the third node c when the potential of the third node c is pulled up to vdd.

As shown in fig. 8, when the arrival time of the preset edge of the time signal is later than the arrival time of the preset edge of the delay signal, the reset circuit has reset the comparison circuit as a whole so that the potential of the third node c and the potential of the fourth node d are both zero, and therefore, when the preset edge of the delay signal arrives, the fourth transistor M4 and the fifth transistor M5 are in the on state. In this case, the power signal may reach the fourth node through the second transistor M2 and the fifth transistor M5, the potential of the fourth node d is rapidly pulled up to vdd, and since the second electrode of the fourth transistor M4 is electrically connected to the gate electrode of the fifth transistor M5 and the fifth transistor M5 is a transistor of which low level is on and high level is off, the fourth transistor M4 is turned off under the control of the high level signal of the fourth node when the potential of the fourth node d is pulled up to high level.

As shown in fig. 8, the comparison circuit of the exemplary embodiment of the present disclosure further includes a first potential control sub-circuit 203A and a second potential control sub-circuit 203B. The control terminal of the first potential control sub-circuit 203A is electrically connected to the input terminal of the first potential control sub-circuit 203A of the fifth transistor M5 and the second electrode of the fourth transistor M4, the output terminal of the first potential control sub-circuit 203A is grounded, and the control terminal of the second potential control sub-circuit 203B is electrically connected to the second electrode of the fourth transistor M4. An input terminal of the second potential control sub-circuit 203B is electrically connected to the second electrode of the fifth transistor M5, and an output terminal of the second potential control sub-circuit 203B is grounded.

As shown in fig. 8, when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, the first potential control sub-circuit 203A is configured to pull up the second electrode potential of the fourth transistor M4 to the target potential, and the second potential control sub-circuit 203B is configured to pull down the second electrode potential of the fifth transistor M5 to the zero potential.

Fig. 9 shows an exemplary schematic diagram of the principle of output-terminal potential control of the comparison circuit of the exemplary embodiment of the present disclosure. As shown in fig. 9, the first potential control sub-circuit includes a sixth transistor M6, the second potential control sub-circuit includes a seventh transistor M7, and both the sixth transistor M6 and the seventh transistor M7 are NMOS transistors with high-level on and low-level off.

As shown in fig. 9, when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, the potential of the third node c is relatively high, and the seventh transistor M7 may be controlled to be turned on, so that the seventh transistor M7 pulls the potential of the fourth node d to zero potential. In this case, the sixth transistor M6 connected to the fourth node d may be turned off, thereby ensuring that the potential of the third node c is maintained at vdd.

As shown in fig. 9, when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal, the potential of the fourth node d is relatively high, and the sixth transistor M6 may be controlled to be turned on, so that the sixth transistor M6 pulls the potential of the third node c to zero potential. In this case, the seventh transistor M7 connected to the third node c may be turned off, thereby ensuring that the potential of the fourth node d is maintained at vdd.

As shown in fig. 9, the comparison circuit of the exemplary embodiment of the present disclosure may further include a first buffer and a second buffer 204B, the second electrode of the fourth transistor M4 is electrically connected to the first buffer 204A, and the second electrode of the fifth transistor M5 is electrically connected to the second buffer 204B. The output of the first buffer 204A or the output of the second buffer 204B may be used as the final output of the sample-and-hold circuit. The first buffer 204A and the second buffer 204B can hold circuits, ensure data accuracy, and prevent distortion.

As shown in fig. 9, when a plurality of sample-and-hold circuits are all connected to the processing circuit, the output terminal of the first buffer 204A included in each sample-and-hold circuit may be electrically connected to the input terminal of the processing circuit as the first output terminal Out-a of the sample-and-hold circuit, or the output terminal of the second buffer 204B included in each sample-and-hold circuit may be electrically connected to the input terminal of the processing circuit as the second output terminal Out-B of the sample-and-hold circuit, so as to ensure that the sampling results of the time signals output by the respective sample-and-hold circuits are compared with each other in the same dimension.

As shown in fig. 9, the number of the reset circuits of the exemplary embodiment of the present disclosure may be one or more, and each reset circuit may include a first reset sub-circuit and a second reset sub-circuit, where the control terminal of the first reset sub-circuit and the control terminal of the second reset sub-circuit are used to access a local reset signal, and the local reset signal is provided by the preprocessing circuit, and thus, the control terminal of the first reset sub-circuit and the control terminal of the second reset sub-circuit are electrically connected to the output terminal of the preprocessing circuit.

The input end of the first reset sub-circuit is electrically connected with the second electrode of the fourth transistor, the output end of the first reset sub-circuit is grounded, the input end of the second reset sub-circuit is electrically connected with the second electrode of the fifth transistor, and the output end of the second reset sub-circuit is grounded. It should be understood that the first reset sub-circuit and the second reset sub-circuit may be PMOS transistors or NMOS transistors.

For example, when the number of the reset circuits is two, as shown in fig. 9, the first reset sub-circuit included in the first reset circuit may be the eighth transistor M8, the second reset sub-circuit may be the ninth transistor M9, the first reset sub-circuit included in the second reset circuit may be the tenth transistor M10, and the second reset sub-circuit may be the eleventh transistor M11.

When the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are NMOS transistors, the reset signal is a high signal before the preset edge of the time signal arrives, which can control the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 to be turned on. In this case, the eighth and tenth transistors M8 and M10 grounded may pull the potentials of the first and third nodes a and c to zero potential, and the ninth and eleventh transistors M9 and M11 grounded may pull the potentials of the second and fourth nodes b and c to zero potential.

Fig. 10 shows an example timing diagram of a transient simulation of a sample-and-hold circuit of an example embodiment of the present disclosure. As shown in fig. 10, the preset edge trigger signal of the time signal output by the second input terminal a of the nand gate included in the first trigger control circuit is a high level signal triggered when the preset edge of the time signal arrives, and the preset edge of the delay signal output by the second input terminal B of the nand gate included in the second trigger control circuit may also be a high level signal.

As can be seen from fig. 10, for the 16-stage delay signal interface, the coarse count frequency may be 625MHz, the corresponding coarse count period is 1.6ns, the fine resolution is 100ps, and the preset edge arrival time of the time signal is 2ps earlier than the preset edge arrival time of the delay signal. At the arrival time of the preset edge of the time signal, the first control signal is switched from the high level to the low level preferentially than the second control signal, so that the third node c presents a potential rising trend, and the fourth node presents a potential falling trend. Meanwhile, when the third node c is electrically connected to the first buffer 204A, the output terminal Out-a of the first buffer 204A serves as an output terminal of the sample-and-hold circuit, and exhibits a high potential steady state.

Therefore, the high potential stable state of the output end of the comparator included in the sample hold circuit of the exemplary embodiment of the disclosure can represent the sequence before and after the preset edge of the comparison time signal and the preset edge of the delay signal, and the sample hold precision can reach 2ps, so that the purpose of accurate sample hold is achieved.

In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A sample-and-hold circuit, comprising: the device comprises a comparison circuit and a reset circuit, wherein a first control end of the comparison circuit is used for being connected with a first control signal, a second control end of the comparison circuit is used for being connected with a second control signal, a control end of the reset circuit is used for being connected with a local reset signal, an input end of the comparison circuit is electrically connected with a power supply end, an output end of the comparison circuit is electrically connected with an input end of the reset circuit, and an output end of the reset circuit is electrically connected with a grounding end;

the reset circuit is used for resetting the comparison circuit by utilizing the local reset signal before the preset edge of the time signal arrives; the comparison circuit is used for outputting a first sampling result of the time signal based on the first control signal when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, and outputting a second sampling result of the time signal based on the second control signal when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal.

2. The sample-and-hold circuit of claim 1, further comprising a first trigger control circuit and a second trigger control circuit, wherein an input end of the first trigger control circuit is used for accessing a preset edge trigger signal of a time signal, an output end of the first trigger control circuit is electrically connected with a first control end of the comparison circuit, an input end of the second trigger control circuit is used for accessing the delay signal, and an output end of the second trigger control circuit is electrically connected with a second control end of the comparison circuit;

the first trigger control circuit is used for transmitting the first control signal to a first control end of the comparison circuit based on a preset edge trigger signal of the time signal when the preset edge of the time signal arrives;

the second trigger control circuit is used for transmitting the second control signal to a second control end of the comparison circuit based on the delay signal when a preset edge of the delay signal arrives.

3. The sample-and-hold circuit of claim 2, wherein the first trigger control circuit and the second trigger control circuit each comprise an inverter and a nand gate, wherein an input terminal of the inverter is used for accessing the local reset signal, and an output terminal of the inverter is electrically connected with a first input terminal of the nand gate;

The second input end of the NAND gate included in the first trigger control circuit is used for accessing the preset edge trigger signal of the time signal, the output end of the NAND gate included in the first trigger control circuit is electrically connected with the first control end of the comparison circuit, the second input end of the NAND gate included in the second trigger control circuit is used for accessing the delay signal, and the output end of the NAND gate included in the second trigger control circuit is electrically connected with the second control end of the comparison circuit.

4. The sample-and-hold circuit of claim 1, wherein the comparison circuit comprises: the circuit comprises a first transistor, a second transistor, a potential regulating sub-circuit and an output sub-circuit, wherein the control electrode of the first transistor is used for being connected with a first control signal, and the control electrode of the second transistor is used for being connected with a second control signal;

the first electrode of the first transistor and the first electrode of the second transistor are electrically connected with the power supply end, the second electrode of the first transistor and the second electrode of the second transistor are both connected with the input end of the output sub-circuit, the potential regulating sub-circuit is electrically connected with the second electrode of the first transistor and the second electrode of the second transistor respectively, and the output end of the output sub-circuit is electrically connected with the input end of the reset circuit;

When the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, the second electrode potential of the first transistor is higher than the second electrode potential of the second transistor, and when the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal, the second electrode potential of the first transistor is lower than the second electrode potential of the second transistor.

5. The sample-and-hold circuit of claim 4, wherein the potential regulating subcircuit comprises a third transistor having a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the second electrode of the second transistor, the third transistor being in a normally-on state.

6. The sample-and-hold circuit of claim 4, wherein the output sub-circuit comprises: a fourth transistor and a fifth transistor;

a first electrode of the fourth transistor is electrically connected with a second electrode of the first transistor, a second electrode of the fourth transistor is electrically connected with an input end of the reset circuit, and a control electrode of the fourth transistor is electrically connected with a second electrode of the fifth transistor;

The first electrode of the fifth transistor is electrically connected with the second electrode of the second transistor, the second electrode of the fifth transistor is electrically connected with the input end of the reset circuit, and the control electrode of the fifth transistor is electrically connected with the second electrode of the fourth transistor.

7. The sample-and-hold circuit of claim 6, wherein the comparison circuit further comprises a first potential control sub-circuit and a second potential control sub-circuit; the control end of the first potential control sub-circuit is electrically connected with the second electrode of the fifth transistor, the input end of the first potential control sub-circuit is electrically connected with the second electrode of the fourth transistor, the output end of the first potential control sub-circuit is grounded, the input end of the second potential control sub-circuit is electrically connected with the second electrode of the fifth transistor, the output end of the second potential control sub-circuit is grounded, and the control end of the second potential control sub-circuit is electrically connected with the second electrode of the fourth transistor;

when the preset edge arrival time of the time signal is earlier than or equal to the preset edge arrival time of the delay signal, the sixth transistor is used for pulling up the second electrode potential of the fourth transistor to the target potential, and the seventh transistor is used for pulling down the second electrode potential of the fifth transistor to the zero potential;

When the preset edge arrival time of the time signal is later than the preset edge arrival time of the delay signal, the sixth transistor is used for pulling down the second electrode potential of the fourth transistor to zero potential, the seventh transistor is used for pulling up the second electrode potential of the fifth transistor to the target potential, and the target potential is equal to the voltage output by the power supply terminal.

8. The sample-and-hold circuit of claim 6, wherein the reset circuit comprises a first reset sub-circuit and a second reset sub-circuit, the control terminal of the first reset sub-circuit and the control terminal of the second reset sub-circuit being used to access the local reset signal;

the input end of the first reset sub-circuit is electrically connected with the second electrode of the fourth transistor respectively, the output end of the first reset sub-circuit is grounded, the input end of the second reset sub-circuit is electrically connected with the second electrode of the fifth transistor, and the output end of the second reset sub-circuit is grounded.

9. A time-to-digital converter, comprising: the delay chain circuit is used for generating a preset clock signal and is provided with a multi-stage delay signal interface;

The time-to-digital converter further comprises a plurality of sample-and-hold circuits according to any one of claims 1 to 8, wherein a first input end of each sample-and-hold circuit is used for accessing a preset edge trigger signal of a start time signal, each stage of delay signal interface is electrically connected with a second input end of the corresponding sample-and-hold circuit, and each sample-and-hold circuit is electrically connected with the data processing circuit.

10. The time-to-digital converter of claim 9, wherein the delay chain circuit is a ring delay circuit comprising M stages of delay cells, the clock frequency f of the predetermined clock signal being greater than the predetermined frequency f ₀ The fine resolution of the preset clock signal is 1/Mf.

11. The time to digital converter of claim 9, wherein the data processing circuit is electrically coupled to a multi-stage delay signal interface, the time signal comprising a start time signal and an end time signal;

the data processing circuit is used for acquiring a fine count result of the start time signal based on time signal sampling results output by the output ends of the sampling and holding circuits when a preset edge trigger signal of the start time signal arrives, acquiring a fine count result of the stop time signal based on the electric potential of the multi-stage delay signal interface when the preset edge trigger signal of the stop time signal arrives, and determining the time difference of the start time signal and the stop time signal based on the fine count result of the start time signal and the fine count result of the stop time signal.

12. The time to digital converter of claim 11, wherein the delay chain circuit is configured to start generating the preset clock signal when a preset edge of the global reset signal arrives, and stop generating the preset clock signal when a preset edge trigger signal of the stop time signal arrives.

13. The time to digital converter of claim 11, further comprising a preprocessing circuit having inputs for accessing a start time signal, a stop time signal, and a global reset signal, the output of the preprocessing circuit being electrically connected to the control terminal of the delay chain circuit and the first input of each of the sample and hold circuits, respectively;

the preprocessing circuit is used for transmitting a delay starting signal to the delay chain circuit when the arrival of the preset edge of the global reset signal is detected before the arrival of the preset edge of the start time signal; and when the arrival of the preset edge of the start time signal is detected, transmitting a preset edge trigger signal of the start time signal to each sampling hold circuit, and when the arrival of the preset edge of the stop time signal is detected, transmitting a delay stop signal to the delay chain circuit.