CN117544139A - Frequency jittering circuit and chip - Google Patents

Frequency jittering circuit and chip Download PDF

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Publication number
CN117544139A
CN117544139A CN202311305379.2A CN202311305379A CN117544139A CN 117544139 A CN117544139 A CN 117544139A CN 202311305379 A CN202311305379 A CN 202311305379A CN 117544139 A CN117544139 A CN 117544139A
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China
Prior art keywords
terminal switching
frequency
switching device
output
delay
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Chinese (zh)
Inventor
胡永山
赵天挺
原义栋
吴顺珉
杜尉丰
贾晓鹏
季烨程
李军
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Beijing Smartchip Microelectronics Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
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Priority to CN202311305379.2A priority Critical patent/CN117544139A/en
Publication of CN117544139A publication Critical patent/CN117544139A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention provides a frequency-jittering circuit and a chip, and belongs to the technical field of electronics. The frequency jittering circuit includes: a low frequency oscillator; the digital counter is electrically connected with the output end of the low-frequency oscillator and is used for generating a delay control signal based on the output pulse number of the low-frequency oscillator; the high-frequency oscillator is electrically connected with the output end of the digital counter and is used for controlling the delay time of the output signal of the high-frequency oscillator based on the delay control signal so as to enable the output signal to realize frequency jittering. Compared with the prior frequency jittering circuit, the frequency jittering circuit is easy to be influenced by a semiconductor process by controlling the output range of the frequency jittering signal through controlling the power supply voltage of the ring oscillator, so that the frequency jittering output frequency range is difficult to control accurately. The invention realizes the control of the delay time of the output signal of the high-frequency oscillator by adopting the digital counter to carry out digital stepping control so as to lead the output signal to realize the frequency jitter, thereby realizing the accurate control of the frequency jitter output frequency range.

Description

Frequency jittering circuit and chip
Technical Field
The invention relates to the technical field of electronics, in particular to a frequency jittering circuit and a chip.
Background
The frequency jitter refers to that the chip is controlled by an internal circuit to enable the working frequency to be switched in a certain range, so that the interference energy is dispersed in a frequency domain, the effect of reducing the whole interference amplitude is achieved, and the integrated circuit chip meets the corresponding EMI (Electromagnetic Interference ) standard requirement.
Referring to fig. 2, the conventional dither circuit structure is composed of a low-frequency oscillator, a current source I, a transistor M1, a capacitor C1, a resistor R1, a transistor M2 and a ring oscillator. Wherein the ring oscillator is composed of three inverters. When the circuit works, the low-frequency oscillator outputs a control signal to control the on and off of the transistor M1. When the transistor M1 is turned on, a current forms a path, and the C1 voltage drops. When the transistor M1 is turned off, the voltage Vdrv charges the C1 through the resistor, so that a sawtooth wave is formed at the control end of the transistor M2, the voltage Vdrv, the resistor R1 and the transistor M2 form a source follower, and power is supplied to the ring oscillator, so that the ring oscillator outputs a jitter frequency signal.
However, in fig. 2, since the resistor R1 and the capacitor C1 are on-chip devices, they are affected by errors in the semiconductor processing process, and the jitter frequency output frequency range cannot be controlled accurately.
Disclosure of Invention
The embodiment of the invention aims to provide a frequency jittering circuit and a chip, which are used for solving the defect that the traditional frequency jittering circuit cannot accurately control the frequency range of frequency jittering output.
In order to achieve the above object, an embodiment of the present invention provides a frequency jittering circuit, including:
a low frequency oscillator;
the digital counter is electrically connected with the output end of the low-frequency oscillator and is used for generating a delay control signal based on the output pulse number of the low-frequency oscillator;
and the high-frequency oscillator is electrically connected with the output end of the digital counter and is used for controlling the delay time of the output signal of the high-frequency oscillator based on the delay control signal so as to enable the output signal to realize frequency jittering.
Optionally, the high-frequency oscillator includes a plurality of delay inverters connected end to form a loop, each of the delay inverters delaying an output signal based on the delay control signal.
Optionally, each of the delay inverters includes: an inverter and a delay control circuit electrically connected with an output end of the inverter; the delay control circuit delays an output signal based on the delay control signal.
Optionally, the delay control circuit includes:
a first three-terminal switching device group including a plurality of first three-terminal switching devices connected in parallel;
a second three-terminal switching device group connected in series with the first three-terminal switching device group, the second three-terminal switching device group including a plurality of second three-terminal switching devices connected in parallel; the first three-terminal switching device and the second three-terminal switching device are opposite in conduction condition; each first three-terminal switching device is correspondingly connected with one second three-terminal switching device in series;
a plurality of first resistors, wherein the connection end of each pair of first three-terminal switching devices and second three-terminal switching devices which are connected in series is connected with one first resistor, and the signal output end of the delay inverter which is connected with the first resistors in series is connected with the first resistors;
one end of the first capacitor is electrically connected with the signal output end, and the other end of the first capacitor is grounded;
wherein the control end of each first three-terminal switching device receives the delay control signal; the control end of each second three-terminal switching device receives the delay control signal; in each pair of the first three-terminal switching device and the second three-terminal switching device connected in series, the delay control signal of the control terminal of the first three-terminal switching device and the delay control signal of the control terminal of the second three-terminal switching device are opposite in phase.
Optionally, the delay time of each delay inverter is calculated based on a first capacitor and a first resistor in the current delay control circuit, which are controlled by the delay control signal to form a path.
Optionally, the first three-terminal switching devices are P-channel MOS transistors, and a drain electrode of each first three-terminal switching device is electrically connected to an output end of the inverter; the second three-terminal switching devices are N-channel MOS transistors, and the source electrode of each second three-terminal switching device is electrically connected with the output end of the inverter; the control end of the first three-terminal switching device and the control end of the second three-terminal switching device are respectively grid electrodes.
Optionally, the first three-terminal switching devices are PNP transistors, and a collector of each first three-terminal switching device is electrically connected with an output end of the inverter; the second three-terminal switching devices are NPN transistors, and the emitter of each second three-terminal switching device is electrically connected with the output end of the inverter; the control end of the first three-terminal switching device and the control end of the second three-terminal switching device are respectively base electrodes.
On the other hand, the embodiment of the invention also provides a chip which comprises the frequency jittering circuit.
Through the technical scheme, compared with the mode that the existing frequency jittering circuit controls the output range of the frequency jittering signal by controlling the power supply voltage of the ring oscillator, the frequency jittering circuit is easily influenced by a semiconductor process, and the frequency jittering output frequency range is difficult to control accurately. The invention realizes the control of the delay time of the output signal of the high-frequency oscillator by adopting the digital counter to carry out digital stepping control so as to lead the output signal to realize the frequency jitter, thereby realizing the accurate control of the frequency jitter output frequency range.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a schematic circuit diagram of a dithering circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of a prior art dither circuit;
fig. 3 is a schematic circuit diagram of a high frequency oscillator provided by the present invention;
fig. 4 is a schematic circuit diagram of each delay inverter in the high-frequency oscillator provided by the present invention.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Referring to fig. 2, the conventional jitter circuit of fig. 2 controls the output range of the jitter signal by controlling the supply voltage of the ring oscillator, and in fig. 2, the resistor R1 and the capacitor C1 are on-chip devices, which are affected by the error of the semiconductor processing technology, and cannot accurately control the jitter range. In addition, the resistor R1 and the capacitor C1 occupy a larger chip layout area, and it is difficult to realize a large-scale output frequency in a limited chip layout area. Meanwhile, the charge and discharge path formed by the voltage Vdrv, the resistor R1 and the capacitor C1 in the conventional frequency jittering circuit increases the complexity of the circuit and the power consumption of the system.
Accordingly, an objective of the present invention is to provide a dithering circuit and a chip for solving the defect that the dithering output frequency range cannot be precisely controlled by the conventional dithering circuit.
Referring to fig. 1, an embodiment of the present invention provides a dithering circuit 100, which includes a low frequency oscillator 10, a digital counter 20, and a high frequency oscillator 30, which are cascaded in sequence.
The low frequency oscillator 10 may be any commercially available oscillator that generates a sinusoidal signal of 20 hz to 20 khz.
A digital counter 20 is electrically connected to the output of the low frequency oscillator 10 for generating a delay control signal based on the number of output pulses of the low frequency oscillator 10. The digital counter 20 is used for counting the number of output pulses of the low frequency oscillator 10 and generating a delay control signal based on the number of output pulses of the low frequency oscillator 10.
And a high-frequency oscillator 30 electrically connected to the output terminal of the digital counter 20, for controlling the delay time of the output signal of the high-frequency oscillator 30 based on the delay control signal, so that the frequency of the output signal of the high-frequency oscillator 30 is changed within a control range, and the output signal of the high-frequency oscillator 30 is dithered.
Compared with the prior frequency jittering circuit, the frequency jittering circuit is easy to be influenced by a semiconductor process by controlling the output range of the frequency jittering signal through controlling the power supply voltage of the ring oscillator, so that the frequency jittering output frequency range is difficult to control accurately. The invention realizes the control of the delay time of the output signal of the high-frequency oscillator 30 by adopting the digital counter 20 to carry out digital stepping control so as to lead the output signal to realize the frequency jitter, thereby realizing the accurate control of the frequency jitter output frequency range.
In addition, compared with the existing frequency jittering circuit using a circuit for generating sawtooth waves, the embodiment of the invention uses the digital counter 20 to carry out digital stepping control, thereby reducing the complexity and static power consumption of the circuit.
In other aspects of the embodiment of the present invention, referring to fig. 3, the high-frequency oscillator 30 includes a plurality of delay inverters 31 connected end to form a loop, and each of the delay inverters 31 delays an output signal based on a delay control signal from the digital counter 20. The number of the delay inverters 31 may be various odd numbers. For example, in some embodiments, 3 delay inverters 31 may be selected. According to the embodiment of the invention, the plurality of delay inverters 31 delay the output signal based on the delay control signal, so that the frequency of the output signal changes within a control range, and the frequency-jittering effect is further realized.
In other aspects of the embodiments of the present invention, referring to fig. 4, each of the delay inverters 31 includes: inverter 311 and the sameA delay control circuit 312 electrically connected to the output terminal of the inverter 311; the delay control circuit 312 delays the output signal based on the delay control signal. Wherein the inverter 311 is configured to invert the input signal, and the delay control circuit 312 is configured to delay the output signal based on the delay control signal. Wherein the inverter 311 comprises a P-channel FET PM in And N-channel field effect transistor NM in . P-channel field effect transistor PM in Gate and N-channel field effect transistor NM in The gates commonly receive an input signal IN.
The delay control signal sent by the digital counter 20 controls the delay inverter 31 to change the delay time of the output signal, and the frequency of the output signal of the frequency dithering circuit 100 also changes periodically, so that an adjustable frequency dithering output function is realized, and more accurate frequency dithering output with wider frequency range is realized.
In other aspects of the embodiments of the present invention, referring to fig. 4, the delay control circuit 312 includes a first three-terminal switching device set 3121, a second three-terminal switching device set 3122, a plurality of first resistors 3123 and a first capacitor 3124.
The first three-terminal switching device group 3121 includes a plurality of first three-terminal switching devices 31211 connected in parallel. A second set of three-terminal switching devices 3122 is connected in series with the first set of three-terminal switching devices 3121. The second three-terminal switching device group 3122 includes a plurality of second three-terminal switching devices 31221 connected in parallel. The first and second three-terminal switching devices 31211 and 31221 are in opposite conduction conditions. Each of the first three-terminal switching devices 31211 is correspondingly connected to one of the second three-terminal switching devices 31221 in series. The connection terminals of each pair of the first and second three-terminal switching devices 31211 and 31221 connected in series are connected to one of the first resistors 3123, and a plurality of the first resistors 3123 are connected in series to the signal output terminal OUT of the delay inverter 31. One end of the first capacitor 3124 is electrically connected to the signal output terminal OUT, and the other end of the first capacitor 3124 is grounded.
In other aspects of the embodiments of the present invention, the first three-terminal switching devices 31211 are P-channel MOS transistors, and the drain of each of the first three-terminal switching devices 31211 is electrically connected to the output terminal of the inverter 311; the second three-terminal switching devices 31221 are N-channel MOS transistors, and the source of each of the second three-terminal switching devices 31221 is electrically connected to the output terminal of the inverter 311; the control terminal of the first three-terminal switching device 31211 and the control terminal of the second three-terminal switching device 31221 are gates, respectively.
It should be noted that, in other aspects of the embodiments of the present invention, the first three-terminal switching devices 31211 are PNP transistors, and the collector of each of the first three-terminal switching devices 31211 is electrically connected to the output terminal of the inverter 311; the second three-terminal switching devices 31221 are NPN transistors, and an emitter of each of the second three-terminal switching devices 31221 is electrically connected to the output terminal of the inverter 311; the control terminal of the first three-terminal switching device 31211 and the control terminal of the second three-terminal switching device 31221 are respectively bases.
Wherein it is assumed that the first three-terminal switching device 31211 has N, i.e. includes PM 0 、PM 1 、PM 2 、……、PM N-1 N P-channel MOS tubes are arranged in total. Assume that the second three-terminal switching device 31221 has N, i.e. includes NM 0 、NM 1 、NM 2 、……、NM N-1 N-channel MOS tubes are all arranged. Each first three-terminal switching device 31211 (PM [ N-1, 0]]I.e. from PM N-1 To PM 0 ) The gate of (c) receives the delay control signal (PG [ N-1, 0)]From PG N-1 To PG 0 ) The method comprises the steps of carrying out a first treatment on the surface of the Each of the second three-terminal switching devices 31221 (NM [ N-1,0]From NM N-1 To NM 0 ) The gate of (c) receives a delay control signal (NG N-1,0]From NG N-1 To NG 0 ) The method comprises the steps of carrying out a first treatment on the surface of the In each pair of the first and second three-terminal switching devices 31211 and 31221 connected in series, the delay control signal of the control terminal of the first three-terminal switching device 31211 and the delay control signal of the control terminal of the second three-terminal switching device 31221 are opposite in phase. The first resistor 3123 also has N, i.e. includes R0]、R[1]、……、R[N-1]. First resistor R0]、…、R[N-1]Is connected in series to the signal output terminal OUT, and determines the delay time of the delay inverter 31 together with the first capacitor 3124.
In operation of the dither circuit 100 of the present embodiment, the digital counter 20 counts PM [ N-1, 0]](from PM N-1 To PM 0 ) Sequentially outputs low level for NM [ N-1, 0]](from NM N-1 To NM 0 ) In the opposite phase, the following transition goes high. At a certain time t, the gate PG [ m ] of the mth first three-terminal switching device 31211]The signal is low and the gate NG m of the mth second three-terminal switching device 31221]The signal is at high level (0<m<N-1), then at time t, gate PG m of mth first three-terminal switching device 31211]Controlled mth first three-terminal switch device PM m And gate NG [ m ] of mth second three-terminal switching device 31221]Controlled mth second three-terminal switching device NM m On, at this time, the first resistor Rm]、…、R[N-1]Forms a path with the first capacitor 3124, and outputs a signal to the signal output terminal OUT.
In addition, the delay time of each of the delay inverters 31 is calculated based on the first capacitance 3124 and the first resistance 3123 of the current delay control circuit 312, which are controlled by the delay control signal to form a path.
Assume that at time t, the first resistors R [ m ], …, R [ N-1] and the first capacitor 3124 form a path for outputting a signal to the signal output terminal OUT. The calculation time constant at this time is shown in formula (1):
τ= (Rm+Rm+1+ … +Rn-1) C1; formula (1)
The delay time of the output signal of the single delay inverter 31 is 5 tau. At this time, the delay time of the high-frequency oscillator 30 is 15 τ, and the frequency of the output signal of the high-frequency oscillator 30 is calculated to be 1/30 τ. PG [ N-1, 0] when the low frequency oscillator 10 continuously outputs](i.e. from PG N-1 To PG 0 ) Sequentially receiving the low level output from the digital counter 20 from the PM 0 To PM N-1 And from NM 0 To NM N-1 Sequentially conducting, wherein in the cycle, the value range of tau is shown in a formula (2):
r < 0.C1 < τ < (R0+Rm+1+ … +RN-1) C1; formula (2)
Wherein the output signal frequency f of the high-frequency oscillator 30 is shown in formula (3):
the embodiment of the present invention controls the on/off states of the first and second three-terminal switching devices 31211 and 31221 in the delay inverter 31 by the delay control signal, thereby controlling the delay time of the output signal. The frequency of the output signal of the dithering circuit 100 in the embodiment of the present invention also shows a periodic variation by the delay time variation of the output signal, the variation range is controlled by the delay control signal sent by the digital counter 20, and the embodiment of the present invention realizes the adjustable dithering output function.
Compared with the prior frequency jittering circuit, the capacitor charge and discharge is utilized to generate sawtooth waves to control the power supply voltage of the ring oscillator, so that the output frequency is changed. The dithering circuit 100 of the embodiment of the present invention adjusts the dithering frequency range by controlling the delay time of the output signal of the high-frequency oscillator 30 through the digital counter 20, and can realize a more accurate dithering frequency output with a wider frequency range. In addition, the embodiment of the invention uses the digital counter 20 to carry out digital stepping control, thereby reducing the complexity and static power consumption of the circuit.
On the other hand, the embodiment of the present invention further provides a chip (not shown) including the frequency jittering circuit 100.
The specific structure of the frequency jitter circuit 100 refers to the above embodiments, and since the chip adopts all the technical solutions of all the embodiments, the chip has at least all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
It should be noted that the chip may be a power chip, an isolation chip, or a switch chip.
The power supply chip may be a DC-DC, i.e. a chip that converts an input direct voltage into another output direct voltage; or may be AC-DC, i.e., a chip that converts alternating current to direct current; or may be an LDO, i.e., a chip that converts high voltage direct current into lower voltage and stable direct current.
The isolation chip may be a digital isolator, an isolated power supply, or an isolated gate driver, etc.
The switch chip may be an analog switch chip, a load switch chip, or the like.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (8)

1. A dithering circuit, comprising:
a low frequency oscillator;
the digital counter is electrically connected with the output end of the low-frequency oscillator and is used for generating a delay control signal based on the output pulse number of the low-frequency oscillator;
and the high-frequency oscillator is electrically connected with the output end of the digital counter and is used for controlling the delay time of the output signal of the high-frequency oscillator based on the delay control signal so as to enable the output signal to realize frequency jittering.
2. The dither circuit according to claim 1, wherein the high-frequency oscillator includes a plurality of delay inverters connected end to form a loop, each of the delay inverters delaying an output signal based on the delay control signal.
3. The dithering circuit of claim 2, wherein each of the delay inverters comprises: the delay control circuit delays an output signal based on the delay control signal.
4. A dithering circuit according to claim 3, wherein the delay control circuit comprises:
a first three-terminal switching device group including a plurality of first three-terminal switching devices connected in parallel;
a second three-terminal switching device group connected in series with the first three-terminal switching device group, the second three-terminal switching device group including a plurality of second three-terminal switching devices connected in parallel, the first three-terminal switching devices having opposite conduction conditions to the second three-terminal switching devices, each first three-terminal switching device being correspondingly connected in series with one second three-terminal switching device;
a plurality of first resistors, one first resistor is connected to the connection end of each pair of the first three-terminal switching device and the second three-terminal switching device which are connected in series, and the plurality of first resistors are connected to the signal output end of the delay inverter in series;
one end of the first capacitor is electrically connected with the signal output end, and the other end of the first capacitor is grounded;
wherein the control end of each first three-terminal switching device receives the delay control signal; the control end of each second three-terminal switching device receives the delay control signal; in each pair of the first three-terminal switching device and the second three-terminal switching device connected in series, the delay control signal of the control terminal of the first three-terminal switching device and the delay control signal of the control terminal of the second three-terminal switching device are opposite in phase.
5. The jitter circuit of claim 4 wherein the delay time of each of said delay inverters is calculated based on a first capacitance and a first resistance of a current delay control circuit controlled by said delay control signal to form a path.
6. The frequency dithering circuit according to claim 4, wherein the first three-terminal switching devices are P-channel MOS transistors, and a drain of each of the first three-terminal switching devices is electrically connected to an output terminal of the inverter; the second three-terminal switching devices are N-channel MOS transistors, and the source electrode of each second three-terminal switching device is electrically connected with the output end of the inverter; the control end of the first three-terminal switching device and the control end of the second three-terminal switching device are respectively grid electrodes.
7. The frequency dithering circuit according to claim 4, wherein the first three-terminal switching devices are PNP transistors, and a collector of each of the first three-terminal switching devices is electrically connected to an output terminal of the inverter; the second three-terminal switching devices are NPN transistors, and the emitter of each second three-terminal switching device is electrically connected with the output end of the inverter; the control end of the first three-terminal switching device and the control end of the second three-terminal switching device are respectively base electrodes.
8. A chip comprising the dither circuit of any one of claims 1-7.
CN202311305379.2A 2023-10-10 2023-10-10 Frequency jittering circuit and chip Pending CN117544139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311305379.2A CN117544139A (en) 2023-10-10 2023-10-10 Frequency jittering circuit and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311305379.2A CN117544139A (en) 2023-10-10 2023-10-10 Frequency jittering circuit and chip

Publications (1)

Publication Number Publication Date
CN117544139A true CN117544139A (en) 2024-02-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311305379.2A Pending CN117544139A (en) 2023-10-10 2023-10-10 Frequency jittering circuit and chip

Country Status (1)

Country Link
CN (1) CN117544139A (en)

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