CN116032216B - Self-bias relaxation oscillator based on consumption - Google Patents
Self-bias relaxation oscillator based on consumption Download PDFInfo
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Abstract
The invention relates to a relaxation oscillator, in particular to a self-bias relaxation oscillator. It includes power supply VCC, comparator, capacitor C1, resistor R1, current I B, current I B2, current I B3, and output VOUT. The power supply VCC is connected with the comparator in an adaptive manner. The non-inverting input end of the comparator is connected with one end of the resistor R1, the other end of the resistor R1 is grounded, and the current I B1 is used for flowing into the resistor R1 to generate the reference voltage VREF. The reverse input end of the comparator is connected with the positive electrode of the capacitor C1, the negative electrode of the capacitor C1 is grounded, and the current I B is used for charging the capacitor. The output end of the comparator is connected with the output port VOUT in an adapting way, and the current I B3 is used for controlling the switch circuit to discharge the capacitor. The MOS transistor NM device is characterized in that an internal MOS transistor NM1 corresponding to a non-inverting input end of the comparator is a depletion type MOS transistor, and a grid electrode of the MOS transistor NM1 is grounded, so that self-bias current is generated, current I B1 is formed, and reference voltage VREF is generated autonomously. The oscillator has the advantages of simple structure, small static power consumption and small error at high and low temperatures of various process angles.
Description
Technical Field
The invention relates to a relaxation oscillator, in particular to a self-bias relaxation oscillator based on consumption and capable of generating reference voltage autonomously.
Background
The conventional relaxation oscillator structure is shown in fig. 1, and requires a reference voltage VREF circuit, which is generally generated by a current flowing into a resistor R1 (such as current I B of fig. 1R 1 generates VREF), a circuit for charging a capacitor (such as charging C1 in fig. 1B 2), the voltage on the capacitor C1 is compared with VREF by a comparator U1, when the voltage of the positive plate of the capacitor C1 is greater than the voltage of VREF, the comparator controls a switching tube NM2 to conduct and discharge the capacitor C1, then immediately turns off NM2, and the capacitor is normally charged, so that the oscillation effect is achieved, a reference voltage VREF is required, a current I B2 charges the capacitor, and a current I B3 provides an operating current for the comparator U1, so that the circuit requires an additional reference current circuit to generate I B1, I B2 and I B3, which results in more components of the whole circuit of the conventional relaxation oscillator, and larger static power consumption. Meanwhile, the defects of large errors at high and low temperatures of various process angles exist in a plurality of components.
Disclosure of Invention
The invention aims to solve the technical problem of providing a self-bias relaxation oscillator based on consumption, which has the advantages of simple structure, smaller static power consumption and smaller error at high and low temperatures of various process angles.
In order to solve the problems, the following technical scheme is provided:
the self-biased relaxation oscillator based on the consumption of the invention comprises a power supply VCC, a comparator, a capacitor C1, a resistor R1, a current I B1, a current I B2, a current I B3 and an output port VOUT. The power supply VCC is connected with the comparator in an adapting way and is used for providing driving voltage for the comparator. The non-inverting input end of the comparator is connected with one end of a resistor R1, the other end of the resistor R1 is grounded, and the current I B1 is used for flowing into the resistor R1 to generate a reference voltage VREF. The reverse input end of the comparator is connected with the positive electrode of the capacitor C1, the negative electrode of the capacitor C1 is grounded, and the current I B2 is used for charging the capacitor; the output end of the comparator is connected with the output port VOUT in an adaptive manner, the current I B3 is used for controlling the switch circuit to discharge the capacitor, and the comparator controls the capacitor to charge and discharge according to the comparison result of the reference voltage VREF and the positive voltage VC1 of the capacitor C1, so that the output port VOUT generates an oscillation signal. The MOS transistor NM device is characterized in that an internal MOS transistor NM1 corresponding to the non-inverting input end of the comparator is a depletion type MOS transistor, and the grid electrode of the MOS transistor NM1 is grounded, so that self-bias current is generated, current I B1 is formed, and reference voltage VREF is generated autonomously.
Wherein the current I B and the current I B are both generated by current mirror replica current I B1.
The comparator comprises a MOS tube PM1, a MOS tube PM2, a MOS tube NM2 and the MOS tube NM1, wherein the MOS tube NM2 is a depletion type MOS tube. The source electrodes of the MOS tube PM1 and the MOS tube PM2 are both connected with a power supply VCC, the grid electrode of the MOS tube PM1 is connected with the grid electrode of the MOS tube PM2, the grid electrode of the MOS tube PM1 is in short circuit with the drain electrode, the drain electrode of the MOS tube PM1 is connected with the drain electrode of the MOS tube NM1, and the source electrode of the MOS tube NM1 is the in-phase input end of the comparator. The drain electrode of the MOS tube PM2 is the output end of the comparator, the drain electrode of the MOS tube PM2 is connected with the drain electrode of the MOS tube NM2, the grid electrode of the MOS tube NM2 is grounded, and the source electrode of the MOS tube NM2 is the inverting input end of the comparator. The MOS transistor PM1 and the MOS transistor PM2 form a first current mirror copy current I B1 to form a current I B.
The switching circuit comprises a MOS tube NM3. The output end of the comparator is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the grid electrode of the MOS tube NM3. The power VCC is connected with the source electrode of the MOS tube PM3, the grid electrode of the MOS tube PM3 is connected with the grid electrode of the MOS tube PM1, the drain electrode of the MOS tube PM3 is connected with the drain electrode of the MOS tube NM3, and the source electrode of the MOS tube NM3 is grounded. The drain electrode of the MOS tube PM3 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the output port VOUT, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end of the inverter INV3 is connected with the grid electrode of the MOS tube NM 4. The positive electrode of the capacitor C1 is connected with the drain electrode of the MOS tube NM4, and the source electrode of the MOS tube NM4 is grounded; the MOS tube PM3 and the MOS tube PM1 form a second current mirror copy current I B1 to form a current I B.
The MOS tube PM1 is completely matched with the MOS tube PM2, and the MOS tube NM1 is completely matched with the MOS tube NM 2.
By adopting the scheme, the method has the following advantages:
because the internal MOS tube NM1 corresponding to the non-inverting input end of the comparator based on the self-bias relaxation oscillator based on the consumable although is a depletion type MOS tube, the grid electrode of the MOS tube NM1 is grounded, thereby generating self-bias current, forming current I B1, and further generating reference voltage VREF autonomously. The drain type NMOS tube grid electrode is grounded and self-biased to generate current, so that the oscillator provides reference current I B1 when in use, reference current I B flows into resistor R1 to generate reference voltage VREF and reference voltage VREF, a circuit for generating reference current I B1 is not required to be externally connected, the structure of the whole oscillator is simplified, and static power consumption is further reduced. Meanwhile, fewer components reduce errors at high and low temperatures of each process corner.
Drawings
FIG. 1 is a schematic diagram of a relaxation oscillator in the background;
FIG. 2 is a schematic diagram of the structure of a self-biased relaxation oscillator based on depletion of the present invention;
FIG. 3 is a graph of depletion MOS transistor IDS versus VGS;
fig. 4 is a waveform diagram of the operation of the self-biased relaxation oscillator based on depletion in the embodiment.
Detailed Description
The invention is described further below with reference to the accompanying drawings.
As shown in fig. 2, the self-biased relaxation oscillator based on depletion of the present invention includes power supply VCC, comparator, capacitor C1, resistor R1, current I B1, current I B2, current I B3 and output VOUT. The power supply VCC is connected with the comparator in an adapting way and is used for providing driving voltage for the comparator. The non-inverting input end of the comparator is connected with one end of a resistor R1, the other end of the resistor R1 is grounded, and the current I B1 is used for flowing into the resistor R1 to generate a reference voltage VREF. The reverse input end of the comparator is connected with the positive electrode of the capacitor C1, the negative electrode of the capacitor C1 is grounded, and the current I B2 is used for charging the capacitor. The output end of the comparator is connected with the output port VOUT in an adaptive manner, the current I B3 is used for controlling the switch circuit to discharge the capacitor, and the comparator controls the capacitor to charge and discharge according to the comparison result of the reference voltage VREF and the positive voltage VC1 of the capacitor C1, so that the output port VOUT generates an oscillation signal. The internal MOS tube NM1 corresponding to the non-inverting input end of the comparator is a depletion type MOS tube, and the grid electrode of the MOS tube NM1 is grounded, so that self-bias current is generated, current I B1 is formed, and reference voltage VREF is generated autonomously. The drain type NMOS tube grid electrode is grounded and self-biased to generate current, so that the oscillator provides reference current I B1 when in use, reference current I B flows into resistor R1 to generate reference voltage VREF and reference voltage VREF, a circuit for generating reference current I B1 is not required to be externally connected, the structure of the whole oscillator is simplified, and static power consumption is further reduced. Meanwhile, fewer components reduce errors at high and low temperatures of each process corner.
Both the current I B and the current I B are generated by current mirror replica current I B1. The current I B and the current I B3 can be generated independently by copying the current I B1 through the current mirror, so that the number of electric elements is further reduced, and the structure of the whole circuit is simpler.
The switching circuit comprises a MOS tube NM3. The comparator comprises a MOS tube PM1, a MOS tube PM2, a MOS tube NM2 and the MOS tube NM1, wherein the MOS tube NM2 is a depletion type MOS tube. The source electrodes of the MOS tube PM1 and the MOS tube PM2 are both connected with a power supply VCC, the grid electrode of the MOS tube PM1 is connected with the grid electrode of the MOS tube PM2, the grid electrode of the MOS tube PM1 is in short circuit with the drain electrode, the drain electrode of the MOS tube PM1 is connected with the drain electrode of the MOS tube NM1, and the source electrode of the MOS tube NM1 is the in-phase input end of the comparator. The drain electrode of the MOS tube PM2 is the output end of the comparator, the drain electrode of the MOS tube PM2 is connected with the drain electrode of the MOS tube NM2, the grid electrode of the MOS tube NM2 is grounded, and the source electrode of the MOS tube NM2 is the inverting input end of the comparator. The MOS transistor PM1 and the MOS transistor PM2 form a first current mirror copy current I B1 to form a current I B. The output end of the comparator is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the grid electrode of the MOS tube NM3; the power VCC is connected with the source electrode of the MOS tube PM3, the grid electrode of the MOS tube PM3 is connected with the grid electrode of the MOS tube PM1, the drain electrode of the MOS tube PM3 is connected with the drain electrode of the MOS tube NM3, and the source electrode of the MOS tube NM3 is grounded. The drain electrode of the MOS tube PM3 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the output port VOUT, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end of the inverter INV3 is connected with the grid electrode of the MOS tube NM 4. The positive electrode of the capacitor C1 is connected with the drain electrode of the MOS tube NM4, and the source electrode of the MOS tube NM4 is grounded; the MOS tube PM3 and the MOS tube PM1 form a second current mirror copy current I B1 to form a current I B.
The MOS tube PM1 is completely matched with the MOS tube PM2, and the MOS tube NM1 is completely matched with the MOS tube NM 2. Further reducing the error of each process corner at high and low temperatures.
As shown in fig. 3, the X-axis is VGS voltage, the Y-axis is current waveform ids flowing through DS, and the characteristics of depletion MOS transistor are that when VGS <0V, current flowing through DS gradually decreases until complete turn-off as VGS voltage decreases, and when w=10um, l=5um, vgs= -290mV (this process is described herein, there is a difference in different processes) there is a current of about 11uA flowing through MOS transistor DS.
In this embodiment, the MOS transistors NM1 and NM2 are depletion type MOS transistors, the size of the MOS transistors NM1 and the resistor R1 is adjusted to control the current flowing through the MOS transistors NM1 to multiply the resistor R1 to generate a reference voltage, because the depletion type NMOS transistor G is grounded and self-biased to generate a current, a VREF and a reference current I B1 are generated, the current I B and the current I B3 are mirror-copied from I B1 through a current mirror, and compared with a traditional circuit, the circuit does not need to supply power to a comparator additionally, does not need to perform current conversion by an excessive current mirror, and the MOS transistors NM1 and NM2 in the circuit are basically not affected by VCC voltage, temperature and process after being matched with each other in the layout.
In this embodiment, because the MOS transistor PM1 and the MOS transistor PM2 are completely matched, the MOS transistor NM1 and the MOS transistor NM2 are completely matched, so the current I B1 is equal to the current I B. When the oscillator of this embodiment works normally, vref= I B1 ×r1, when the positive voltage VC1 of the capacitor C1 is lower than VREF, the MOS transistor NM2 is turned on, the capacitor C1 is charged by the current I B, the positive voltage vc1= I B2 ×t/C1 of the capacitor C1, T is time, when the voltage of the capacitor C1 rises above the reference voltage VREF, the MOS transistor NM2 is turned off, the drain of the MOS transistor NM2 is pulled high, the gate of the MOS transistor NM3 is pulled low after passing through the inverter INV1, the MOS transistor NM3 is turned off, the drain thereof is pulled high, the gate of the MOS transistor NM4 is turned on, the capacitor C1 is discharged, and the VC1 is lower than the reference voltage VREF again, so that the output port outputs the oscillating current in this cycle, thereby achieving the oscillating effect.
Fig. 4 is a waveform diagram showing the operation of the present embodiment, when the reference voltage vref=290 mV, when VC1> VREF, the output VOUT of the oscillator becomes low, and the oscillator functions normally, t=1.18 uS.
In particular, vref=vc1 when the oscillator is flipped, so there are I B1×r1= I B2×t/C1, t=r1c1, and f=1/T, F is frequency, so f=1/R1C 1. In this embodiment, r1=50k, c1=20p, the theoretical value t=1us, and the measured value t=1.18us due to errors of devices and delays of circuit operation can be more accurate by slightly adjusting the capacitance.
The self-bias relaxation oscillator based on consumption of the invention has the advantages of simple structure, high precision, low power consumption, small influence by temperature and technology, no need of extra circuits, realization of the function of the oscillator, and wide application in switching power supplies, changepump and timers, delay circuits and trigger circuits.
Claims (3)
1. A self-bias relaxation oscillator based on consumption comprises a power supply VCC, a comparator, a capacitor C1, a resistor R1, a current IB2, a current IB3 and an output port VOUT; the power supply VCC is adaptively connected with the comparator and is used for providing driving voltage for the comparator; the non-inverting input end of the comparator is connected with one end of a resistor R1, the other end of the resistor R1 is grounded, and the current IB1 is used for flowing into the resistor R1 to generate a reference voltage VREF; the reverse input end of the comparator is connected with the positive electrode of the capacitor C1, the negative electrode of the capacitor C1 is grounded, and the current IB2 is used for charging the capacitor; the output end of the comparator is connected with the output port VOUT in an adaptive manner, the current IB3 is used for controlling the switch circuit to discharge the capacitor, and the comparator controls the capacitor to charge and discharge according to the comparison result of the reference voltage VREF and the positive voltage VC1 of the capacitor C1, so that the output port VOUT generates an oscillation signal; the MOS transistor NM circuit is characterized in that an internal MOS transistor NM1 corresponding to a non-inverting input end of the comparator is a depletion type MOS transistor, and a grid electrode of the MOS transistor NM1 is grounded, so that self-bias current is generated, current IB1 is formed, and reference voltage VREF is generated autonomously; both the current IB2 and the current IB3 are generated by a current mirror replica current IB 1; the comparator comprises a MOS tube PM1, a MOS tube PM2, a MOS tube NM2 and the MOS tube NM1, wherein the MOS tube NM2 is a depletion type MOS tube; the sources of the MOS tube PM1 and the MOS tube PM2 are both connected with a power supply VCC, the grid electrode of the MOS tube PM1 is connected with the grid electrode of the MOS tube PM2, the grid electrode of the MOS tube PM1 is in short circuit with the drain electrode, the drain electrode of the MOS tube PM1 is connected with the drain electrode of the MOS tube NM1, and the source electrode of the MOS tube NM1 is the in-phase input end of the comparator; the drain electrode of the MOS tube PM2 is the output end of the comparator, the drain electrode of the MOS tube PM2 is connected with the drain electrode of the MOS tube NM2, the grid electrode of the MOS tube NM2 is grounded, and the source electrode of the MOS tube NM2 is the inverting input end of the comparator; the MOS tube PM1 and the MOS tube PM2 form a first current mirror copy current IB1 to form a current IB2.
2. The self-biased relaxation oscillator based on depletion according to claim 1, characterized in that the switching circuit comprises a MOS transistor NM3; the output end of the comparator is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the grid electrode of the MOS tube NM3; the power supply VCC is connected with the source electrode of the MOS tube PM3, the grid electrode of the MOS tube PM3 is connected with the grid electrode of the MOS tube PM1, the drain electrode of the MOS tube PM3 is connected with the drain electrode of the MOS tube NM3, and the source electrode of the MOS tube NM3 is grounded; the drain electrode of the MOS tube PM3 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the output port VOUT, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end of the inverter INV3 is connected with the grid electrode of the MOS tube NM 4; the positive electrode of the capacitor C1 is connected with the drain electrode of the MOS tube NM4, and the source electrode of the MOS tube NM4 is grounded; the MOS tube PM3 and the MOS tube PM1 form a second current mirror copy current IB1 to form a current IB3.
3. The self-biased relaxation oscillator based on depletion mode as claimed in claim 1 or 2, wherein said MOS tube PM1 and MOS tube PM2 are fully matched, said MOS tube NM1 and MOS tube NM2 being fully matched.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211593613.1A CN116032216B (en) | 2022-12-13 | 2022-12-13 | Self-bias relaxation oscillator based on consumption |
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| CN202211593613.1A CN116032216B (en) | 2022-12-13 | 2022-12-13 | Self-bias relaxation oscillator based on consumption |
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| CN116032216A CN116032216A (en) | 2023-04-28 |
| CN116032216B true CN116032216B (en) | 2024-02-13 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102156505A (en) * | 2009-12-25 | 2011-08-17 | 三美电机株式会社 | Current source circuit and delay circuit and oscillating circuit using the same |
| CN112953521A (en) * | 2019-12-11 | 2021-06-11 | 精工爱普生株式会社 | Charge pump circuit, PLL circuit, and oscillator |
| CN115202430A (en) * | 2021-04-13 | 2022-10-18 | 拓尔微电子股份有限公司 | Reference voltage generating circuit and oscillator |
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- 2022-12-13 CN CN202211593613.1A patent/CN116032216B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102156505A (en) * | 2009-12-25 | 2011-08-17 | 三美电机株式会社 | Current source circuit and delay circuit and oscillating circuit using the same |
| CN112953521A (en) * | 2019-12-11 | 2021-06-11 | 精工爱普生株式会社 | Charge pump circuit, PLL circuit, and oscillator |
| CN115202430A (en) * | 2021-04-13 | 2022-10-18 | 拓尔微电子股份有限公司 | Reference voltage generating circuit and oscillator |
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| CN116032216A (en) | 2023-04-28 |
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