CN117476763B - E-HEMT with low leakage current and preparation method - Google Patents

E-HEMT with low leakage current and preparation method Download PDF

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CN117476763B
CN117476763B CN202311824671.5A CN202311824671A CN117476763B CN 117476763 B CN117476763 B CN 117476763B CN 202311824671 A CN202311824671 A CN 202311824671A CN 117476763 B CN117476763 B CN 117476763B
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buffer layer
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CN117476763A (en
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蔡文哲
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Shenzhen Sirius Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention provides an E-HEMT with low electric leakage and a preparation method thereof, wherein the E-HEMT comprises the following components: a heterojunction substrate; the heterojunction substrate comprises a base and a silicon-based N+ buffer layer; the substrate is positioned below the silicon-based N+ buffer layer and is adjacent to the silicon-based N+ buffer layer; the silicon-based N+ buffer layer is positioned between the GaN buffer layer and the substrate and is adjacent to the GaN buffer layer. The invention replaces the traditional silicon substrate with the material with higher forbidden bandwidth and better heat conduction performance, such as silicon carbide material, because the silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate and the like, and is suitable for high-temperature, high-power and extreme environments.

Description

E-HEMT with low leakage current and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to an E-HEMT with low electric leakage and a preparation method thereof.
Background
The GaN material has the characteristics of large forbidden bandwidth, high critical breakdown electric field, high thermal conductivity and the like, so that the GaN material has unique advantages in the aspects of preparing high-voltage, high-temperature, high-power and high-density integrated electronic devices. The GaN material may form a heterojunction structure with AlGaN or the like. Since the barrier layer material such as AlGaN has spontaneous polarization and piezoelectric polarization effects, a two-dimensional electron gas (2 DEG) with high concentration and high mobility is formed at the heterojunction interface. This feature can not only improve carrier mobility and operating frequency of the GaN-based devices, but also reduce on-resistance and switching delay of the devices. The GaN-based HEMT device has the characteristics of high breakdown characteristic, high switching speed, small on-resistance and the like, and has wide application prospect in the power electronic fields such as power management, wind power generation, solar batteries, electric automobiles and the like. Compared with the traditional MOS device, the GaN-based HEMT device has higher switching speed and bears higher reverse voltage, can improve efficiency, reduce loss and save energy, and has huge market application prospect in the 600V-1200V device range.
For power devices, it is critical to achieve enhanced and high voltage operation. From the standpoint of safety and energy consumption, it is necessary that no extra leakage occurs in the event of a power outage. The preparation of enhanced devices with superior performance is one research direction of great research value. If the conventional E-HEMT (Enhanced Modle HEMT) device continuously pressurizes a source electrode (Souce) and a Drain electrode (Drain) under the turn-off condition, the GaN HEMT can generate large-area electric leakage, the electric leakage channel layer is mainly positioned in the GaN buffer layer, and can further cause electric leakage phenomenon that current flows from the GaN buffer layer to the substrate, the electric leakage phenomenon can further cause internal heating of the device to cause the problem of failure and circuit damage of the GaN HEMT device, the selection of the substrate material of the semiconductor power device directly influences the performance and reliability of the power device, silicon, quartz, sapphire and the like are often selected as the substrate materials in the prior art, but the traditional substrate materials can not meet the insulation requirement under the high-voltage working condition of the power device, and the application field of the GaN HEMT is severely limited.
Disclosure of Invention
The invention aims to provide an E-HEMT with low electric leakage and a preparation method, the E-HEMT replaces a traditional silicon substrate with a material with higher forbidden bandwidth and better heat conduction performance, such as a silicon carbide material, because the third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field strength, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, the E-HEMT can be suitable for high-temperature, high-frequency, high-power and extreme environments, compared with the silicon material, the silicon carbide has larger forbidden bandwidth and higher critical breakdown field strength, and an N-type heavily doped layer is introduced above the silicon carbide layer as a buffer layer, so that an electron well can be formed by the silicon-based N+ doped layer, the electric leakage phenomenon at the bottom end of the substrate is further weakened, and the integral thermal effect of the device is reduced.
An E-HEMT with low leakage, comprising: a heterojunction substrate;
The heterojunction substrate comprises a base and a silicon-based N+ buffer layer;
the substrate is positioned below the silicon-based N+ buffer layer and is adjacent to the silicon-based N+ buffer layer;
The silicon-based N+ buffer layer is positioned between the GaN buffer layer and the substrate and is adjacent to the GaN buffer layer.
Preferably, the forbidden bandwidth of the filling material of the substrate is larger than that of silicon.
Preferably, the filling material of the substrate includes: silicon carbide.
Preferably, the doping concentration of the n+ buffer layer is 10 19cm-3.
Preferably, the thickness of the n+ buffer layer is 3um.
Preferably, the thickness of the substrate is 25um.
Preferably, the thermal conductivity of the filler material of the substrate is equal to or greater than the thermal conductivity of silicon carbide.
Preferably, the method further comprises: gaN buffer layer, alGaN barrier layer, gaN layer, source electrode, drain electrode and grid electrode,
The GaN buffer layer is positioned above the heterojunction substrate;
The GaN layer is positioned above the GaN buffer layer;
the AlGaN barrier layer is positioned above the GaN layer;
the source electrode is positioned above the AlGaN barrier layer;
the grid electrode is positioned above the AlGaN barrier layer;
the drain is located over the AlGaN barrier layer.
A method of making an E-HEMT with low leakage, comprising:
a layer of N-type heavily doped silicon layer is epitaxially grown on the substrate to form a silicon-based N+ buffer layer;
Forming a GaN buffer layer, a GaN layer and an AlGaN barrier layer by epitaxy above the silicon-based N+ buffer layer;
A gate, a drain, and a source are deposited.
Preferably, the forming a silicon-based n+ buffer layer by extending an N-type heavily doped silicon layer above the substrate includes:
A silicon layer with the thickness of 3um is epitaxially grown on the substrate;
and performing ion implantation in the silicon layer to form a silicon-based N+ buffer layer with the doping concentration of 10 19cm-3.
The invention replaces the silicon substrate of the traditional E-HEMT with a material with higher forbidden band width than the silicon substrate, because the material with higher forbidden band width can form higher potential barrier difference with the GaN buffer layer, electrons are difficult to pass through the potential barrier, the current leaked from the GaN buffer layer to the substrate direction is reduced, the replaced substrate material also has high heat dissipation performance, the heat in the E-HEMT can be effectively led out, the heating condition in the E-HEMT is improved, the failure condition of the E-HEMT caused by overheating in the E-HEMT is avoided, an N+ buffer layer with N-type heavy doping is additionally arranged below the GaN buffer layer, and the silicon-based N+ doping layer can be used for manufacturing an electronic trap, so that the electric leakage phenomenon at the bottom of the substrate is further weakened, and the integral heat effect of the E-HEMT device is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic illustration of an E-HEMT structure of the present invention;
FIG. 2 is a schematic diagram of a process flow for preparing an E-HEMT according to the invention;
FIG. 3 is a schematic diagram of the E-HEMT manufacturing flow structure of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
For power devices, it is critical to achieve enhanced and high voltage operation. From the standpoint of safety and energy consumption, it is necessary that no extra leakage occurs in the event of a power outage. The preparation of enhanced devices with superior performance is one research direction of great research value. Under the condition that the conventional E-HEMT (Enhanced Modle HEMT) device is turned off, if the source electrode (Souce) and the Drain electrode (Drain) are continuously pressurized, the GaN HEMT can generate large-area electric leakage, the electric leakage channel layer is mainly positioned in the GaN buffer layer, electric leakage phenomenon that current flows from the GaN buffer layer to the substrate can be further caused, the electric leakage phenomenon can further cause internal heating of the device to cause failure of the GaN HEMT device and circuit damage, the performance and reliability of the power device are directly affected by the selection of the substrate material of the semiconductor power device, silicon, quartz, sapphire and the like are often selected as the substrate material in the prior art, but the traditional substrate material cannot meet the insulation requirement under the high-voltage working condition of the power device, and the application field of the GaN HEMT is severely limited.
In the prior art, in order to prevent the substrate from leaking electricity, methods are generally adopted including: the surface treatment of the substrate is enhanced, and common surface treatment methods include cleaning, oxidation, film deposition, and the like. The cleaning can remove impurities and pollutants on the surface, so that the purity of the surface is improved; oxidation can form a layer of oxide film, so that the insulating property is enhanced; the film deposition can form an insulating layer on the surface, so that the insulating capability is further improved. By these surface treatment methods, occurrence of leakage problems can be effectively prevented. The structural design of the semiconductor device is also an important link for preventing electric leakage. For example, in transistor design, the distance between the gate, the source and the drain is reasonably set, and the gap is filled with a proper insulating material, so that current leakage can be effectively prevented. In addition, the insulation performance of the device can be improved by adding structures such as a protective layer and an isolation layer, and the electric leakage is further reduced. Reinforcing electrical insulation is an important means of preventing electrical leakage. In the manufacturing process of the semiconductor device, electrical insulation may be achieved by using materials such as an insulating layer, an insulating substrate, an insulating paste, and the like. The insulating materials have good electrical insulation performance, and can effectively isolate current and prevent leakage. Strict quality control is critical to prevent leakage problems. In the production process of the semiconductor device, a perfect quality control system needs to be established to ensure that each link meets the standard requirements. For example, in the material purchasing process, materials meeting the standard are selected; in the manufacturing process, the process parameters are strictly controlled; during the test, a tight electrical performance test is performed. However, the above method is relatively expensive to produce and is not suitable for mass production.
The invention replaces the silicon substrate of the traditional E-HEMT with a material with higher forbidden band width than the silicon substrate, because the material with higher forbidden band width can form higher potential barrier difference with the GaN buffer layer, electrons are difficult to pass through the potential barrier, the current leaked from the GaN buffer layer to the substrate direction is reduced, the replaced substrate material also has high heat dissipation performance, the heat in the E-HEMT can be effectively led out, the heating condition in the E-HEMT is improved, the failure condition of the E-HEMT caused by overheating in the E-HEMT is avoided, an N+ buffer layer with N-type heavy doping is additionally arranged below the GaN buffer layer, and the silicon-based N+ doping layer can be used for manufacturing an electronic trap, so that the electric leakage phenomenon at the bottom of the substrate is further weakened, and the integral heat effect of the E-HEMT device is reduced.
Example 1
An E-HEMT with low leakage, referring to fig. 1, comprising: a heterojunction substrate;
The substrate is a material for supporting crystal formation, and the substrate plays a role of mechanical support. In the present invention, the substrate is made of silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is critical to ensure uniformity and integrity of crystal growth. In addition, the substrate can also prevent impurities and defects during crystal growth. Second, the substrate plays an important role in the electrical properties of the GaN HEMT. In the preparation of a GaN HEMT, the electrical properties of the substrate determine the performance and stability of the device. For example, the conductivity of the substrate directly affects the efficiency and speed of current transport. In addition, the electron affinity and the forbidden band width of the substrate are also critical for adjusting the threshold voltage and electron mobility of the GaN HEMT. In addition, the substrate plays an important role in isolating the insulating layer of the GaN HEMT. In the GaN HEMT fabrication process, the insulating layer of the substrate is typically composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulating properties of the GaN HEMT, such as electrical insulation and capacitance characteristics. The good insulating layer can effectively isolate different electrodes in the GaN HEMT structure and reduce leakage current and capacitive coupling effect.
The heterojunction substrate comprises a base and a silicon-based N+ buffer layer;
the heterojunction of the semiconductor is a special PN junction, and is formed by sequentially depositing more than two layers of different semiconductor material films on the same base, wherein the materials have different energy band gaps, and can be compounds such as gallium arsenide or semiconductor alloys such as silicon-germanium. The heterojunction is an interfacial region formed by the contact of two different semiconductors. Heterojunctions can be classified into homoheterojunctions (P-junctions or N-junctions) and heteroheterojunctions (P-N or P-N) according to the conductivity types of the two materials, and multilayer heterojunctions are called heterostructures. The conditions under which the heterojunction is typically formed are: the two semiconductors have similar crystal structures, similar atomic spacing and thermal expansion coefficients. Heterojunction can be fabricated by interfacial alloy, epitaxial growth, vacuum deposition, etc. The heterojunction has excellent photoelectric characteristics which cannot be achieved by PN junctions of two semiconductors, so that the heterojunction is suitable for manufacturing ultra-high-speed switching devices, solar cells, semiconductor lasers and the like.
Because the heterojunction is formed by contacting two semiconductor single crystal materials of different materials, and the lattice constants of the two different materials are often different, lattice mismatch results in dangling bonds at the interface of the two semiconductor materials, that is, some unsaturated bonds appear in the semiconductor material with smaller lattice constants at the interface, and these dangling bonds seriously affect the movement of carriers, so that the heterojunction has some characteristics that the homojunction does not have, for example: the two-dimensional electron gas exists at the interface of the AlGaN barrier layer and the GaN layer heterojunction, and the AlGaN/GaN heterojunction is formed by epitaxially growing an N-type GaN buffer layer and then epitaxially growing a P-type AlGaN barrier layer. Since AlGaN materials have a wider band gap than GaN materials, when equilibrium is reached, the energy band at the interface of the heterojunction is bent, resulting in discontinuity of the conduction band and the valence band, and a triangular potential well is formed at the heterojunction interface. On the GaN side, the conduction band bottom is already below the fermi level, so there will be a large number of electrons accumulated in the triangular potential well. At the same time, the high barrier on the side of the wide bandgap AlGaN makes it difficult for electrons to surmount the potential well, and electrons are confined to move laterally in a thin layer of interface, known as a two-dimensional electron gas (2 DEG). The heterojunction energy band may have abrupt change of energy band or electron barrier (upward peak) at interface, or electron potential well (downward peak) at interface, and the characteristic that energy band bending can be generated by heterojunction interface is utilized.
In the embodiment of the invention, the heterojunction substrate consists of an N-type semiconductor N+ buffer layer made of a silicon material and a P-type semiconductor made of a semiconductor material with higher forbidden band width and stronger heat conduction performance than the silicon material,
The substrate is positioned below the silicon-based N+ buffer layer and is adjacent to the silicon-based N+ buffer layer;
the silicon-based N+ buffer layer is positioned between the GaN buffer layer and the substrate and is adjacent to the GaN buffer layer.
The substrate and the silicon-based N+ buffer layer form a heterojunction substrate together, in fig. 1, the substrate, the silicon-based N+ buffer layer and the GaN buffer layer are respectively arranged from bottom to top in the vertical direction, the substrate is tightly connected with the silicon-based N+ buffer layer, the silicon-based N+ buffer layer is tightly connected with the GaN buffer layer, and in the HEMT, the GaN material is a key material of the GaN HEMT device and has the advantages of wide forbidden band, high electron mobility, high saturation drift speed and the like. However, due to the lattice mismatch between GaN and standard substrate materials, crystal defects and high-density lattice dislocations can result, affecting device performance. To solve this problem, a buffer layer needs to be introduced between the substrate and the GaN material. The buffer layer has the main functions of relieving stress caused by lattice mismatch, reducing defect density and improving film quality. Typical buffer materials include AlN, gaN, alGaN. The AlGaN buffer layer or the GaN buffer layer or the AlN buffer layer can effectively improve the electrical property of the GaN HEMT device and improve the mobility. In the growth process of the buffer layer, the quality of crystals can be optimized and defects can be reduced by controlling parameters such as growth temperature, thickness, flow and the like.
Preferably, the fill material of the substrate has a forbidden bandwidth greater than that of silicon.
The forbidden band width refers to a band gap width (the unit is electron volt (ev)), and the energy of electrons in the solid cannot be continuously valued, but is discontinuous energy bands, free electrons or holes exist in order to conduct electricity, the energy band in which the free electrons exist is called a conduction band, and the energy band in which the free holes exist is called a valence band. To be a free electron or hole, the bound electron must acquire enough energy to transition from the valence band to the conduction band, the minimum of which is the forbidden bandwidth.
The forbidden bandwidth is an important characteristic parameter of a semiconductor, and its size is mainly determined by the energy band structure of the semiconductor, that is, the binding property of the crystal structure and atoms. A large number of electrons in the semiconductor valence band are electrons on the valence bond (referred to as valence electrons) and are not capable of conducting electricity, i.e., are not carriers. Conduction can only occur after the valence electrons have transitioned to the conduction band (i.e., intrinsic excitation) to generate free electrons and free holes. Holes are in fact valence vacancies left after a valence electron transition to the conduction band (the motion of one hole is equivalent to the motion of a large group of valence electrons). Therefore, the magnitude of the forbidden bandwidth reflects a physical quantity of how strongly or weakly valence electrons are bound, i.e., the minimum energy required to generate intrinsic excitation. The energy between the lowest energy level of the conduction band and the highest energy level of the valence band. The electrons stay mostly in the valence band due to the lower energy level of the valence band. The valence band is typically predominantly holes, nonconductive, and conduction band electrons can move and conduct. The forbidden band width is the separation between the conduction band and the valence band, which is one of the electron transitions. Electrons bound in the valence band must gain enough energy to transition to the conduction band to become free electrons.
Because the forbidden bandwidth of the filling material of the base is larger than that of the silicon, the current can be prevented from being remained from the buffer layer to the substrate, and the formation of the heterojunction enables electrons to have energy band offset between the silicon and the filling material of the base, so that an electron barrier is formed, and the electron barrier can control the movement of electrons between the two materials, so that the purpose of blocking the electrons outside the substrate is achieved.
Materials having a larger forbidden band width than silicon mainly include silicon carbide (SiC), cubic boron nitride (C-BN), gallium nitride (GaN) aluminum nitride (AlN), zinc selenide (ZnSe), diamond, and the like. The material has the forbidden band width of more than 2eV, the forbidden band width of silicon is 1.12eV, and the wide forbidden band semiconductor material has the characteristics of wide band gap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift speed and the like, and can be applied to the aspects of high temperature, high frequency, high power, photoelectrons, radiation resistance and the like.
Preferably, the filler material of the substrate comprises: silicon carbide.
Because the forbidden bandwidth of silicon carbide is far greater than that of silicon, and other properties of silicon carbide are also superior to that of silicon, for example, the breakdown field strength of silicon carbide is 3MV/cm, while the breakdown field strength of silicon is only 0.3MV/cm, the forbidden bandwidth of silicon carbide is far greater than that of silicon, the corresponding intrinsic carrier concentration is smaller than that of silicon, and the highest working temperature of a wide forbidden bandwidth semiconductor is higher than that of a silicon material. The breakdown field strength is much greater than silicon. As a preferred embodiment, the present invention uses silicon carbide as the filler material for the substrate.
Preferably, the doping concentration of the n+ buffer layer is 10 19cm-3.
The doping concentration of the n+ buffer layer will affect the energy band difference between the GaN buffer layer and the substrate, the higher the doping concentration of the n+ buffer layer, the more difficult it is for electrons to reach the n+ buffer layer from the GaN buffer layer, the larger the energy band difference between the n+ buffer layer and the substrate, and the better the anti-leakage performance of the E-HEMT, so the doping concentration of the n+ buffer layer is set to be greater than the doping concentration of the GaN buffer layer, so that the electron barrier is greater, and the anti-leakage performance of the substrate is better.
Preferably, the thickness of the n+ buffer layer is 3um.
The greater the thickness of the n+ buffer layer, the more difficult it is for electrons to reach the substrate through the n+ buffer layer, the better the anti-leakage performance of the E-HEMT, and if the thickness of the n+ buffer layer is increased, the doping concentration of the n+ buffer layer may be reduced, and correspondingly, if the thickness of the n+ buffer layer is smaller, the doping thickness of the n+ buffer layer needs to be increased in order to block electrons from passing through the n+ buffer layer, and if the thickness of the n+ buffer layer is too large, the defect of increasing the chip area may be caused, so that the thickness of the n+ buffer layer should not be too large.
Preferably, the thickness of the substrate is 25um.
The substrate provides mechanical support for the whole E-HEMT and can conduct heat with the external environment, and can discharge heat generated by the E-HEMT in normal operation to the external environment, and the thickness of the substrate cannot be less than 20um because the substrate needs to provide mechanical support for the E-HEMT, and if the substrate is too thick, the chip area is increased, and as a preferred embodiment, the thickness of the substrate is set to 25um.
Preferably, the thermal conductivity of the filler material of the substrate is equal to or greater than the thermal conductivity of silicon carbide.
The thermal conductivity is the thermal conductivity coefficient of the semiconductor material, reflects the thermal conductivity capability of the semiconductor material, is defined as the heat transferred by a unit thermal gradient (the temperature is reduced by 1K in 1m length) through a unit thermal conducting surface in unit time, and an object with high thermal conductivity is an excellent thermal conductor; while the thermal conductivity is small is a poor conductor of heat or a thermal insulator. The value of the thermal conductivity is also affected by the temperature, the density of the material is high and its thermal conductivity is also generally high. The heat conductivity of the metal is reduced when the metal contains impurities, the heat conductivity of the alloy is lower than that of pure metal, and the heat conductivity of various substances is in the range of: the metal is 50-415W/(mXK), the alloy is 12-120W/(mXK), the heat insulating material is 0.03-0.17W/(mXK), the liquid is 0.17-0.7W/(mXK), the gas is 0.007-0.17W/(mXK), and the carbon nano tube is up to 1000W/(mXK) or more. The traditional semiconductor material silicon has the thermal conductivity of 150W/(m×K), and the thermal conductivity of 490W/(m×K) which is far greater than that of silicon, so that the material with the thermal conductivity greater than or equal to that of silicon carbide and the forbidden bandwidth greater than that of silicon can be used as the filling material of the substrate in the selection of the substrate filling material.
Preferably, the method further comprises: gaN buffer layer, alGaN barrier layer, gaN layer, source electrode, drain electrode and grid electrode,
The GaN buffer layer is positioned above the heterojunction substrate;
the buffer layer has the main functions of relieving stress caused by lattice mismatch, reducing defect density and improving film quality. Typical buffer materials include AlN, gaN, alGaN. The GaN buffer layer can effectively improve the electrical property of the GaN HEMT device and improve the mobility. In the growth process of the GaN buffer layer, the quality of the crystal can be optimized and the defects can be reduced by controlling parameters such as growth temperature, thickness, flow and the like.
The GaN layer is positioned above the GaN buffer layer;
The AlGaN barrier layer is positioned above the GaN layer;
the source electrode is positioned above the AlGaN barrier layer;
the grid electrode is positioned above the AlGaN barrier layer;
by adjusting the applied gate voltage (relative to the source), the two-dimensional electron gas (2 DEG) density in the channel can be regulated, thereby achieving control of the gate voltage and drain voltage over the drain current (output current).
The drain electrode is located over the AlGaN barrier layer.
A GaN-based heterojunction field effect transistor (GaN HEMT) operates with a high concentration and high electron mobility 2DEG formed in an AlGaN/GaN heterojunction channel. The conventional GaN HEMT is a transverse device, and the structure of the conventional GaN HEMT mainly comprises a substrate, a GaN buffer layer, a gallium nitride channel layer (GaN layer), an AlGaN barrier layer, and a source electrode, a grid electrode and a drain electrode which are respectively arranged on the upper surface of the AlGaN barrier layer, wherein the substrate, the GaN buffer layer, the gallium nitride channel layer (GaN layer) and the AlGaN barrier layer are sequentially grown from bottom to top, and the source electrode and the drain electrode form ohmic contact with the AlGaN barrier layer; the grid electrode and the AlGaN barrier layer form Schottky contact; and a passivation layer grows on the surface of the AlGaN barrier layer between the source electrode and the drain electrode.
Example 2
A method of making an E-HEMT with low leakage, referring to fig. 2, 3, comprising:
S100, an N-type heavily doped silicon layer is epitaxially grown on the substrate to form a silicon-based N+ buffer layer;
The epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate, and the epitaxial process is a process of growing a crystal layer in the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, epitaxially forming a GaN buffer layer, a GaN layer and an AlGaN barrier layer above the silicon-based N+ buffer layer;
s300, depositing a grid electrode, a drain electrode and a source electrode.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like.
Preferably, S100 of forming a silicon-based n+ buffer layer by epitaxially growing an N-type heavily doped silicon layer over a substrate includes:
s101, a silicon layer with the thickness of 3um is epitaxially grown on the substrate;
S102, performing ion implantation in the silicon layer to form a silicon-based N+ buffer layer with the doping concentration of 10 19cm-3.
The invention adopts an ion implantation mode to carry out ion implantation in the silicon layer to form the N+ buffer layer with the doping concentration of 10 19cm-3. The doping concentration and thickness of the silicon-based N+ buffer layer are controlled by controlling the times, the doses and the energy of ion implantation. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
The invention replaces the silicon substrate of the traditional E-HEMT with a material with higher forbidden band width than the silicon substrate, because the material with higher forbidden band width can form higher potential barrier difference with the GaN buffer layer, electrons are difficult to pass through the potential barrier, the current leaked from the GaN buffer layer to the substrate direction is reduced, the replaced substrate material also has high heat dissipation performance, the heat in the E-HEMT can be effectively led out, the heating condition in the E-HEMT is improved, the failure condition of the E-HEMT caused by overheating in the E-HEMT is avoided, an N+ buffer layer with N-type heavy doping is additionally arranged below the GaN buffer layer, and the silicon-based N+ doping layer can be used for manufacturing an electronic trap, so that the electric leakage phenomenon at the bottom of the substrate is further weakened, and the integral heat effect of the E-HEMT device is reduced.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. An E-HEMT with low leakage, comprising: a heterojunction substrate;
The heterojunction substrate comprises a base and a silicon-based N+ buffer layer;
the silicon-based N+ buffer layer is an N-type heavily doped silicon layer;
the substrate is positioned below the silicon-based N+ buffer layer and is adjacent to the silicon-based N+ buffer layer;
the silicon-based N+ buffer layer is positioned between the GaN buffer layer and the substrate and is adjacent to the GaN buffer layer;
the thickness of the substrate is larger than that of the silicon-based N+ buffer layer;
the substrate is silicon carbide;
The thickness of the substrate is 25 microns;
the thickness of the n+ buffer layer was 3 microns.
2. The E-HEMT with low leakage according to claim 1, wherein said n+ buffer layer has a doping concentration of 10 19cm-3.
3. The E-HEMT with low leakage of claim 1, further comprising: alGaN barrier layer, gaN layer, source electrode, drain electrode and grid electrode,
The GaN layer is positioned above the GaN buffer layer;
the AlGaN barrier layer is positioned above the GaN layer;
the source electrode is positioned above the AlGaN barrier layer;
the grid electrode is positioned above the AlGaN barrier layer;
the drain is located over the AlGaN barrier layer.
4. A method for manufacturing an E-HEMT with low leakage, the method being applied to manufacture an E-HEMT with low leakage according to any one of claims 1-3, comprising:
An N-type heavily doped silicon layer is epitaxially grown on the substrate of the silicon carbide material to form a silicon-based N+ buffer layer;
Forming a GaN buffer layer, a GaN layer and an AlGaN barrier layer by epitaxy above the silicon-based N+ buffer layer;
A gate, a drain, and a source are deposited.
5. The method for preparing an E-HEMT with low leakage according to claim 4, wherein forming a silicon-based N+ buffer layer by epitaxially growing an N-type heavily doped silicon layer over the substrate comprises:
a silicon layer with the thickness of 3 micrometers is epitaxially grown on the substrate;
and performing ion implantation in the silicon layer to form a silicon-based N+ buffer layer with the doping concentration of 10 19cm-3.
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