CN117457731B - SiC vertical IGBT with P-type space layer below grid electrode and preparation method - Google Patents
SiC vertical IGBT with P-type space layer below grid electrode and preparation method Download PDFInfo
- Publication number
- CN117457731B CN117457731B CN202311778302.7A CN202311778302A CN117457731B CN 117457731 B CN117457731 B CN 117457731B CN 202311778302 A CN202311778302 A CN 202311778302A CN 117457731 B CN117457731 B CN 117457731B
- Authority
- CN
- China
- Prior art keywords
- layer
- type space
- region
- space layer
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 37
- 238000005468 ion implantation Methods 0.000 claims description 33
- 238000000151 deposition Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 48
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 48
- 230000008569 process Effects 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 18
- 239000007789 gas Substances 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000000903 blocking effect Effects 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 239000013078 crystal Substances 0.000 description 10
- 239000000126 substance Substances 0.000 description 9
- 230000007547 defect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000010884 ion-beam technique Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011343 solid material Substances 0.000 description 4
- 238000000348 solid-phase epitaxy Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000003877 atomic layer epitaxy Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000001721 carbon Chemical class 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010893 electron trap Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a SiC vertical IGBT with a P-type space layer below a grid electrode and a preparation method, wherein the SiC vertical IGBT comprises the following components: a P-type space layer; the P-type space layer is positioned between the grid electrode, the N+ region and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region and the drift layer. The invention introduces the P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector, the interface mobility of the gate oxide layer and the silicon carbide is low, the resistance is large, and the conductive path shorts the interface channel of the gate oxide layer, so that the on-resistance of the SiC vertical IGBT is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC vertical IGBT with a P-type space layer below a grid electrode and a preparation method thereof.
Background
IGBT (Insulated Gate Bipolar Transistor) is an insulated gate bipolar transistor (igbt) for short, which is composed of a Bipolar Junction Transistor (BJT) and a metal oxide field effect transistor (MOSFET), is a composite fully-controlled voltage-driven switching power semiconductor device, is a core device for realizing electric energy conversion, and is one of the main development directions of the current MOS-bipolar power devices. The IGBT has the characteristics of high MOSFET input impedance, easy driving of a grid electrode and the like, has the advantages of high current density, high power density and the like of a bipolar transistor, and is widely applied to the fields of high voltage and high current such as rail transit, new energy automobiles, smart grids, wind power generation and the like, and the fields of low-power household appliances such as microwave ovens, washing machines, electromagnetic ovens, electronic rectifiers, cameras and the like. The IGBT is basically the same as the MOSFET in driving method, the IGBT is a three-terminal device, the front surface is provided with two electrodes, namely an emitter (Emitter) and a Gate (Gate), the back surface is provided with a Collector (Collector), and in a forward working state, the emitter is grounded or connected with negative voltage, the Collector is connected with positive voltage, and the voltage Vce between the two electrodes is >0, so the emitter and the Collector of the IGBT are respectively called a Cathode (Cathode) and an Anode (Anode). The IGBT can control the on/off/blocking state of the IGBT by controlling the magnitudes of its collector-emitter voltage Vce and gate-emitter voltage Vge. The switching function of the IGBT is to form a channel by applying a forward gate voltage to provide base current for the PNP transistor so as to conduct the IGBT. And conversely, the reverse gate voltage is applied to eliminate the channel, and the reverse base current flows to turn off the IGBT.
The maximum voltage of Si IGBTs can reach 8.4 kV, approaching the limit of Si devices, but the frequency and operating temperature also greatly limit the further development of Si IGBTs in these fields. SiC has a higher breakdown field strength, higher intrinsic temperature, higher thermal conductivity and higher carrier saturation drift velocity as a wide bandgap material. Therefore, the SiC IGBT device shows stronger competitiveness in the fields of high voltage, high temperature and high power, the maximum blocking voltage of the SiC IGBT can reach 15kV, and the device has fewer carrier storage effects, because the atomic surface density of the unit area of the SiC is higher than that of Si, the density of dangling Si bonds, C bonds and carbon clusters at the interface is higher, more defects can be introduced when grid oxygen is formed, the defects act as electron traps, and the problem of SiC/SiO 2 interface defects can cause the reduction of the reliability of the device.
Disclosure of Invention
The invention aims to provide a SiC vertical IGBT with a P-type space layer below a grid electrode and a preparation method thereof, wherein the P-type space layer is introduced below the grid electrode of the SiC vertical IGBT, and because the thickness of the P-type space layer is very thin, when the grid electrode is connected with a positive voltage, an inversion layer is formed on the P-type space layer under a lower grid voltage, so that a conductive path from an emitter to an N+ region, from the N+ region to the P-type space layer, from the P-type space layer to a drift layer and finally to a collector is formed, the mobility of a grid oxide and a silicon carbide interface is low, the resistance is large, and the conductive path shorts an interface channel of the grid oxide, thereby reducing the on-resistance of the SiC vertical IGBT.
A SiC vertical IGBT having a P-type space layer under a gate, comprising: a P-type space layer;
the P-type space layer is positioned between the grid electrode, the N+ region and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region and the drift layer.
Preferably, the thickness of the P-type space layer is 80-100nm.
Preferably, the doping concentration of the P-type space layer is 5×10 15 to 10 16cm-3.
Preferably, the method further comprises: an N-buffer layer;
the N-buffer layer is located between a substrate and the drift layer and is adjacent to the substrate and the drift layer.
Preferably, the doping concentration of the N-buffer layer is 5×10 17 to 10 18cm-3.
Preferably, the width of the P-type space layer is larger than or equal to the sum of the width of the grid electrode and the width of the N+ region.
Preferably, the method further comprises: an emitter, a collector, a grid, a substrate, a buffer layer, a drift layer and a P+ region;
the collector electrode is positioned below the substrate;
The substrate is positioned below the buffer layer;
The buffer layer is positioned below the drift layer;
The drift layer is positioned below the P+ region;
the P+ region is located below the emitter;
the grid electrode is positioned below the emitter electrode;
the emitter is located over the n+ region, the p+ region, and the gate.
A preparation method of a SiC vertical IGBT with a P-type space layer below a grid electrode comprises the following steps:
a buffer layer and a drift layer are epitaxially grown over the substrate;
Ion implantation is carried out on the upper layer of the drift layer to form a P-type space layer, an N+ region and a P+ region;
Etching the N+ region to form a groove;
depositing a gate in the trench;
emitter and collector are deposited.
Preferably, the forming the P-type space layer, the n+ region and the p+ region by ion implantation on the upper layer of the drift layer comprises:
ion implantation is carried out on the upper layer of the drift layer to form a P-type space layer;
Ion implantation is carried out on two sides of the P-type space layer to form a P+ region;
and forming an N+ region on the upper layer of the P-type space layer by ion implantation.
Preferably, the forming the n+ region by ion implantation on the upper layer of the P-type space layer includes:
and performing ion implantation above the P-type space layer with the thickness of 80-100nm to form an N+ region.
The invention introduces the P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector, the interface mobility of the gate oxide layer and the silicon carbide is low, the resistance is large, and the conductive path shorts the interface channel of the gate oxide layer, so that the on-resistance of the SiC vertical IGBT is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of a SiC vertical IGBT structure of the present invention;
Fig. 2 is a schematic diagram of a process flow of preparing a SiC vertical IGBT according to the present invention;
fig. 3 is a schematic diagram of a SiC vertical IGBT manufacturing flow structure of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The maximum voltage of Si IGBTs can reach 8.4 kV, approaching the limit of Si devices, but the frequency and operating temperature also greatly limit the further development of Si IGBTs in these fields. SiC has a higher breakdown field strength, higher intrinsic temperature, higher thermal conductivity and higher carrier saturation drift velocity as a wide bandgap material. Therefore, the SiC IGBT device shows stronger competitiveness in the fields of high voltage, high temperature and high power, the maximum blocking voltage of the SiC IGBT can reach 15kV, and the device has fewer carrier storage effects, because the atomic surface density of the unit area of the SiC is higher than that of Si, the density of dangling Si bonds, C bonds and carbon clusters at the interface is higher, more defects can be introduced when grid oxygen is formed, the defects act as electron traps, and the problem of SiC/SiO 2 interface defects can cause the reduction of the reliability of the device.
The invention introduces the P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector, the interface mobility of the gate oxide layer and the silicon carbide is low, the resistance is large, and the conductive path shorts the interface channel of the gate oxide layer, so that the on-resistance of the SiC vertical IGBT is reduced.
Example 1
A SiC vertical IGBT with a P-type space layer under the gate, referring to fig. 1, comprising: a P-type space layer;
The substrate of the PN junction is divided into P type and N type, and +is heavily doped (high doping concentration), is lightly doped (low doping concentration), and P type doped with IIIA group elements, such as: boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl). N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc).
The P-type space layer is positioned between the grid electrode, the N+ region and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region and the drift layer.
The P-type space layer is a P-type doped semiconductor, the P-type space layer is arranged between the N+ region and the drift layer, a conductive path positioned in the P-type space layer can be opened by the grid electrode, negative charges positioned in the P-type space layer can be attracted by the grid electrode when the grid electrode is connected with positive voltage, so that an inversion layer is formed below the grid electrode, current can flow from the emitter to the N+ region, then flow from the N+ region to the P-type space layer, flow from the P-type space layer to the drift layer, and finally flow from the drift layer to the collector.
Because the thickness of the P-type space layer is small, the P-type space layer can form a conductive path from the N+ region to the drift layer under a lower gate voltage, so that the problem of low mobility of a silicon carbide-silicon dioxide interface is solved, the channel resistance is greatly reduced, and the electrical performance of the SiC vertical IGBT is remarkably improved.
Preferably, the thickness of the P-type space layer is 80-100nm.
The thickness of the P-type space layer can influence the opening voltage of the conductive channel, because the opening of the conductive channel needs to change the P-type space layer into an inversion layer completely in the vertical direction, the larger the thickness of the P-type space layer is, the more difficult the P-type space layer is to be completely induced into the inversion layer in the vertical direction, the higher the required gate voltage is, the thickness of the P-type space layer is not too thick, otherwise, the gate is difficult to induce to form the inversion layer, the opening voltage required by the conductive channel is too high, and the on-resistance is increased accordingly, the thickness of the P-type space layer is not too thin, the smaller the thickness of the P-type space layer is, electrons can easily pass through the P-type space layer, so that the too thin P-type space layer can lead to electric leakage of the SiC vertical IGBT, and the voltage resistance is reduced.
Preferably, the doping concentration of the P-type space layer is 5×10 15 to 10 16cm-3.
The doping concentration of the P-type space layer influences the opening voltage of the conductive channel, because majority carriers in the P-type semiconductor are holes, the principle of opening the conductive channel by the grid is that electrons in the P-type space layer are attracted to form the conductive channel, the higher the doping concentration of the P-type semiconductor is, the higher the concentration of the holes is, the smaller the concentration of the electrons is, the more difficult the grid is to attract electrons to form the conductive channel, the higher the grid voltage is needed to form an inversion layer on the P-type space layer, so that the higher the doping concentration of the P-type space layer is, the higher the opening voltage of the conductive channel is, the lower the doping concentration of the P-type space layer is, the opening voltage of the conductive channel is, and if the doping concentration of the P-type space layer is too small, the problem that the SiC vertical IGBT is leaked and the withstand voltage performance is reduced is solved.
Preferably, the method further comprises: an N-buffer layer;
the N-buffer layer is positioned between the substrate and the drift layer and is adjacent to the substrate and the drift layer.
The N-buffer layer is a buffer layer and is mainly used for blocking expansion of a depletion layer of the SiC vertical IGBT during forward blocking, so that the SiC vertical IGBT can achieve the same forward blocking capacity as a non-punch-through IGBT by using a smaller width of the drift layer, the switching speed of the SiC vertical IGBT is improved, and meanwhile, a lower on-state voltage drop is maintained, and the SiC vertical IGBT has good forward blocking characteristics.
When the grid voltage is larger than the threshold voltage, the SiC vertical IGBT starts to conduct, the grid induces an inversion layer in the P-type space layer, a conducting channel is formed in the P-type space layer, electrons are injected into the drift layer through the conducting channel, and hole injection of a collector P+ region is pushed. Due to the large width of the drift layer, most of the holes recombine in the drift layer with electrons injected from the conductive channel. The remaining holes diffuse from the drift layer to the PN junction formed by the drift layer and the P+ region, and the holes are captured by the electric field through the space charge region into the P+ region due to the slight reverse bias of the PN junction formed by the drift layer and the P+ region. Since the drift layer adopts a low doping concentration in order to achieve a high blocking voltage capability, the hole concentration at a medium current density exceeds the doping concentration of the drift layer. Therefore, the drift layer is in a large injection state, and is accompanied by a strong conductivity modulation effect, so that a good low-on-state voltage drop and high current density can be kept in the on state of the SiC vertical IGBT. Therefore, the buffer layer is arranged between the drift layer and the substrate, so that the switching speed of the SiC vertical IGBT is remarkably improved.
Preferably, the doping concentration of the N-buffer layer is 5×10 17 to 10 18cm-3.
In the punch-through type IGBT, a buffer layer with high concentration doping is required to be disposed between the substrate and the drift layer to increase the switching speed of the IGBT and maintain a low on-state voltage drop, if the doping concentration of the N-buffer layer is too low, the expansion of the depletion layer cannot be blocked, and if the doping concentration of the N-buffer layer is too high, the depletion layer cannot be depleted, and as a preferred embodiment, the present invention sets the doping concentration of the N-buffer layer to 10 18cm-3.
Preferably, the width of the P-type space layer is greater than or equal to the sum of the gate and the width of the n+ region.
If the width of the P-type space layer is smaller than the sum of the width of the gate and the width of the N+ region, part of the SiC vertical IGBT is leaked, and the P-type space layer does not extend to the bottom of the N+ region completely, part of the N+ region which forms ohmic contact with the emitter is leaked, a part of current directly flows to the N column and then flows to the drain, the SiC vertical IGBT leaks, the circuit is damaged, and the safety and reliability of the SiC vertical IGBT are reduced.
Preferably, the method further comprises: an emitter, a collector, a grid, a substrate, a buffer layer, a drift layer and a P+ region;
the collector electrode is positioned below the substrate;
the collector is used for collecting and outputting electrons and converting the electron flow into current output.
The substrate is positioned below the buffer layer;
The substrate is a material for supporting crystal generation in the IGBT, and the substrate plays a role of mechanical support. In the present invention, the substrate is made of silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is critical to ensure uniformity and integrity of crystal growth. In addition, the substrate can also prevent impurities and defects during crystal growth, thereby improving the quality of the IGBT. Second, the substrate plays an important role in the electrical performance of the IGBT. In fabricating an IGBT, the electrical properties of the substrate determine the performance and stability of the device. For example, the conductivity of the substrate directly affects the efficiency and speed of current transport. In addition, the electron affinity and the forbidden band width of the substrate are also important for adjusting the threshold voltage and the electron mobility of the IGBT. In addition, the substrate plays an important role in isolating the insulating layer of the IGBT. In IGBT fabrication, the insulating layer of the substrate is typically composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulating properties of the IGBT, such as electrical insulation and capacitance characteristics. The good insulating layer can effectively isolate different electrodes in the IGBT structure and reduce leakage current and capacitive coupling effect.
The buffer layer is positioned below the drift layer;
The P-type substrate is used as a collector region of the SiC vertical IGBT, has a high concentration and is difficult to thin, and in order to reduce the injection efficiency of hole carriers at the collector side, an n+ buffer layer is typically epitaxially grown between the drift layer and the substrate to block part of hole injection. In the blocking state, the buffer layer also plays a role in cutting off the electric field of the drift region.
The drift layer is positioned below the P+ region;
The electric field distribution of the drift layer plays a key role in the on-characteristics and current control of the IGBT. When a gate voltage is applied to the IGBT, the electric field distribution in the drift layer is modulated by the gate voltage, thereby controlling the current flow between the source and drain. When the IGBT is in operation, current between the source and drain is mainly transferred through the drift layer. The doping type and concentration of the drift layer determine the conduction type (N-type or P-type) and the magnitude of the current. The structure and characteristics of the drift layer directly affect the current control capability of the IGBT. By adjusting the shape, size and doping concentration of the drift layer, accurate control of current can be achieved, so that the requirements of different applications are met.
The P+ region is positioned below the emitter;
The grid electrode is positioned below the emitter electrode;
the grid electrode is a control electrode in the IGBT, is separated from the channel by an insulating layer and is a key part of the IGBT. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the emitter and collector.
The emitter is located over the n+ region, the p+ region, and the gate.
The emitter is used for supplying electrons and controlling current.
Example 2
Referring to fig. 2 and 3, a method for manufacturing a SiC vertical IGBT having a P-type space layer under a gate includes:
S100, an epitaxial buffer layer and a drift layer are arranged above a substrate;
The epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate, and the epitaxial process is a process of growing a crystal layer in the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processing in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like.
S200, forming a P-type space layer, an N+ region and a P+ region on the upper layer of the drift layer by ion implantation;
The invention adopts ion implantation to form a P-type space layer, an N+ region and a P+ region on the upper layer of the drift layer. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S300, etching the N+ region to form a groove;
Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gases and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is a chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor whereby the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S400, depositing a grid electrode in the groove;
The deposited grid adopts a polysilicon deposition method, namely, a grid electrode and local connection lines are formed on the silicide stack on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forms contact plugs between the source electrode/drain electrode and the unit connection lines. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) that can be performed in situ by directly introducing a dopant gas of arsine (AH 3), phosphine (PH 3), or diborane (B 2H6) into the silicon material gas of silane or DCS in a reaction chamber (i.e., in a furnace). Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.
S500, depositing an emitter and a collector.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like.
Preferably, S200, forming the P-type space layer, the n+ region and the p+ region by ion implantation on the upper layer of the drift layer includes:
s210, forming a P-type space layer by ion implantation on the upper layer of the drift layer;
S220, performing ion implantation on two sides of the P-type space layer to form a P+ region;
s230, forming an N+ region on the upper layer of the P-type space layer by ion implantation.
And performing ion implantation on the upper layer of the drift layer according to the preset positions and doping concentrations of the P-type space layer, the N+ region and the P+ region, firstly depositing a layer of P-type space layer with the thickness of 80-100nm on the upper layer of the drift layer, then continuing to perform pentavalent ion implantation on two sides of the P-type space layer to form a P+ region of a P-type semiconductor with higher doping concentration, and then performing trivalent ion implantation on the upper part of the P-type space layer to change an N column with low doping concentration into an N+ region with high doping concentration, thereby completing the preparation of the semiconductor structure.
Preferably, S230, forming an n+ region on the upper layer of the P-type space layer by ion implantation includes:
and performing ion implantation above the P-type space layer with the thickness of 80-100nm to form an N+ region.
When the ion implantation above the P-type space layer is needed to form an N+ region, the thickness of the P-type space layer is not less than 80nm, in order to control the thickness of the P-type space layer more easily, the N column is fully implanted into the P-type space layer, then the ion implantation is carried out on the upper layer with the thickness of 80-100nm of the P-type space layer to form the N+ region, namely, the P-type space layer with the bottom thickness of 80-100nm is reserved, and the upper layer is partially implanted to form the N+ region.
The invention introduces the P-type space layer below the trench gate, because the thickness of the P-type space layer is very thin, when the gate is connected with positive voltage, an inversion layer is formed on the P-type space layer under lower gate voltage, thereby forming a conductive path from the emitter to the N+ region, from the N+ region to the P-type space layer, from the P-type space layer to the drift layer and finally to the collector, the interface mobility of the gate oxide layer and the silicon carbide is low, the resistance is large, and the conductive path shorts the interface channel of the gate oxide layer, so that the on-resistance of the SiC vertical IGBT is reduced.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A SiC vertical IGBT having a P-type space layer under a gate, comprising: the P-type semiconductor device comprises a P-type space layer, an emitter, a grid electrode, a P+ region, an N+ region and a drift layer;
The P-type space layer is positioned between the grid electrode, the N+ region and the drift layer and is adjacent to the grid electrode oxide layer, the N+ region and the drift layer;
The P-type space layer is adjacent to the bottom surface of the grid electrode;
the thickness of the P-type space layer is 80-100nm;
The doping concentration of the P-type space layer is 5 multiplied by 10 15 to 10 16cm-3;
The width of the P-type space layer is larger than or equal to the sum of the widths of the grid electrode and the N+ region;
the emitter is positioned above the N+ region, the grid electrode and the P+ region and is adjacent to the P+ region, the N+ region and the grid electrode;
the grid electrode is positioned below the emitter electrode;
the P+ region is positioned below the emitter and is adjacent to the N+ region;
the N+ region is positioned below the emitter and on two sides of the grid electrode;
The thickness of the N+ region is equal to that of the gate trench;
the thickness of the P+ region is larger than that of the grid electrode groove;
Further comprises: an N-buffer layer;
the N-buffer layer is located between a substrate and the drift layer and is adjacent to the substrate and the drift layer.
2. The SiC vertical IGBT with a P type space layer under the gate of claim 1 wherein the N-buffer layer has a doping concentration of 5 x 10 17 to 10 18cm-3.
3. The SiC vertical IGBT with a P type space layer under the gate of claim 1 further comprising: a collector electrode, a substrate and a buffer layer;
the collector electrode is positioned below the substrate;
The substrate is positioned below the buffer layer;
The buffer layer is located below the drift layer.
4. A method for manufacturing a SiC vertical IGBT having a P-type space layer under a gate, the method being applied to manufacture a SiC vertical IGBT having a P-type space layer under a gate as claimed in any one of claims 1 to 3, comprising:
a buffer layer and a drift layer are epitaxially grown over the substrate;
ion implantation is carried out on the upper layer of the drift layer to form a P-type space layer, an N+ region and a P+ region;
Etching the N+ region to form a groove;
depositing a gate in the trench;
emitter and collector are deposited.
5. The method for fabricating a vertical IGBT with a P type space layer under a gate of claim 4 wherein forming the P type space layer, the n+ region, and the p+ region by ion implantation on the upper layer of the drift layer comprises:
ion implantation is carried out on the upper layer of the drift layer to form a P-type space layer;
Ion implantation is carried out on two sides of the P-type space layer to form a P+ region;
and forming an N+ region on the upper layer of the P-type space layer by ion implantation.
6. The method for fabricating a vertical IGBT with a P type space layer under a gate of claim 5 wherein forming an n+ region by ion implantation on the upper layer of the P type space layer comprises:
and performing ion implantation above the P-type space layer with the thickness of 80-100nm to form an N+ region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311778302.7A CN117457731B (en) | 2023-12-22 | 2023-12-22 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311778302.7A CN117457731B (en) | 2023-12-22 | 2023-12-22 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117457731A CN117457731A (en) | 2024-01-26 |
| CN117457731B true CN117457731B (en) | 2024-05-28 |
Family
ID=89593265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311778302.7A Active CN117457731B (en) | 2023-12-22 | 2023-12-22 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117457731B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763902A (en) * | 1996-03-27 | 1998-06-09 | Abb Research Ltd. | Insulated gate bipolar transistor having a trench and a method for production thereof |
| US6069371A (en) * | 1997-03-17 | 2000-05-30 | Kabushiki Kaisha Toshiba | Semiconductor rectifier and a method for driving the same |
| JP2000311998A (en) * | 1999-04-08 | 2000-11-07 | Rockwell Sci Center Llc | Insulated gate turn-off thyristor |
| CN105593996A (en) * | 2013-10-02 | 2016-05-18 | 株式会社电装 | Silicon carbide semiconductor device |
| CN107644904A (en) * | 2017-09-11 | 2018-01-30 | 电子科技大学 | A kind of mos gate control IGCT and preparation method thereof |
| CN109427886A (en) * | 2017-08-25 | 2019-03-05 | 比亚迪股份有限公司 | MOSFET and preparation method, electronic equipment, vehicle |
| CN216980573U (en) * | 2021-09-30 | 2022-07-15 | 比亚迪股份有限公司 | Semiconductor field effect transistor and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10468509B2 (en) * | 2017-06-07 | 2019-11-05 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
-
2023
- 2023-12-22 CN CN202311778302.7A patent/CN117457731B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763902A (en) * | 1996-03-27 | 1998-06-09 | Abb Research Ltd. | Insulated gate bipolar transistor having a trench and a method for production thereof |
| US6069371A (en) * | 1997-03-17 | 2000-05-30 | Kabushiki Kaisha Toshiba | Semiconductor rectifier and a method for driving the same |
| JP2000311998A (en) * | 1999-04-08 | 2000-11-07 | Rockwell Sci Center Llc | Insulated gate turn-off thyristor |
| CN105593996A (en) * | 2013-10-02 | 2016-05-18 | 株式会社电装 | Silicon carbide semiconductor device |
| CN109427886A (en) * | 2017-08-25 | 2019-03-05 | 比亚迪股份有限公司 | MOSFET and preparation method, electronic equipment, vehicle |
| CN107644904A (en) * | 2017-09-11 | 2018-01-30 | 电子科技大学 | A kind of mos gate control IGCT and preparation method thereof |
| CN216980573U (en) * | 2021-09-30 | 2022-07-15 | 比亚迪股份有限公司 | Semiconductor field effect transistor and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117457731A (en) | 2024-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN117253905A (en) | SiC device with floating island structure and preparation method thereof | |
| CN117334745A (en) | Source electrode groove integrated SBD super junction SiC MOS and preparation method | |
| CN117334746A (en) | Source electrode groove integrated SBD super-junction SiC MOS with oxide layer and preparation method | |
| CN117334747A (en) | SiC planar MOS of source electrode groove integrated SBD and preparation method | |
| CN117476773B (en) | LDMOS with low electric leakage and preparation method | |
| CN117525140A (en) | Integrated strip-shaped groove source electrode control freewheel channel SiC UMOS and preparation method | |
| CN117423730A (en) | sJ SiC VDMOS with split gate and preparation method thereof | |
| CN117253924A (en) | Silicon carbide LDMOS and preparation method | |
| CN117238964A (en) | Super-junction SiC MOS with homoheterojunction freewheel channel and preparation method | |
| CN117438469A (en) | SiC super-junction MOS with homoheterojunction freewheel channel and preparation method | |
| CN117457731B (en) | SiC vertical IGBT with P-type space layer below grid electrode and preparation method | |
| CN117457732B (en) | SiC LIGBT with P-type space layer below grid electrode and preparation method | |
| CN117457748B (en) | SiC super-junction MOS with P-type space layer below grid electrode and preparation method | |
| CN117457749B (en) | SiC LMOS with P-type space layer below grid electrode and preparation method | |
| CN117476758A (en) | IGBT (insulated Gate Bipolar transistor) capable of improving latch-up resistance based on N+ region and N-region and preparation method | |
| CN117727756B (en) | High-voltage-resistant GaN HEMT suitable for high-frequency application and preparation method | |
| CN117497578B (en) | IGBT with low electric leakage and preparation method | |
| CN117410322B (en) | Groove type super junction silicon MOSFET and preparation method | |
| CN117476756A (en) | Silicon carbide IGBT with trench emitter and preparation method | |
| CN117334748B (en) | Source electrode trench integrated SBD and HK medium SiC UMOS and preparation method | |
| CN117476757A (en) | IGBT with high latch-up resistance and preparation method | |
| CN117423729A (en) | Trench gate VDMOS with heterojunction and preparation method | |
| CN117525139A (en) | Integrated strip-shaped groove source electrode control follow current channel plane SiC MOS and preparation method | |
| CN117525136A (en) | SiC UMOS with N buried layer and preparation method | |
| CN117238914A (en) | SiC device integrated with SBD and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |