CN110571275A - preparation method of gallium oxide MOSFET - Google Patents
preparation method of gallium oxide MOSFET Download PDFInfo
- Publication number
- CN110571275A CN110571275A CN201910879776.8A CN201910879776A CN110571275A CN 110571275 A CN110571275 A CN 110571275A CN 201910879776 A CN201910879776 A CN 201910879776A CN 110571275 A CN110571275 A CN 110571275A
- Authority
- CN
- China
- Prior art keywords
- gallium oxide
- beta
- doped
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 164
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 164
- 238000002360 preparation method Methods 0.000 title description 14
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 42
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 150000002739 metals Chemical class 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 24
- 230000008569 process Effects 0.000 description 11
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000005566 electron beam evaporation Methods 0.000 description 8
- 238000009616 inductively coupled plasma Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000001755 magnetron sputter deposition Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
a gallium oxide MOSFET semiconductor device, comprising: a gallium oxide-based substrate; a drain electrode and a source electrode arranged on the gallium oxide substrate; highly doped gallium oxide with a doping concentration of 10 is arranged in the gallium oxide-based substrate at least in the lower regions of the drain electrode and the source electrode17‑1020cm‑3(ii) a The grid dielectric layer is arranged in the area which is not covered with the source electrode and the drain electrode on the gallium oxide substrate; and the grid electrode is arranged on the grid dielectric layer. Compared with the original MOSFET device which uses low work function metal as a source electrode and a drain electrode, the device of the invention can effectively solve the problems of over-high threshold voltage or low switching ratio of the device in the original device.
Description
Technical Field
The invention relates to the field of semiconductors, and further relates to a preparation method of a gallium oxide MOSFET.
background
At present, the gallium oxide material is difficult to realize effective P-type doping, so that the enhanced gallium oxide MOSFET is difficult to easily obtain a high on-off ratio. For a depletion-type gallium Oxide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), although the depletion-type gallium Oxide MOSFET can be easily implemented without using a complex structure or process, the existing device also has the problem of over-high threshold voltage (> 30V), which seriously affects the practical application of the device. Gallium oxide (Ga)2O3) Due to its excellent characteristics, it has a wide forbidden band (4.8eV), and a large forbidden bandThe breakdown electric field (8MV/cm) has wide application prospect in high-power devices and is expected to become a new generation of semiconductor material.
However, the gallium oxide power enhancement MOSFET has the problems that the current switching ratio is not high and the off threshold voltage of the depletion MOSFET is too high. This prevents the efficient use of gallium oxide materials, and there is a need for a method to improve the on-off ratio of gallium oxide devices. The currently proposed method for improving the on-off ratio of the enhancement MOSFET is realized by a gate trench structure or a FinFET (fin field-effect transistor) structure.
At present, the gallium oxide material is difficult to realize effective P-type doping, so that only unintentionally doped gallium oxide can be used as a channel when an enhancement MOSFET is manufactured. Unintentionally doped gallium oxide may inadvertently introduce some donor impurities during the material preparation process, resulting in poor insulating properties. Therefore, the leakage current of the enhanced gallium oxide MOSFET in an off state is large, and the on-off ratio of the device is not high.
The MOSFET of the gate groove structure and the FinFET structure has complex preparation process, and increases the difficulty and the cost of mass production of devices. Meanwhile, both methods need to be subjected to an etching process, and a large number of defects and surface states are introduced during etching, so that the performance of the device is greatly influenced. The contact part of the gate dielectric and the gallium oxide is easy to break down while the on-resistance is increased by influencing the carrier transport. For the method, the process for manufacturing the device is simple, and an etching process is not needed.
in addition, for a depletion-type gallium Oxide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), although the depletion-type gallium Oxide MOSFET can be easily implemented without using a complex structure or process, the existing device also has the problem of over-high threshold voltage (> 30V), which seriously affects the practical application of the device.
Disclosure of Invention
Technical problem to be solved
in view of the above, the present invention provides a method for fabricating a gallium oxide MOSFET to at least partially solve the above technical problems.
(II) technical scheme
according to an aspect of the present invention, there is provided a gallium oxide MOSFET semiconductor device, comprising:
A gallium oxide-based substrate;
A drain electrode and a source electrode arranged on the gallium oxide substrate;
Highly doped gallium oxide with a doping concentration of 10 is arranged in the gallium oxide-based substrate at least in the lower regions of the drain electrode and the source electrode17-1020cm-3；
The grid dielectric layer is arranged in the area which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;
and the grid electrode is arranged on the grid dielectric layer.
In a further embodiment, a gallium oxide-based substrate is a substrate for fabricating an enhanced gallium oxide MOSFET, comprising: a semi-insulating beta gallium oxide layer; unintentionally doped beta gallium oxide, arranged on the semi-insulating beta gallium oxide layer; and the doped gallium oxide is arranged in a partial region of the unintentionally doped beta gallium oxide, and the partial region is positioned below the source electrode and the drain electrode.
In a further embodiment, the gallium oxide-based substrate is a substrate for fabricating a depletion-mode MOSFET, comprising: semi-insulating layer beta gallium oxide; unintentionally doped beta gallium oxide, disposed on the semi-insulating layer beta gallium oxide; doped gallium oxide disposed over the unintentionally doped beta gallium oxide.
In further embodiments, the source and drain metals are high work function metals, which may be nickel, platinum or palladium or other metals with a work function higher than 4.5 eV.
In further embodiments, the doping element doping the gallium oxide is silicon Si, tin Sn, or other elements that cause the gallium oxide to exhibit N-type conductivity.
according to another aspect of the present invention, there is provided a method for manufacturing a gallium oxide enhancement type or depletion type MOSFET semiconductor device, comprising:
Preparing a gallium oxide-based substrate;
The gallium oxide-based substrate is provided with doped gallium oxide in at least partial region with the doping concentration of 1017-1020cm-3A gate electrode disposed on the gallium oxide-based substrate;
A drain and a source are formed over the doped gallium oxide of the gallium oxide substrate,
Forming a gate dielectric layer in a region which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;
And forming a grid electrode on the grid dielectric layer.
in a further embodiment, a gallium oxide-based substrate is prepared comprising: forming a semi-insulating layer beta gallium oxide; forming unintentionally doped beta gallium oxide on the semi-insulating layer beta gallium oxide; and forming doped gallium oxide in the part of the area which is not intentionally doped with the beta gallium oxide, wherein the area is positioned below the source electrode and the drain electrode.
In a further embodiment, a gallium oxide-based substrate is prepared comprising: forming a semi-insulating layer beta gallium oxide; forming unintentionally doped beta gallium oxide on the semi-insulating layer beta gallium oxide; and forming doped gallium oxide on the whole surface area of the unintentionally doped beta gallium oxide.
In a further embodiment, the source and drain metals are metals with work functions higher than 4.5 eV.
in further embodiments, the doping element doping the gallium oxide is silicon Si, tin Sn, or other elements that cause the gallium oxide to exhibit N-type conductivity.
(III) advantageous effects
In the invention, the originally used low-work-function source-drain electrode metal is replaced by the high-work-function metal in the scheme, so that the on-off ratio of the device can be improved, and the leakage current of the device in an off state can be reduced.
Compared with the common devices with the gate groove structure and the FinFET structure, the method does not need to use an etching process for the gallium oxide working part in the preparation process, so that the problems of large gate leakage current, advanced gate breakdown, reduced channel mobility and the like caused by the etching process to the devices do not exist in a new scheme.
Compared with the prior depletion type MOSFET device using low work function metal as a source electrode and a drain electrode, the depletion type MOSFET device can effectively solve the problem of overhigh threshold voltage of the device in the prior device.
the preparation process of the device is simple and mature, the process steps used by the device are mature semiconductor device preparation processes, and meanwhile, the device has the advantage of being compatible with a silicon material device preparation process.
Drawings
Fig. 1-6 are flow charts of methods for fabricating enhanced gallium oxide MOSFETs according to embodiments of the present invention.
Fig. 7-12 are flow charts of methods for fabricating depletion mode gallium oxide MOSFETs according to embodiments of the present invention.
Fig. 13 and 14 are schematic diagrams of isolation formation in a method of fabricating a gallium oxide MOSFET according to an embodiment of the invention.
Detailed Description
in order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
in the present invention, the technical terms referred to have the following meanings:
MOSFET: a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a Field-Effect Transistor that can be widely used in analog circuits and digital circuits.
Work function (work function): also known as work function, is defined in solid physics as: the least energy required to move an electron from the interior of the solid to the surface of the object. Work function generally refers to the work function of a metal.
Compared with a device without a gate groove structure and a FinFET structure, the insulation performance is poor due to the fact that some donor impurities are unintentionally introduced into the unintentionally doped gallium oxide in the material preparation process. Therefore, the leakage current of the enhanced gallium oxide MOSFET in an off state is large, and the on-off ratio of the device is not high. If the originally used low-work-function source-drain electrode metal is replaced by the high-work-function metal in the scheme, the on-off ratio of the device can be improved, and the leakage current of the device in an off state can be reduced.
In view of the above technical shortcomings, the present invention proposes a new device structure, which solves the above problems by forming tunneling source-drain contact using high work function metal and highly doped gallium oxide. High-work-function metal used for forming Schottky contact is used as a source-drain electrode material, gallium oxide in contact with the electrode is doped at a high concentration, the original source-drain contact property is changed, two potential barriers which are easy to tunnel are expected to be formed on the source-drain electrode, and a tunneling type source-drain contact is formed, so that the purposes of improving the on-off ratio of an enhancement type device and reducing the threshold voltage of a depletion type device are achieved.
The embodiment of the invention provides a gallium oxide MOSFET semiconductor device, which comprises:
A gallium oxide-based substrate;
a drain electrode and a source electrode arranged on the gallium oxide substrate;
The gallium oxide-based substrate is provided with doped gallium oxide at least in the lower regions of the drain electrode and the source electrode, and the doping concentration is 1017-1020cm-3；
The grid dielectric layer is arranged in the area which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;
and the grid electrode is arranged on the grid dielectric layer.
Wherein, the gallium oxide substrate can be a substrate based on an enhancement MOSFET or a depletion MOSFET, for example, the gallium oxide substrate is an enhancement gallium oxide MOSFET substrate, and includes: semi-insulating layer beta gallium oxide; unintentionally doped beta gallium oxide, disposed on the semi-insulating layer beta gallium oxide; and the doped gallium oxide is arranged in a partial region of the unintentionally doped beta gallium oxide, and the partial region is positioned below the source electrode and the drain electrode. Wherein, the preparation process of the semi-insulating substrate can adopt beta gallium oxide single crystal grown by pulling and pulling, the unintended doped gallium oxide buffer layer grows by adopting HVPE (hydride vapor phase epitaxy) method, the growth thickness can be 1 μm, the buffer layer grows on the (010) surface of the iron-doped beta gallium oxide semi-insulating substrate, the doped gallium oxide is formed by injecting Si atoms into a specific area of the gallium oxide through patterned ion injection, the injection depth is at least 100nm, and the doping concentration of the injected area is 1017-1020cm-3(ii) a The source and drain electrode metal can be deposited by electron beam evaporation or magneticallygrowing by a sputtering control method; the gate dielectric layer can be prepared by Atomic Layer Deposition (ALD) and has the thickness of 30 nm; and finally, growing the grid metal by an electron beam evaporation deposition or magnetron sputtering method. The etching process in the preparation process is implemented by inductively coupled plasma etching (ICP).
For example, the gallium oxide-based substrate is a depletion type MOSFET substrate, and comprises: semi-insulating layer beta gallium oxide; unintentionally doped beta gallium oxide, disposed on the semi-insulating layer beta gallium oxide; doped gallium oxide disposed over the unintentionally doped beta gallium oxide. The preparation process of the semi-insulating substrate can adopt beta gallium oxide single crystal grown by pulling, an unintended doped gallium oxide buffer layer grows by adopting an HVPE (hydride vapor phase epitaxy) method, the growth thickness can be 1 mu m, the buffer layer grows on a (010) surface of the iron-doped beta gallium oxide semi-insulating substrate, the doped gallium oxide injects Si atoms into the gallium oxide by an ion injection method to form, or a highly doped gallium oxide thin layer can be obtained by epitaxial growth directly by an epitaxial method such as MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy), and the injection depth or the epitaxial thin layer thickness is at least 100 nm; the source and drain electrode metal can be grown by an electron beam evaporation deposition or magnetron sputtering method, and the gate dielectric layer can be prepared by Atomic Layer Deposition (ALD) and has the thickness of 30 nm; and finally, growing the grid metal by an electron beam evaporation deposition or magnetron sputtering method. The etching process in the preparation process is implemented by inductively coupled plasma etching (ICP).
in the embodiment of the present invention, the source electrode and the drain electrode metal may be one of nickel, platinum or palladium, or other metals with work function larger than 4.5 eV.
Wherein, for the doped gallium oxide, the doping element of the doped gallium oxide is Si, and if the epitaxially grown doped gallium oxide is used, the doping element is Sn or Si, and the doping concentration is 1017-1020cm-3Within the scope, the purpose of the embodiment of the invention can be realized, namely two barriers which are easy to generate tunneling are formed on the source and the drain to form tunneling source and drain contact, so that the switch ratio of an enhancement type device is improved, and the threshold voltage of a depletion type device is reduced.
for better understanding of the present invention, the following specific embodiments are specifically illustrated in the accompanying drawings, but it should be understood that the specific details of the following embodiments are merely for describing the technical solutions of the present invention, and should not be construed as limiting the present invention.
fig. 1-6 illustrate a method for fabricating an enhanced gallium oxide MOSFET, which may include: inductively Coupled Plasma (ICP) etching is carried out on the gallium oxide substrate to realize device isolation, etching gases are Cl2 and Ar, the gas flow rates are respectively 15sccm and 5sccm, the Radio Frequency (RF) power in the etching process is 400W, the etching power is 60W, and the etching depth is larger than 300nm
local ion implantation and activation are carried out, an ion implantation window is manufactured through a photoetching development step, namely, the position where the ion implantation is not carried out is covered by photoresist, then Si atoms are implanted into the gallium oxide by using an ion implanter, the implantation depth is at least 100nm, and the highest implantation energy is 95 keV. N at 950 ℃ after implantation2and performing heat treatment in the atmosphere for 30mins to activate atoms implanted into the gallium oxide.
Growing and stripping a high-work-function metal source drain electrode; the window for the growth of the metal electrode is manufactured through the photoetching development step, namely the part where the electrode does not grow is covered by photoresist. Then, a metal nickel Ni film with high work function is grown by using an electron beam evaporation deposition or magnetron sputtering method, and then the product is soaked in acetone, so that redundant metal falls off, namely stripping.
Growing a gate dielectric; growing gate dielectric Al using Atomic Layer Deposition (ALD)2O3film thickness of 30nm
growing gate metal and stripping; the window for the growth of the metal electrode is manufactured through the photoetching development step, namely the part where the electrode does not grow is covered by photoresist. Then, growing a low-work-function titanium Ti film by using an electron beam evaporation deposition or magnetron sputtering method, and then soaking the product in acetone, so that redundant metal falls off, namely stripping.
And etching the gate dielectric on the source and drain metal, wherein the step can be prepared by using Inductively Coupled Plasma (ICP).
Fig. 7-12 illustrate a method of fabricating a depletion mode gallium oxide MOSFET, which may include the steps of:
Etching to realize device isolation, performing Inductively Coupled Plasma (ICP) etching on the gallium oxide substrate to realize device isolation, wherein the etching gases are Cl2 and Ar, the gas flow rates are respectively 15sccm and 5sccm, the Radio Frequency (RF) power in the etching process is 400W, the etching power is 60W, and the etching depth is more than 300nm
And (3) performing ion implantation and activation, implanting Si atoms into the gallium oxide by using an ion implanter, wherein the implantation depth is at least 100nm, and the highest implantation energy is 95 keV. N at 950 ℃ after implantation2And performing heat treatment in the atmosphere for 30mins to activate atoms implanted into the gallium oxide.
Growing a high work function metal source and drain electrode, and stripping a window for metal electrode growth manufactured by a photoetching development step, namely covering the part where the electrode does not grow by photoresist. Then, a metal nickel Ni film with high work function is grown by using an electron beam evaporation deposition or magnetron sputtering method, and then the product is soaked in acetone, so that redundant metal falls off, namely stripping.
growing gate dielectric the gate dielectric Al is grown using an Atomic Layer Deposition (ALD) method2O3Film thickness of 30nm
growing gate metal, and stripping a window for metal electrode growth manufactured by a photoetching development step, namely covering the part where the electrode does not grow by photoresist. Then, growing a low-work-function titanium Ti film by using an electron beam evaporation deposition or magnetron sputtering method, and then soaking the product in acetone, so that redundant metal falls off, namely stripping.
And etching the gate dielectric on the source and drain metal, wherein the step can be prepared by using Inductively Coupled Plasma (ICP) etching.
Fig. 13 and 14 show a method for fabricating a depletion mode gallium oxide substrate according to an embodiment, in which a highly doped gallium oxide layer is epitaxially grown on an unintentionally doped gallium oxide layer by using an epitaxial method such as MOCVD or MBE, and then device isolation is performed by etching.
the above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A gallium oxide MOSFET semiconductor device, comprising:
A gallium oxide-based substrate;
a drain electrode and a source electrode arranged on the gallium oxide substrate;
Highly doped gallium oxide with a doping concentration of 10 is arranged in the gallium oxide-based substrate at least in the lower regions of the drain electrode and the source electrode17-1020cm-3；
The grid dielectric layer is arranged in the area which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;
And the grid electrode is arranged on the grid dielectric layer.
2. The device of claim 1,
The gallium oxide-based substrate is used for manufacturing an enhanced gallium oxide MOSFET and comprises:
a semi-insulating beta gallium oxide layer;
unintentionally doped beta gallium oxide, arranged on the semi-insulating beta gallium oxide layer;
and the doped gallium oxide is arranged in a partial region of the unintentionally doped beta gallium oxide, and the partial region is positioned below the source electrode and the drain electrode.
3. the device of claim 1,
the gallium oxide-based substrate is used for manufacturing a depletion type MOSFET and comprises:
semi-insulating layer beta gallium oxide;
unintentionally doped beta gallium oxide, disposed on the semi-insulating layer beta gallium oxide;
Doped gallium oxide disposed over the unintentionally doped beta gallium oxide.
4. The device of claim 1, wherein the source and drain metals are high work function metals, such as nickel, platinum or palladium or other metals with work function higher than 4.5 eV.
5. The device of claim 1, wherein the doping element of the doped gallium oxide is silicon (Si), tin (Sn) or other element that can cause gallium oxide to exhibit N-type conductivity.
6. A method for preparing a gallium oxide enhancement type or depletion type MOSFET semiconductor device comprises the following steps:
preparing a gallium oxide-based substrate;
The gallium oxide-based substrate is provided with doped gallium oxide in at least partial region with the doping concentration of 1017-1020cm-3A gate electrode disposed on the gallium oxide-based substrate;
A drain and a source are formed over the doped gallium oxide of the gallium oxide substrate,
Forming a gate dielectric layer in a region which is not covered with the source electrode and the drain electrode on the gallium oxide substrate;
And forming a grid electrode on the grid dielectric layer.
7. The method of claim 6,
Preparing a gallium oxide-based substrate comprising:
Forming a semi-insulating layer beta gallium oxide;
forming unintentionally doped beta gallium oxide on the semi-insulating layer beta gallium oxide;
And forming doped gallium oxide in the part of the area which is not intentionally doped with the beta gallium oxide, wherein the area is positioned below the source electrode and the drain electrode.
8. The method of claim 6,
Preparing a gallium oxide-based substrate comprising:
forming a semi-insulating layer beta gallium oxide;
Forming unintentionally doped beta gallium oxide on the semi-insulating layer beta gallium oxide;
And forming doped gallium oxide on the whole surface area of the unintentionally doped beta gallium oxide.
9. The method of claim 6, wherein the source and drain metals are metals with work functions higher than 4.5 eV.
10. The method according to claim 6, wherein the doping element of the doped gallium oxide is silicon (Si), tin (Sn) or other elements capable of enabling the gallium oxide to show N-type conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910879776.8A CN110571275A (en) | 2019-09-17 | 2019-09-17 | preparation method of gallium oxide MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910879776.8A CN110571275A (en) | 2019-09-17 | 2019-09-17 | preparation method of gallium oxide MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110571275A true CN110571275A (en) | 2019-12-13 |
Family
ID=68780799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910879776.8A Pending CN110571275A (en) | 2019-09-17 | 2019-09-17 | preparation method of gallium oxide MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110571275A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111243962A (en) * | 2020-01-20 | 2020-06-05 | 中国电子科技集团公司第五十五研究所 | Gallium oxide high-electron-mobility heterojunction transistor and preparation method thereof |
| CN113224169A (en) * | 2021-05-07 | 2021-08-06 | 电子科技大学 | Folding grid oxidation gallium-based field effect transistor |
| CN113555444A (en) * | 2021-07-06 | 2021-10-26 | 浙江芯国半导体有限公司 | High-quality gallium oxide semiconductor device and preparation method thereof |
| CN113629148A (en) * | 2021-06-24 | 2021-11-09 | 湖南大学 | Double-gate enhanced gallium oxide MESFET device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103782392A (en) * | 2011-09-08 | 2014-05-07 | 株式会社田村制作所 | Ga2O3 semiconductor element |
| US20160141372A1 (en) * | 2013-06-17 | 2016-05-19 | Tamura Corporation | Ga2O3 SEMICONDUCTOR ELEMENT |
| CN106796889A (en) * | 2014-08-29 | 2017-05-31 | 株式会社田村制作所 | Semiconductor element and its manufacture method |
| CN107078063A (en) * | 2014-08-29 | 2017-08-18 | 株式会社田村制作所 | Semiconductor element and crystal laminate structure |
-
2019
- 2019-09-17 CN CN201910879776.8A patent/CN110571275A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103782392A (en) * | 2011-09-08 | 2014-05-07 | 株式会社田村制作所 | Ga2O3 semiconductor element |
| US20160141372A1 (en) * | 2013-06-17 | 2016-05-19 | Tamura Corporation | Ga2O3 SEMICONDUCTOR ELEMENT |
| CN106796889A (en) * | 2014-08-29 | 2017-05-31 | 株式会社田村制作所 | Semiconductor element and its manufacture method |
| CN107078063A (en) * | 2014-08-29 | 2017-08-18 | 株式会社田村制作所 | Semiconductor element and crystal laminate structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111243962A (en) * | 2020-01-20 | 2020-06-05 | 中国电子科技集团公司第五十五研究所 | Gallium oxide high-electron-mobility heterojunction transistor and preparation method thereof |
| CN111243962B (en) * | 2020-01-20 | 2022-07-15 | 中国电子科技集团公司第五十五研究所 | Gallium oxide high-electron-mobility heterojunction transistor and preparation method thereof |
| CN113224169A (en) * | 2021-05-07 | 2021-08-06 | 电子科技大学 | Folding grid oxidation gallium-based field effect transistor |
| CN113224169B (en) * | 2021-05-07 | 2023-02-07 | 电子科技大学 | Folding grid oxidation gallium-based field effect transistor |
| CN113629148A (en) * | 2021-06-24 | 2021-11-09 | 湖南大学 | Double-gate enhanced gallium oxide MESFET device and manufacturing method thereof |
| CN113555444A (en) * | 2021-07-06 | 2021-10-26 | 浙江芯国半导体有限公司 | High-quality gallium oxide semiconductor device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10784338B2 (en) | Field effect transistor devices with buried well protection regions | |
| US10868134B2 (en) | Method of making transistor having metal diffusion barrier | |
| CN110571275A (en) | preparation method of gallium oxide MOSFET | |
| WO2017123999A1 (en) | Enhancement mode iii-nitride devices having an al(1-x)sixo gate insulator | |
| CN113196499B (en) | Vertical silicon carbide power MOSFET and IGBT and manufacturing method thereof | |
| CN106158948B (en) | III-nitride enhanced HEMT device and manufacturing method thereof | |
| US10177239B2 (en) | HEMT transistor | |
| CN113380623A (en) | Method for realizing enhanced HEMT (high Electron mobility transistor) through p-type passivation | |
| CN102082176A (en) | Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof | |
| CN112447836A (en) | High electron mobility transistor with high voltage endurance capability | |
| CN104701359A (en) | Vertical-structure AlGaN/GaN HEMT device and manufacturing method thereof | |
| CN112289858A (en) | III-nitride enhanced HEMT device and preparation method thereof | |
| CN111081763B (en) | Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof | |
| CN111799326B (en) | Novel transistor structure for regulating and controlling two-dimensional electron gas concentration and manufacturing method | |
| CN113745332A (en) | Enhanced high electron mobility transistor based on ferroelectric group III nitride polarization reversal | |
| KR101172857B1 (en) | Enhancement normally off nitride smiconductor device and manufacturing method thereof | |
| CN116959991A (en) | Field effect transistor and preparation method thereof and method for preparing groove structure in drift layer of field effect transistor | |
| TWI829085B (en) | Sic mosfet with reduced channel length and high vth | |
| CN107591444B (en) | Enhancement transistor and manufacturing method thereof | |
| CN210272373U (en) | High electron mobility transistor with high voltage endurance capability | |
| CN108346687B (en) | Gallium nitride-based high electron mobility transistor | |
| CN113972263A (en) | Enhanced AlGaN/GaN HEMT device and preparation method thereof | |
| KR102067596B1 (en) | Nitride semiconductor and method thereof | |
| CN111599865B (en) | GaN-based P-channel MOSFET and preparation method thereof | |
| US20230108909A1 (en) | Semiconductor Device, Manufacturing Method and Electronic Equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20191213 |
|
| WD01 | Invention patent application deemed withdrawn after publication |