CN117238964A - Super-junction SiC MOS with homoheterojunction freewheel channel and preparation method - Google Patents
Super-junction SiC MOS with homoheterojunction freewheel channel and preparation method Download PDFInfo
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Abstract
The invention provides a super-junction SiC MOS with a homoheterojunction freewheel channel and a preparation method thereof, wherein the super-junction SiC MOS comprises the following components: an N-base layer, a P column, and a first n+ layer; the N-base layer is abutted against the gate oxide layer; the first N+ layer is located in a region surrounded by the P-body layer and the N-base layer. The P column is positioned between the P-body layer and the substrate and is adjacent to the N-drift layer, the P-body layer and the substrate. According to the invention, the reverse freewheeling channel is arranged below the grid groove, when the SiC MOS is in a reverse state, current flows from the source electrode to the first N+ layer, then flows from the first N+ layer to the N-base layer, and finally flows from the N-base layer to the N-drift layer to the drain electrode, so that a reverse freewheeling loop is formed, and compared with a body diode of the SiC MOS, the reverse freewheeling loop has lower starting voltage, the chip area can be saved, the production cost is reduced, and the safety and stability of the SiC MOS are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a super-junction SiC MOS with a homoheterojunction freewheel channel and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. The SiC power device has a series of advantages of high input impedance, high switching speed, high working frequency, high voltage resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high frequency, power amplifiers and the like.
As a switching device, a reverse freewheeling diode is often required in a circuit due to oscillations or voltage spikes, avoiding degradation of the device. There are now mainly the following approaches for using freewheeling diodes: diodes are connected in parallel in the circuit, but this can lead to the circuit adding additional switched capacitance and gate charge degradation, increasing the energy loss of the whole circuit; the freewheeling diode and the MOSFET are made into a set of facilities when the device is packaged, but the area utilization rate of the chip is reduced, and meanwhile, the use reliability of the device is reduced due to extra current leakage of the device caused by integration of a plurality of systems. The parasitic body diode of the switching element is utilized as a freewheeling diode when the reverse voltage is applied, but for the traditional SiC MOSFET, the use of the body diode brings about some characteristics: firstly, the threshold voltage of the self diode of the SiC MOSFET is higher and is about 3V, so that the extra energy consumption of the circuit is improved, and the energy utilization rate is reduced; secondly, the conduction of the body diode can lead to bipolar degradation of the device, and the bipolar degradation is caused by the fact that the defects in the SiC material are increased due to the recombination of electron hole pairs, the doped region drifts, so that various leakage current amounts of the permanent MOSFET are increased, and permanent damage failure is finally formed. In order to reduce the size of transistor devices, reduce on-resistance, reduce dynamic loss, improve the energy-saving characteristics and improve the cost performance of transistors, a SiC MOSFET with a novel structure is currently needed to improve the switching frequency of a circuit and reduce the switching loss in the circuit.
Disclosure of Invention
The invention aims to provide a super-junction SiC MOS with a homoheterojunction freewheel channel and a preparation method, wherein a reverse freewheel channel is arranged below a grid groove, when the SiC MOS is in a reverse state, current flows from a source electrode to a first N+ layer, then flows from the first N+ layer to an N-base layer, flows from the N-base layer to an N-drift layer and finally flows to a drain electrode, a reverse freewheel loop is formed, and compared with a body diode of the SiC MOS, the reverse freewheel loop has lower starting voltage, the chip area can be saved, the production cost is reduced, and the safety and stability of the SiC MOS are improved.
A superjunction SiC MOS having homoheterojunction freewheel channels, comprising: an N-base layer, a P column, and a first n+ layer;
the N-base layer is abutted against the gate oxide layer;
the first N+ layer is located in a region surrounded by the P-body layer and the N-base layer.
The P column is positioned between the P-body layer and the substrate and is adjacent to the N-drift layer, the P-body layer and the substrate.
Preferably, the P-body layer includes: a first extension part positioned between the source electrode and the N-drift layer and a second extension part positioned between the N-drift layer and the N+ layer and the N-base layer;
the first extension is adjacent to the source and the N-drift layer;
the second extension is adjacent to the N-drift layer, the n+ layer, and the N-base layer.
Preferably, the thickness of the N-base layer is 80-100nm.
Preferably, the oxide layer on the right side of the gate has a smaller thickness than the oxide layer under the gate.
Preferably, the thickness of the oxide layer positioned on the right side of the gate is 40-50nm.
Preferably, the thickness of the oxide layer below the grid electrode is 160-200nm.
Preferably, the doping concentration of the N-base layer is smaller than that of the N-drift layer.
Preferably, the doping concentration of the P column is 2×10 16 -6×10 16 cm -3 。
Preferably, the method further comprises: a source electrode, a drain electrode, a grid electrode, a substrate, a P-well layer, a second N+ layer and a P+ layer;
the drain electrode is positioned below the substrate;
the substrate is positioned below the N-drift layer and the P column;
the N-drift layer is positioned below the P-well layer and the P-body;
the P-well layer is positioned below the second N+ layer and the P+ layer;
the second N+ layer and the P+ layer are located below the source electrode;
the grid electrode is positioned above the first N+ layer and the N-base layer;
the source is located above the P-body layer, the first n+ layer, the second n+ layer, and the p+ layer.
A preparation method of a super junction SiC MOS with a homoheterojunction freewheel channel comprises the following steps:
a P column and an N-drift layer are epitaxially arranged above the substrate;
etching a groove on the upper layer of the N-drift layer;
forming a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer by ion implantation on the upper layer of the N-drift layer;
depositing polysilicon and an oxide layer in the trench to form a gate;
etching the polysilicon;
and depositing a source electrode and a drain electrode.
According to the invention, the reverse freewheeling circuit formed by the source electrode, the first N+ layer, the N-base layer and the N-drift layer is arranged below the grid electrode, when the super junction SiC MOS is connected with reverse current, the barrier between the N-base layer and the N-drift layer is lower than that of the PN junction, so that the starting voltage of the reverse freewheeling circuit is lower than that of the body diode, the current flowing from the source electrode to the drain electrode can preferentially pass through the reverse freewheeling circuit, the starting of the body diode can be inhibited to a certain extent, the switching loss can be reduced, and compared with the method in the prior art that the SiC MOSFET and the SBD or the JFET are integrated in an anti-parallel mode to play a role of reverse freewheeling, the technological process is very simple, the manufactured chip area is small, and the reliability and stability of the SiC MOS are higher.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a super junction SiC MOS structure of the invention;
fig. 2 is a schematic diagram of a process flow of preparing a super junction SiC MOS according to the present invention;
fig. 3 is a schematic structural diagram of a preparation flow of the super junction SiC MOS of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The prior art generally uses a body diode of the MOSFET or an external parallel diode to realize the reverse freewheeling of the MOSFET. The body diode of the MOSFET is also called parasitic diode, the body diode can play a role in reverse protection and follow current when in heavy current driving and inductive load, and the forward conduction voltage drop is about 2.7-3V generally, because the body diode exists, the MOSFET cannot simply see the function of a switch in a circuit, such as a charging circuit, the charging is completed, after a power supply is removed, the battery can reversely supply power to the outside, the battery generates serious heat under the condition of heavy current, and meanwhile, the energy waste is caused, so that the energy efficiency of the whole circuit is low.
The freewheeling diode is a special diode that is composed of a PN junction diode. The circuit has the main function of playing a role of freewheeling in the circuit, and can effectively prevent the flow of reverse current and protect the stability and the safety of the circuit. The working principle of the freewheeling diode is to realize the prevention of reverse current by combining the forward conduction characteristic of the PN junction diode and the negative resistance characteristic of the MOSFET. The MOSFET works at a first quadrant, and the PN diode is reversely biased to be cut off; when the MOSFET is operated at the third quadrant, the PN diode turns on at an appropriate voltage drop (Si MOSFET vf=0.7V-1V, sic MOSFET vf=2.7V-3.0V) for freewheeling. The reverse leakage current of the freewheeling diode is very small, so that the stability and the safety of the circuit can be effectively protected. Second, its on-resistance is small, which can reduce the power consumption and heat loss of the circuit. In addition, the response speed is high, the flow of reverse current can be instantaneously prevented, the components of the circuit are protected from being damaged, and the stability and the safety of the circuit are improved. However, the chip area formed by antiparallel integration of the SiC MOS and the flywheel diode is large, and the current industrial requirements cannot be met.
According to the invention, the reverse freewheeling circuit formed by the source electrode, the first N+ layer, the N-base layer and the N-drift layer is arranged below the grid electrode, when the super junction SiC MOS is connected with reverse current, the barrier between the N-base layer and the N-drift layer is lower than that of the PN junction, so that the starting voltage of the reverse freewheeling circuit is lower than that of the body diode, the current flowing from the source electrode to the drain electrode can preferentially pass through the reverse freewheeling circuit, the starting of the body diode can be inhibited to a certain extent, the switching loss can be reduced, and compared with the method in the prior art that the SiC MOSFET and the SBD or the JFET are integrated in an anti-parallel mode to play a role of reverse freewheeling, the technological process is very simple, the manufactured chip area is small, and the reliability and stability of the SiC MOS are higher.
Example 1
A superjunction SiC MOS having homoheterojunction freewheel channels, see fig. 1, comprising: an N-base layer, a P-pillar (P-pilar) and a first N+ layer;
the N-base layer is abutted against the gate oxide layer;
the first n+ layer is located in a region surrounded by the P-body layer and the N-base layer.
The P-pillars are located between and contiguous with the P-body layer and the substrate.
MOSFETs can be classified into planar gate MOSFETs and superjunction MOSFETs according to manufacturing processes, and a planar structure transistor has a disadvantage in that if a rated voltage is increased, a drift layer becomes thick, and thus on-resistance increases. The nominal voltage of the MOSFET depends on the width of the drift region in the vertical direction and the doping parameters. To increase the voltage rating, the width of the drift region is typically increased while the doping concentration is reduced, but this results in a significant increase in the on-resistance of the MOSFET. In order to solve the problem of the increase of on-resistance due to the increase of rated voltage, the super junction structure MOSFET has a structure in which a plurality of vertical PN junctions are arranged at D terminal and S terminal, with the result that low on-resistance is realized while maintaining high voltage. The existence of the super junction breaks through the theoretical limit of silicon greatly, and the higher the rated voltage is, the more obviously the on-resistance is reduced.
The heterojunction of the semiconductor is a special PN junction, and is formed by sequentially depositing more than two layers of different semiconductor material films on the same base, wherein the materials have different energy band gaps, and can be compounds such as gallium arsenide or semiconductor alloys such as silicon-germanium. The heterojunction is an interfacial region formed by the contact of two different semiconductors. Heterojunctions can be classified into homoheterojunctions (P-junctions or N-junctions) and heteroheterojunctions (P-N or P-N) according to the conductivity types of the two materials, and multilayer heterojunctions are called heterostructures. The conditions under which the heterojunction is typically formed are: the two semiconductors have similar crystal structures, similar atomic spacing and thermal expansion coefficients. Heterojunction can be fabricated by interfacial alloy, epitaxial growth, vacuum deposition, etc. The heterojunction has excellent photoelectric characteristics which cannot be achieved by PN junctions of two semiconductors, so that the heterojunction is suitable for manufacturing ultra-high-speed switching devices, solar cells, semiconductor lasers and the like.
The potential barrier to be overcome by the homotype heterojunction consisting of the N-drift layer and the N-base layer is far lower than the potential barrier to be overcome by the heterojunction consisting of the P-type semiconductor and the N-type semiconductor (body diode), and compared with the traditional freewheel channel, the freewheel channel provided by the invention has lower starting voltage and small switching loss.
When the MOSFET is in an off state, a reverse current is generated in the tube due to the action of reverse voltage, the reverse current is called as the reverse recovery current of the MOSFET, the reverse recovery current of the MOSFET has important influence on the working performance and reliability of the MOSFET, the magnitude of the reverse recovery current of the MOSFET is related to the structural parameters, the working temperature, the external voltage and other factors of the MOSFET, when the MOSFET works in a circuit with higher frequency, if the reverse recovery performance is insufficient, the MOSFET is extremely easy to damage, and the high-frequency circuit can be adapted only by improving the reverse recovery speed of the MOSFET.
The MOSFET inevitably has switching losses during switching, including on losses and off losses. The conduction loss refers to the power loss generated when the power tube is turned on from off. The cut-off loss refers to the power loss generated when the power tube is turned on to off. The switching loss includes an on loss and an off loss, and when the non-ideal switching tube is on, the voltage of the switching tube does not immediately drop to zero, but has a falling time, and meanwhile, the current of the switching tube does not immediately rise to the load current, and also has a rising time. In this period, the current and voltage of the switching tube have an overlapping region, and loss, namely, turn-on loss, is generated. Switching losses are losses that occur when parasitic capacitances are charged and discharged during switching operations of large MOSFETs in switching power supplies.
In order to improve the switching speed of the MOSFET and reduce the switching loss of the MOSFET, a reverse freewheeling circuit formed by a source electrode, a first N+ layer, an N-base layer and an N-drift layer is arranged below a grid electrode, when the SiC MOS is connected with reverse current, the barrier between the N-base layer and the N-drift layer is lower than a PN junction, so that the starting voltage of a reverse freewheeling channel is lower than that of a body diode, current flowing from the source electrode to the drain electrode can preferentially pass through the reverse freewheeling channel, the starting of the body diode can be inhibited to a certain extent, the switching loss can be reduced, compared with the method of integrating the SiC MOSFET and an SBD or JFET in an antiparallel mode in the prior art, the process flow is very simple, the manufactured chip area is small, the reliability and stability of the SiC MOS are higher, the circuit can be protected, and the service life of the circuit is prolonged.
Preferably, the P-body layer includes: a first extension part positioned between the source electrode and the N-drift layer and a second extension part positioned between the N-drift layer and the N+ layer and the N-base layer;
the first extension is adjacent to the source and the N-drift layer;
the second extension is adjacent to the N-drift layer, the n+ layer, and the N-base layer.
The first function of the P-body layer is to control the turn-off of the reverse freewheeling channel, and when the SiC MOS is in the off state, the P-body layer can deplete the N-base layer, thereby closing the current channel from the first n+ layer to the N-base layer, and protecting the SiC MOS from breakdown by large currents.
The second role of the P-body layer is to protect the gate oxide layer at the bottom corners of the gate trench, which is inevitably subject to defects due to the technical limitations of the prior art, such as small spots and pinholes caused by uneven local growth rate of the oxide layer, after the gate oxide layer is formed by oxidation. Defects in the oxide layer are more likely to occur, especially at the trench bottom corners. The defect of the gate oxide layer causes the phenomenon that electric field lines are easily concentrated at the corners of the bottom of the trench gate, so that the electric field intensity at the corners of the bottom of the trench is far greater than that at other positions of the trench, and the problem that the gate oxide layer is most easily broken down at the corners of the bottom of the trench gate is solved. Therefore, the P-body layer is arranged below the gate oxide layer, so that the problem of electric field distribution concentration at the bottom corner of the gate trench can be reduced, and the reliability of the gate oxide layer is improved.
Preferably, the thickness of the N-base layer is 80-100nm.
In order to ensure that the N-base layer can be completely consumed by the P-body layer in the off state, if the thickness of the N-base layer is too large, the N-base layer cannot be consumed by the P-body layer, large-area leakage of the SiC MOS is caused, siC MOS loss is caused, if the thickness of the N-base layer is too small, the N-base layer is too early consumed by the P-body layer, and a sufficiently large freewheel loop cannot be provided, so that the minimum thickness of the N-base layer cannot be lower than 80nm and the maximum thickness cannot exceed 100nm.
Preferably, the oxide layer on the right side of the gate has a smaller thickness than the oxide layer under the gate.
Preferably, the oxide layer on the right side of the gate has a thickness of 40-50nm.
Preferably, the oxide layer below the gate has a thickness of 160-200nm.
The thickness of the oxide layer on the right side of the gate is the thickness of the oxide layer under the gateFor example, when the withstand voltage of the SiC MOS is 1200V, the thickness of the gate oxide layer on the right side wall of the trench is 40nm, and the thickness of the gate oxide layer on the bottom of the trench is 200nm, because the thinner the oxide layer on the right side of the gate is, the easier an inversion layer is induced in the P-well layer, and when the SiC MOS works normally, the current can flow from the drain to the substrate, and thenThe substrate flows to the P-well layer, then flows to the second N+ layer from the P-well layer and finally flows to the source electrode, the thin gate oxide layer can improve the current density of the SiC MOS, but the voltage resistance of the gate oxide layer which is too thin is insufficient, so the thickness of the oxide layer on the right side of the gate cannot be lower than 40nm.
Due to technical limitations of the prior art after the gate oxide is oxidized, defects in the gate oxide, such as small spots and pinholes in the oxide caused by uneven local growth rates of the oxide, are unavoidable. Defects in the oxide layer are more likely to occur, especially at the trench bottom corners. The defect of the grid oxide layer causes the phenomenon that electric field lines are easily concentrated at the corner of the bottom of the trench, so that the electric field intensity at the corner of the bottom of the trench is far greater than that at other positions of the trench, and the breakdown of the grid oxide layer is most easily generated at the corner of the bottom of the trench of the grid, so that the thickness of the oxide layer below the grid is greater than that of the oxide layer on the right side of the grid, and the breakdown problem of the grid oxide layer can be avoided, and the reliability of the SiC MOS device and the safety of a circuit are improved.
Preferably, the doping concentration of the N-base layer is less than the doping concentration of the N-drift layer.
The concentration of the N-base layer was 10 16 cm -3 。
The substrate of the PN junction is divided into P type and N type, and +is heavily doped (high doping concentration), is lightly doped (low doping concentration), and P type doped with IIIA group elements, such as: boron, aluminum, gallium, indium, thallium. N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc). The doping concentration of heavy doping is 10 18 cm -3 The light doping concentration is lower than that of the heavy doping, because current can flow from the N-base layer to the N-drift layer only when the doping concentration of the N-base layer is slightly lower than that of the N-drift layer, the N-base layer is light doping, and in the embodiment of the invention, the N-drift layer has higher doping concentration than that of the N-drift layer in the planar structure due to the superjunction structure, and the doping concentration of the N-drift layer is 4 multiplied by 10 16 cm -3 Therefore, the doping concentration of the N-base layer is correspondingly increased, and the doping concentration of the N-base layer is 10 16 cm -3 。
Preferably, the doping concentration of the P column is 2×10 16 -6×10 16 cm -3 。
The P-pillar is lightly doped, if the doping concentration of the P-pillar is too low or too low, the charge in the SiC MOS is not balanced, and the electrical performance of the SiC MOS is affected, so the doping concentration of the P-pillar is set according to the doping concentration of the N-drift layer, and as a preferred embodiment, the doping concentration of the P-pillar is set to 2×10 16 -6×10 16 cm -3 。
Preferably, the method further comprises: a source electrode (S), a drain electrode (D), a grid electrode (G), a substrate (N-sub), a P-well layer, a second N+ layer and a P+ layer;
the drain electrode is positioned below the substrate;
the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.
The substrate is positioned below the N-drift layer (drift layer) and the P column;
the electric field distribution of the N-drift layer plays a key role in the conduction characteristics and current control of the MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. During MOSFET operation, current between source and drain is transferred primarily through the N-drift layer. The doping type and concentration of the N-drift layer determine the conduction type (N-type or P-type) and magnitude of the current. The structure and characteristics of the N-drift layer directly influence the current control capability of the MOS transistor. By adjusting the shape, the size and the doping concentration of the N-drift layer, accurate control of current can be realized, so that the requirements of different applications are met.
The N-drift layer is positioned below the P-well layer and the P-body;
the P-well layer is positioned below the second N+ layer and the P+ layer;
the second N+ layer and the P+ layer are positioned below the source electrode;
the grid electrode is positioned above the first N+ layer and the N-base layer;
the gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.
The source is located above the P-body layer, the first n+ layer, the second n+ layer, and the p+ layer.
The source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
Example 2
A method for preparing a super junction SiC MOS having a homoheterojunction freewheel channel, referring to fig. 2 and 3, includes:
s100, a P column and an N-drift layer are epitaxially grown above a substrate;
an epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. According to the different phases of the growth source, the epitaxial growth modes are divided into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During the implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, and amorphization occurs to form a surface amorphous silicon layer; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The chemical vapor phase epitaxy and Chemical Vapor Deposition (CVD) principles are basically the same, and are all processes for depositing films by utilizing chemical reaction on the surface of a wafer after gas mixing; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, etching a groove on the upper layer of the N-drift layer;
the invention forms a groove by etching the upper layer of the N-drift layer by an etching method. Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is an absolute chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor. So that the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S300, forming a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer by ion implantation on the upper layer of the N-drift layer;
the invention adopts an ion implantation mode to implant ions on the upper layer of the N-drift layer to form a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S400, depositing polysilicon and an oxide layer in the groove to form a grid;
the deposited grid adopts a polysilicon deposition method, namely forming a grid electrode and local connection lines on the first layer of polysilicon (Poly 1) stacked by silicideA second layer of polysilicon (Poly 2) forms contact plugs between the source/drain and the cell lines. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) process by depositing arsenic trioxide (AH) in a reaction chamber (i.e., in a furnace tube) 3 ) Phosphorus trihydride (PH) 3 ) Or diborane (B) 2 H 6 ) The doping gas of the silicon material is directly input into the silicon material gas of silane or DCS, so that the polysilicon doping process of the in-situ low-pressure chemical vapor deposition can be performed. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates of both deposition processes areIs mainly determined by the temperature during deposition.
S500, etching polysilicon;
polysilicon gate MOSFETs require polysilicon etching to form the gate pattern. MOSFETs with high k and metal gate require etching of the polysilicon. To protect the gate oxide from damage, the etching of the silicon gate is typically divided into several steps: main etching, landing etching and over etching. The main etch typically has a relatively high etch rate but a relatively small selection of silicon oxide. The cross-sectional profile and critical dimensions of the silicon gate can be substantially determined by the main etch. The landing etch typically has a relatively high selectivity to the gate oxide to ensure that the gate oxide is not damaged. Once the gate oxide is reached, an over-etch step with a higher selectivity to silicon oxide must be performed to ensure that the residual silicon is removed without damaging the gate oxide. Cl 2 HBr, HCl is the primary gas for silicon gate etching.
The etching process of the polysilicon gate must have a high selectivity to the underlying gate oxide and have very good uniformity and repeatability. A high degree of anisotropy is also required because the polysilicon gate acts as a barrier during the source/drain implant. The sloped sidewalls cause doping of the underlying portion of the polysilicon gate structure.
Polysilicon etching is divided into three steps, the first step being pre-etching to remove natural oxide layers, hard masking layers (such as SiON) and surface contaminants to obtain a uniform etch (which reduces surface defects caused by contaminants acting as micro masking layers in etching). Next is the main etch to the endpoint. This step serves to etch away most of the polysilicon film without damaging the gate oxide and achieving the desired anisotropic sidewall profile. The final step is over-etching to remove etching residues and remaining polysilicon and to ensure a high selectivity to the gate oxide. This step should avoid the formation of micro-trenches in the gate oxide layer around the polysilicon.
S600, depositing a source electrode and a drain electrode.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses to the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrateSolid deposits are formed and the gas phase by-products generated are detached from the substrate surface. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C 4 ，H 2 ，CH 4 And forming a coating layer on the surface of the substrate through chemical reaction of the gases.
According to the invention, the reverse freewheeling circuit formed by the source electrode, the first N+ layer, the N-base layer and the N-drift layer is arranged below the grid electrode, when the super junction SiC MOS is connected with reverse current, the barrier between the N-base layer and the N-drift layer is lower than that of the PN junction, so that the starting voltage of the reverse freewheeling circuit is lower than that of the body diode, the current flowing from the source electrode to the drain electrode can preferentially pass through the reverse freewheeling circuit, the starting of the body diode can be inhibited to a certain extent, the switching loss can be reduced, and compared with the method in the prior art that the SiC MOSFET and the SBD or the JFET are integrated in an anti-parallel mode to play a role of reverse freewheeling, the technological process is very simple, the manufactured chip area is small, and the reliability and stability of the SiC MOS are higher.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A superjunction SiC MOS having a homoheterojunction freewheel channel, comprising: an N-base layer, a P column, and a first n+ layer;
the N-base layer is abutted against the gate oxide layer;
the first N+ layer is located in a region surrounded by the P-body layer and the N-base layer.
The P column is positioned between the P-body layer and the substrate and is adjacent to the N-drift layer, the P-body layer and the substrate.
2. A superjunction SiC MOS having homoheterojunction freewheel channels as claimed in claim 1, characterized in that said P-body layer comprises: a first extension part positioned between the source electrode and the N-drift layer and a second extension part positioned between the N-drift layer and the N+ layer and the N-base layer;
the first extension is adjacent to the source and the N-drift layer;
the second extension is adjacent to the N-drift layer, the n+ layer, and the N-base layer.
3. A superjunction SiC MOS having a homoheterojunction freewheel channel according to claim 1 characterized in that the thickness of the N-base layer is 80-100nm.
4. A superjunction SiC MOS having a homoheterojunction freewheel channel according to claim 1 characterized in that the thickness of the oxide layer on the right side of the gate is smaller than the oxide layer under the gate.
5. The super junction SiC MOS of claim 4 wherein the oxide layer on the right side of the gate has a thickness of 40-50nm.
6. A superjunction SiC MOS having a homoheterojunction freewheel channel according to claim 4 characterized in that the oxide layer thickness under the gate is 160-200nm.
7. The super junction SiC MOS with homoheterojunction freewheel channel of claim 1 characterized in that the doping concentration of the N-base layer is smaller than the doping concentration of the N-drift layer.
8. The super-junction SiC MOS having a homoheterojunction freewheel channel of claim 1 characterized in that the doping concentration of the P-pillars is 2×10 16 -6×10 16 cm -3 。
9. The super junction SiC MOS having a homoheterojunction freewheel channel of claim 1 further comprising: a source electrode, a drain electrode, a grid electrode, a substrate, a P-well layer, a second N+ layer and a P+ layer;
the drain electrode is positioned below the substrate;
the substrate is positioned below the N-drift layer and the P column;
the N-drift layer is positioned below the P-well layer and the P-body;
the P-well layer is positioned below the second N+ layer and the P+ layer;
the second N+ layer and the P+ layer are located below the source electrode;
the grid electrode is positioned above the first N+ layer and the N-base layer;
the source is located above the P-body layer, the first n+ layer, the second n+ layer, and the p+ layer.
10. The preparation method of the super-junction SiC MOS with the homoheterojunction freewheel channel is characterized by comprising the following steps of:
a P column and an N-drift layer are epitaxially arranged above the substrate;
etching a groove on the upper layer of the N-drift layer;
forming a P-body layer, a first N+ layer, an N-base layer, a second N+ layer, a P+ layer and a P-well layer by ion implantation on the upper layer of the N-drift layer;
depositing polysilicon and an oxide layer in the trench to form a gate;
etching the polysilicon;
and depositing a source electrode and a drain electrode.
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| CN117912957B (en) * | 2024-03-18 | 2024-05-28 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide super-junction trench gate MOSFET with low body diode voltage drop |
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