CN107644904A - A kind of mos gate control IGCT and preparation method thereof - Google Patents
A kind of mos gate control IGCT and preparation method thereof Download PDFInfo
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- CN107644904A CN107644904A CN201710810330.0A CN201710810330A CN107644904A CN 107644904 A CN107644904 A CN 107644904A CN 201710810330 A CN201710810330 A CN 201710810330A CN 107644904 A CN107644904 A CN 107644904A
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Abstract
The present invention relates to power semiconductor technologies, more particularly to a kind of MOS controls IGCT and preparation method thereof.The present invention is transformed conventional MCT negative electrode and gate regions, by increasing thin p type semiconductor layer 15 and increase P-type semiconductor base 12 under grid, so that device is when being not added with voltage devices forward blocking on grid, P+ anodes 2, which inject the hole leakage current that hole is formed, to be taken away by P-type semiconductor base 12, realize device pressure-resistant.During forward conduction, when adding positive voltage on grid, P-type semiconductor transoid forms electron channel under grid, electronics in N-type semiconductor source region 5 enters in drift region, breech lock occurs rapidly for the PNPN IGCTs being made up of P+ anodes 2, drift region 3, p-type base 4 and N-type source region 5, device obtains big conducting electric current, and snapback phenomenons are not present during conducting.The negative electrode PN junction double-layer structure of the present invention uses dual diffusion technique, is made compared with traditional tri- layers of diffusion techniques of MGT simple.
Description
Technical field
The invention belongs to power semiconductor technologies field, more particularly to a kind of MOS controls IGCT and preparation method thereof
Background technology
Pulse Power Techniques have particularly important application in the field such as national defence scientific research and new and high technology, and now more next
It is apply in industry and civil area more.Mos gate control IGCT is a kind of important pulse applied in Pulse Power Techniques
Power device.
MOS control IGCTs (MOS Controlled Thyristor, abbreviation MCT) are the allusion quotations in mos gate control IGCT
Type represents, and it is the multiple device synthesized by power MOSFET with thyristor groups, by MOSFET grid making alive control
IGCT is switched on and off, therefore MCT had both had the good on-state characteristic of IGCT and higher anti-dv/dt abilities, simultaneously
Have the advantages that power MOSFET input impedance height, switching speed are fast, there is high current density, low conduction loss and switching speed
It is fast to wait premium properties, it is mainly used in power electronics and power pulse field.But some shortcomings limit existing for conventional MCT devices
It has been made to promote the use of.Conventional MCT is normally on device, it is necessary to add negative pressure device is realized shut-off or positive on grid
Block, this can make system become complicated, also reduce the reliability of system.Conventional negative electrode short circuit MCT (Cathode
Shorted-MCT, abbreviation CS-MCT) device shut-off or forward blocking can be realized when being not added with grid voltage, but it can be caused
Forward conduction voltage drop increases and makes device job insecurity.The manufacture craft of other conventional MGT triple media causes its work
Skill is complicated difficult, reduces yield rate, adds the cost of product.The making of drive system and complexity complicated conventional MGT
Technique significantly limit its commercialization.
The content of the invention
The purpose of the present invention, aiming at current conventional open type MGT system complex, complex manufacturing technology and CS-MCT
The problem of snapback phenomenons during forward conduction be present, propose a kind of mos gate control IGCT and preparation method thereof.
Technical scheme：A kind of mos gate control IGCT, as shown in Fig. 2 its structure cell is included by anode knot
Structure, drift region structure, cathode construction and grid structure；The anode construction includes P+ anodes 2 and positioned at the lower surface of P+ anodes 2
Anode metal 1；The drift region structure is included positioned at the N- drift regions 3 of P+ anode upper surfaces；The cathode construction includes first
Negative electrode and the second negative electrode；First cathode construction includes the first cathodic metal 14 and the first P-type semiconductor base 12；Described
One P-type semiconductor base 12 is arranged on the side at the top of drift region 3, and its upper surface is connected with cathodic metal 14；Described second is cloudy
Pole structure includes the second cathodic metal 10, the P-type semiconductor base 4 of N-type semiconductor source region 5 and second；Second P-type semiconductor
Base 4 is arranged on the opposite side at the top of drift region 3；The N-type semiconductor source region 5 is arranged on the second P-type semiconductor base 4；
Second cathodic metal 10 is located at the upper surface of N-type semiconductor source region 5；The grid structure be located at the top of drift region 3 and
Between first, second negative electrode, by gate oxide 8, the thin p type semiconductor layer 15 positioned at the lower section of gate oxide 8 and positioned at gate oxidation
The polysilicon gate 9 at the top of layer 8 is formed；Characterized in that, the first P-type semiconductor base 12 by thin P-type semiconductor area 15 with
Second P-type semiconductor base 4 is connected.
Brief description of the drawings
Fig. 1 is conventional MCT structure cells schematic diagram；
Fig. 2 is conventional cathodes short-circuit structure MCT structure cell schematic diagrames；
Fig. 3 is the structural representation of the mos gate control IGCT cellular of the present invention；
Fig. 4 is the MGT of the present invention and doping concentration comparison diagram under conventional MCT grid；
Fig. 5 is to prepare the structural representation behind N- drift regions in the fabrication processing of the present invention；
Fig. 6 is the structural representation formed in the fabrication processing of the present invention after oxide layer；
Fig. 7 is to form P-type semiconductor base by ion implanting p type impurity knot in fabrication processing of the invention
Structural representation；
Fig. 8 is to form N-type semiconductor source region by ion implanting N-type impurity knot in fabrication processing of the invention
Structural representation；
Fig. 9 is etching oxidation layer in fabrication processing of the invention, and in former oxide layer position, progress ion implanting
P type impurity forms the structural representation of thin p type semiconductor layer；
Figure 10 is to form grid oxide layer by thermal oxide in fabrication processing of the invention, and one layer is deposited on grid oxide layer
Polysilicon/metal etches the structural representation to form gate electrode again；
Figure 11 is the structural representation after front-side metallization in fabrication processing of the invention；
Figure 12 is in fabrication processing of the invention after thinning back side, carries out p type impurity and injects the knot to form anode region
Structure schematic diagram；
Figure 13 is the structural representation after back face metalization in fabrication processing of the invention；
Figure 14 is MGT of the present invention, conventional MCT and CS-MCT blocking characteristics curve synoptic diagram；
Figure 15 is MGT, CS-MCT on state characteristic curve synoptic diagram of the present invention；
Figure 16 is the test circuit figure for testing MGT electric capacity discharge characteristic curve of the present invention；
Figure 17 is MGT of the present invention and conventional MCT, CS-MCT electric capacity discharge characteristic curve schematic diagram；
Embodiment
The present invention is described in detail below in conjunction with the accompanying drawings
As shown in figure 3, the present invention mos gate control IGCT, its structure cell include by anode construction, drift region structure,
Cathode construction and grid structure；The anode construction includes P+ anodes 2 and the anode metal 1 positioned at the lower surface of P+ anodes 2；It is described
Drift region structure is included positioned at the N- drift regions 3 of P+ anode upper surfaces；The cathode construction includes the first negative electrode and the second negative electrode；
First cathode construction includes the first cathodic metal 14 and the first P-type semiconductor base 12；The first P-type semiconductor base
12 are arranged on the side at the top of drift region 3, and its upper surface is connected with cathodic metal 14；It is cloudy that second cathode construction includes second
Pole metal 10, the P-type semiconductor base 4 of N-type semiconductor source region 5 and second；The second P-type semiconductor base 4 is arranged on drift
The opposite side at the top of area 3；The N-type semiconductor source region 5 is arranged on the second P-type semiconductor base 4；Second cathodic metal
10 are located at the upper surface of N-type semiconductor source region 5；The grid structure be located at the top of drift region 3 and first, second negative electrode it
Between, by gate oxide 8, the thin p type semiconductor layer 15 positioned at the lower section of gate oxide 8 and the polysilicon positioned at the top of gate oxide 8
Grid 9 is formed；Characterized in that, the first P-type semiconductor base 12 passes through the thin P-type semiconductor base of P-type semiconductor area 15 and second
Area 4 is connected.
As shown in figure 1, control IGCT (MCT) for the MOS of routine.As shown in Fig. 2 it is conventional cathodes short-circuit structure
MCT.The place different from conventional MCT structures of the invention is that the present invention is transformed cathodic region and gate regions, and second is cloudy
Pole structure is similar with conventional MCT cathode construction, and the first cathode construction is equivalent to anode in short circuit structure MCT shorting region, anode
Region is similar with conventional MCT anode construction.Compared with conventional MCT grid structure, the present invention adds below gate regions
One layer thin p type semiconductor layer 15, this thin p type semiconductor layer connect the one the second P-type semiconductor bases.Fig. 4 is MGT of the present invention
With the difference of conventional MCT doping concentrations under grid oxygen.Conventional MCT needs on grid plus a negative pressure makes channel inversion just to make device
Part reaches pressure-resistant effect, and the present invention is due to the presence of thin p type semiconductor layer 15 so that device is in the case where being not added with grid voltage
Also can realize pressure-resistant.Compared with CS-MCT, because the negative electrodes of MGT second of the present invention are similar to conventional MCT, positive grid voltage is added to make under grid
When there is n-type channel break-over of device, MGT of the present invention is similar to conventional MCT, therefore snapback phenomenons are not present.MGT of the present invention
Negative electrode PN junction double-layer structure use dual diffusion technique, made compared with traditional tri- layers of diffusion techniques of MGT simple.
Mos gate control IGCT provided by the invention, its operation principle are as follows：
In the structure cell shown in Fig. 3, when anode plus positive voltage, when negative electrode and grid connecting to neutral current potential, the He of p-type base 12
P-type base 4 is connected together by thin P layers 15, therefore forms a unified P base, between drift region and unified P bases
P-N junction is reverse-biased, and caused PN junction reverse leakage current all finally flows into p-type base 12 and extracted by gate electrode 14, and in unified p-type
A horizontal pressure drop, this PN junction reverse leakage current very little, the caused transverse direction on p-type base 12 and p-type base 4 are produced on base
Pressure drop is not enough to open PNPN thyristor structures much smaller than the PN junction barrier voltage that N-type source region and p-type base are formed.Now device
Effect that part is pressure-resistant is suitable with conventional cathodes short-circuit structure MCT.
In the structure cell shown in Fig. 3, when grid 9 plus positive potential, negative electrode adds zero potential, and anode adds malleation, under grid
Face forms N-type electron channel.Now electronics caused by N-type source region 5 flows into drift region 3 by grid lower channel, is p-type base 4, drift
The right side PNP transistor for moving area 3 and the composition of P+ anodes 2 provides ideal base drive current, and right side PNP transistor is opened, and right side PNP is brilliant
The collector current (hole current) of body pipe flows to N-type source region 5 by p-type base 4, is N-type source region 5 and p-type base 4 and N drifts
Move the NPN transistor that area 3 is formed and ideal base drive current is provided, be made up of P+ anodes 2, drift region 3, p-type base 4 and N-type source region 5
PNPN IGCTs breech lock occurs rapidly so that electric current sharply increases, and device obtains high current ability and high current-rising-rate,
Snapback phenomenons are not present simultaneously.
MGT provided by the invention, by taking the structure cell shown in Fig. 3 as an example, its making step is as follows：
The first step：Knot terminal is made in silicon chip substrate, forms N-type drift region 3, as shown in Figure 5；
Second step：Oxide layer 16 is formed by thermal oxide in the upper surface of N-type drift region 3, as shown in Figure 6；
3rd step：P-type semiconductor base 12 and 4 is formed in the upper strata both sides implanting p-type impurity of N-type drift region 3 and knot, such as
Shown in Fig. 7；
4th step：On the upper strata of N-type drift region 3, injection N-type impurity forms N-type semiconductor source region 5；N-type semiconductor source region 5
In P-type semiconductor base 4, as shown in Figure 8；
5th step：Etching oxidation layer 16, thin p type semiconductor layer is formed by implanting p-type impurity 16 times in former oxide layer
15, as shown in Figure 9；
6th step：Grid oxide layer 8 is formed by thermal oxide among the thin upper surface of p type semiconductor layer 15, and on grid oxide layer 8
One layer of polysilicon/metal of deposit etches to form gate electrode 9 again, as shown in Figure 10；
7th step：BPSG insulating medium layers are deposited in device upper surface, etch ohmic contact hole；
8th step：In P-type semiconductor base 12 and the upper surface of N-type semiconductor source region 5 deposit metal, negative electrode gold is formed respectively
Category 14 and 10；As shown in figure 11；
9th step：Deposit passivation layer；
Tenth step：The lower surface of N-type semiconductor drift region 3 is thinned, polishing, implanting p-type impurity and carry out from
Son activation, forms P+ anode regions 2, as shown in figure 12；
11st step：Back of the body gold, anode 1 is formed in the bottom of P+ anodes 2, as shown in figure 13.
Emulation comparison is carried out with pressure-resistant 1500V CS-MCT, conventional MCT and the mos gate control IGCT of the present invention.Such as Figure 14
Shown, when grid voltage is equal to 0V, this example MGT has that more than 1600V's is pressure-resistant, and conventional MCT only has that about 0.4V's is pressure-resistant.Only
When grid voltage is -10V, conventional MCT could obtain pressure-resistant with this example MGT identicals.When device is opened, as shown in figure 15, this
Invention MGT conduction voltage drops are significantly less than conventional MCT, and CS-MCT has snapback phenomenons, and this is not present in MGT of the present invention
Phenomenon.
By pressure-resistant 1500V conventional MCT with carrying out simulation comparison exemplified by the mos gate control IGCT of the present invention.Test circuit
As shown in figure 16, supply voltage 1000V, electric capacity C are 0.2 μ F, and inductance L is 5nH, and gate resistance Rg is 4.7 Ω.It is active in device
Area's area is 1cm2When, as can be seen from Figure 17, MGT of the present invention current peak and current-rising-rate and conventional MCT are several
It is identical, hence it is evident that better than CS-MCT.Therefore, MGT of the present invention is applied to power pulse field.
Claims (2)
1. a kind of mos gate control IGCT, its structure cell is included by anode construction, drift region structure, cathode construction and grid knot
Structure；The anode construction includes P+ anodes (2) and the anode metal (1) positioned at P+ anodes (2) lower surface；The drift region structure
Including positioned at the N- drift regions (3) of P+ anode upper surfaces；The cathode construction includes the first negative electrode and the second negative electrode；Described first
Cathode construction includes the first cathodic metal (14) and the first P-type semiconductor base (12)；The first P-type semiconductor base (12)
The side being arranged at the top of drift region (3), its upper surface are connected with cathodic metal (14)；Second cathode construction includes second
Cathodic metal (10), N-type semiconductor source region (5) and the second P-type semiconductor base (4)；The second P-type semiconductor base (4)
The opposite side being arranged at the top of drift region (3)；The N-type semiconductor source region (5) is arranged on the second P-type semiconductor base (4)；
Second cathodic metal (10) is located at the upper surface of N-type semiconductor source region (5)；The grid structure is located at drift region (3) top
Between portion and first, second negative electrode, by gate oxide (8), the thin p type semiconductor layer (15) below gate oxide (8)
Formed with the polysilicon gate (9) at the top of gate oxide (8)；Characterized in that, the first P-type semiconductor base (12) passes through
Thin P-type semiconductor area (15) is connected with the second P-type semiconductor base (4).
2. a kind of preparation method of mos gate control IGCT, it is characterised in that comprise the following steps：
The first step：Knot terminal is made in silicon chip substrate, forms N-type drift region (3)；
Second step：Oxide layer (16) is formed by thermal oxide in N-type drift region (3) upper surface；
3rd step：P-type semiconductor base (12) and (4) are formed in N-type drift region (3) upper strata both sides implanting p-type impurity and knot；
4th step：On P-type semiconductor base (4) upper strata, injection N-type impurity forms N-type semiconductor source region (5)；The N-type is partly led
Body source region (5) is located in P-type semiconductor base (4)；
5th step：Etching oxidation layer (16), (16) form thin p type semiconductor layer by implanting p-type impurity under former oxide layer
(15)；
6th step：Grid oxide layer (8) is formed by thermal oxide among thin p type semiconductor layer (15) upper surface, and in grid oxide layer
(8) one layer of polysilicon/metal is deposited on to etch to form gate electrode (9) again；
7th step：BPSG insulating medium layers are deposited in device upper surface, etch ohmic contact hole；
8th step：Metal is deposited in P-type semiconductor base (12) and N-type semiconductor source region (5) upper surface, forms negative electrode gold respectively
Belong to (14) and (10)；
9th step：Deposit passivation layer；
Tenth step：N-type semiconductor drift region (3) lower surface is thinned, polishing, implanting p-type impurity simultaneously carries out ion
Activation, form P+ anodes (2)；
11st step：Back of the body gold, anode (1) is formed in P+ anodes (2) bottom.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117457731A (en) * | 2023-12-22 | 2024-01-26 | 深圳天狼芯半导体有限公司 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796124A (en) * | 1992-10-08 | 1998-08-18 | Kabushiki Kaisha Toshiba | MOS gate controlled thyristor |
| CN104393034A (en) * | 2014-11-25 | 2015-03-04 | 电子科技大学 | MOS (metal oxide semiconductor) grid-control thyristor and manufacturing method thereof |
-
2017
- 2017-09-11 CN CN201710810330.0A patent/CN107644904A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796124A (en) * | 1992-10-08 | 1998-08-18 | Kabushiki Kaisha Toshiba | MOS gate controlled thyristor |
| CN104393034A (en) * | 2014-11-25 | 2015-03-04 | 电子科技大学 | MOS (metal oxide semiconductor) grid-control thyristor and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117457731A (en) * | 2023-12-22 | 2024-01-26 | 深圳天狼芯半导体有限公司 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
| CN117457731B (en) * | 2023-12-22 | 2024-05-28 | 深圳天狼芯半导体有限公司 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
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