CN117253871A - Semiconductor packaging device and packaging method thereof - Google Patents
Semiconductor packaging device and packaging method thereof Download PDFInfo
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- CN117253871A CN117253871A CN202311543448.3A CN202311543448A CN117253871A CN 117253871 A CN117253871 A CN 117253871A CN 202311543448 A CN202311543448 A CN 202311543448A CN 117253871 A CN117253871 A CN 117253871A
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- lead frame
- chip
- frame
- packaging
- heat dissipation
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000017525 heat dissipation Effects 0.000 claims abstract description 50
- 229910000679 solder Inorganic materials 0.000 claims abstract description 34
- 230000001680 brushing effect Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 15
- 239000012792 core layer Substances 0.000 claims description 6
- 239000005022 packaging material Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000000306 component Substances 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of semiconductor devices, and discloses a semiconductor packaging device and a packaging method thereof, wherein when the semiconductor packaging device works, heat generated by a chip is conducted upwards along a first lead frame and then is dissipated to the outside from the upper surface of the first lead frame; the heat generated by the chip can be downwards conducted along the second lead frame and the third lead frame, namely a plurality of heat dissipation channels are formed, and the heat dissipation efficiency of the semiconductor packaging device is further improved; two grooves are formed, and if the solder overflows when the chip is mounted, the two grooves can prevent the solder from overflowing on the surface of the chip, and the combination property of the lead frame and the packaging body can be improved, so that the lead frame and the packaging body are prevented from falling off in a layering manner; the chip is fixed with the three lead frames in a mode of brushing solder, so that the mounting difficulty is low and the production efficiency is high.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor packaging device and a packaging method thereof.
Background
With the development of the information age, semiconductor devices are widely used in various electronic products, and the demands for these electronic devices are increasing, wherein the semiconductor devices are also receiving great attention as core components of the electronic products.
At present, most of power semiconductor devices adopt a fully-encapsulated or semi-encapsulated structure, internal connection of the semiconductor devices adopts a lead wire or bridge connection mode, and the semiconductor packaging devices have the following problems: 1. the lead wire or bridge type connection is adopted, so that the processing difficulty is high, and the production efficiency is low; 2. whether the semiconductor device is fully encapsulated or semi-encapsulated, the chip of the semiconductor device is encapsulated in the plastic package body, and the heat transmission mode generated by the chip during the operation of the semiconductor device is mainly to radiate from top to bottom, so that the heat radiation channel is single, and the heat cannot be efficiently conducted out, thereby reducing the temperature of the chip; 3. the surface of the pin used for bridge connection is generally a plane, the adhesion force between the package body and the surface of the pin is poor, and layering problem easily occurs between the pin and the package body in the use process. Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a semiconductor package device and a packaging method thereof, so as to solve the problems of the existing semiconductor device, such as high processing difficulty, low heat dissipation efficiency, and easy delamination of the connection between the leads and the package.
A semiconductor package device comprising a package body and a chip disposed within the package body, the semiconductor package device further comprising:
a first lead frame, wherein the lower end of the first lead frame is in electrical contact with the chip, and the upper surface of the first lead frame extends out of the upper surface of the package body;
a second lead frame, the upper end of the second lead frame is provided with a first bulge and a first groove surrounding the first bulge, the upper end of the first bulge is in electrical contact with the chip, and the lower surface of the second lead frame extends out of the lower surface of the packaging body;
a third lead frame, the upper end of which is provided with a second bulge and a second groove surrounding the second bulge, the upper end of the second bulge is in electrical contact with the chip, and the lower surface of the third lead frame extends out of the lower surface of the packaging body;
the front, back, left and right sides of the first lead frame are connected with first connecting ribs, and the outer side surfaces of the first connecting ribs extend out of the outer side surfaces of the packaging body;
the front, back, left and right sides of the second lead frame are connected with second connecting ribs, and the outer side surfaces of the second connecting ribs extend out of the outer side surfaces of the packaging body;
and the front side surface and the left side surface of the third lead frame are connected with third connecting ribs, and the outer side surfaces of the third connecting ribs extend out of the outer side surfaces of the packaging body.
Specifically, the chip comprises a grid electrode, a source electrode and a drain electrode, wherein the drain electrode is positioned at the upper end of the chip, the source electrode and the grid electrode are positioned at the lower end of the chip, the lower end of the first lead frame is connected with the drain electrode through a first welding material layer, the first bulge is connected with the source electrode through a second welding material layer, and the second bulge is connected with the grid electrode through a third welding material layer.
Specifically, on the same plane, the first connecting rib and the second connecting rib are arranged in a staggered mode along the arrangement direction, and the first connecting rib and the third connecting rib are arranged in a staggered mode along the arrangement direction.
Specifically, the upper end of the first lead frame is provided with a first heat dissipation part and a first hollowed-out groove surrounding the first heat dissipation part, a part of the packaging body is filled in the first hollowed-out groove, and the upper surface of the first heat dissipation part extends out of the upper surface of the packaging body;
the lower end of the second lead frame is provided with a second heat dissipation part and a second hollowed-out groove surrounding the second heat dissipation part, a part of the packaging body is filled in the second hollowed-out groove, and the lower surface of the second heat dissipation part extends out of the lower surface of the packaging body;
the lower end of the third lead frame is provided with a third heat dissipation part and a third hollowed-out groove surrounding the third heat dissipation part, a part of the packaging body is filled in the third hollowed-out groove, and the lower surface of the third heat dissipation part extends out of the lower surface of the packaging body.
Specifically, the area ratio of the upper surface of the first heat dissipation part to the upper surface of the drain electrode is greater than 1:1.
Specifically, the area ratio of the lower surface of the second heat dissipation part to the lower surface of the source electrode is greater than 1:1.
Specifically, the area ratio of the lower surface of the third heat dissipation part to the lower surface of the grid electrode is greater than 1:1.
A packaging method of a semiconductor package device, comprising the steps of:
s1, preparing a first frame and a second frame, wherein the first frame comprises a first outer frame and the first lead frame connected to the inner side of the first outer frame, and the second frame comprises a second outer frame, and the second lead frame and the third lead frame connected to the inner side of the second outer frame;
s2, brushing solder paste on the second lead frame and the third lead frame respectively, aligning and fixing the chip, brushing solder paste on the chip, aligning and placing the first lead frame, and curing to obtain an intermediate core layer;
s3, coating the middle core layer through plastic packaging materials, and curing to obtain a packaging body, wherein the upper surface of the first lead frame extends out of the upper surface of the packaging body, the lower surface of the second lead frame extends out of the lower surface of the packaging body, and the lower surface of the third lead frame extends out of the lower surface of the packaging body;
and S4, cutting and removing the first outer frame and the second outer frame to obtain the semiconductor packaging device.
The invention has the beneficial effects that:
according to the semiconductor packaging device and the packaging method thereof, when the semiconductor packaging device works, heat generated by a chip is conducted upwards along a first lead frame and then is dissipated to the outside from the upper surface of the first lead frame; the heat generated by the chip can be downwards conducted along the second lead frame and the third lead frame, namely a plurality of heat dissipation channels are formed, and the heat dissipation efficiency of the semiconductor packaging device is further improved; two grooves are formed, and if the solder overflows when the chip is mounted, the two grooves can prevent the solder from overflowing on the surface of the chip, and the combination property of the lead frame and the packaging body can be improved, so that the lead frame and the packaging body are prevented from falling off in a layering manner; the chip is fixed with the three lead frames in a mode of brushing solder, so that the mounting difficulty is low and the production efficiency is high.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a perspective view of a semiconductor package device according to the present invention;
fig. 2 is a bottom view of a semiconductor package device of the present invention;
FIG. 3 is a cross-sectional view taken along the A-A plane in FIG. 2;
fig. 4 is an exploded view of a semiconductor package device of the present invention;
FIG. 5 is a schematic diagram of the back structure of the chip of the present invention;
fig. 6 is a schematic view of the back structures of the second and third lead frames of the present invention;
FIG. 7 is a perspective view of a first frame of the present invention;
fig. 8 is a perspective view of a second frame according to the present invention.
The reference numerals are: the package body 10, the chip 20, the first lead frame 30, the first solder layer 21, the second lead frame 40, the first bump 41, the first groove 42, the second solder layer 22, the third lead frame 50, the second bump 51, the second groove 52, the third solder layer 23, the first connecting rib 31, the second connecting rib 43, the third connecting rib 53, the first heat dissipation portion 32, the first hollow groove 33, the second heat dissipation portion 44, the second hollow groove 45, the third heat dissipation portion 54, the third hollow groove 55, the first frame 60, and the second frame 70.
Detailed Description
The invention provides a semiconductor packaging device and a packaging method thereof, which are used for making the purposes, technical schemes and effects of the invention clearer and more definite, and the invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
As shown in fig. 1 to 4, the present embodiment discloses a semiconductor package device including a package body 10 and a chip 20 disposed within the package body 10, the semiconductor package device further including:
a first lead frame 30, a lower end of the first lead frame 30 being in electrical contact with the chip 20, an upper surface of the first lead frame 30 extending beyond an upper surface of the package body 10;
a second lead frame 40, the upper end of the second lead frame 40 having a first protrusion 41 and a first groove 42 surrounding the first protrusion 41, the upper end of the first protrusion 41 being in electrical contact with the chip 20, the lower surface of the second lead frame 40 extending beyond the lower surface of the package body 10;
the third lead frame 50, the upper end of the third lead frame 50 has a second protrusion 51 and a second groove 52 surrounding the second protrusion 51, the upper end of the second protrusion 51 is in electrical contact with the chip 20, and the lower surface of the third lead frame 50 extends out of the lower surface of the package body 10.
In the semiconductor package device of the embodiment, the heat can be directly conducted by the combination mode of the first lead frame 30 and the chip 20 through surface contact, and the upper surface of the first lead frame 30 extends out of the upper surface of the package body 10, when the semiconductor package device works, the heat generated by the chip 20 is conducted upwards along the first lead frame 30 and then is dissipated to the outside from the upper surface of the first lead frame 30, so that the heat dissipation efficiency is high; the lower surfaces of the second lead frame 40 and the third lead frame 50 are further provided to extend out of the lower surface of the package body 10, and heat generated by the chip 20 can be conducted downwards along the second lead frame 40 and the third lead frame 50, i.e., a plurality of heat dissipation channels are formed, so that the heat dissipation efficiency of the semiconductor package device is further improved.
In the semiconductor package of this embodiment, the upper end of the second lead frame 40 has the first protrusion 41 and the first groove 42, and if solder paste overflows when the chip 20 is mounted, the first groove 42 can prevent solder paste from overflowing onto the surface of the chip 20, and in addition, the first groove 42 can increase the bonding property between the second lead frame 40 and the package body 10, so as to prevent the two from falling off in a layering manner.
In the semiconductor package device of this embodiment, the second protrusion 51 and the second groove 52 are disposed at the upper end of the third lead frame 50, and if solder paste overflows when the chip 20 is mounted, the second groove 52 can prevent solder paste from overflowing onto the surface of the chip 20, in addition, the second groove 52 can increase the bonding property of the third lead frame 50 and the package body 10, preventing the third lead frame 50 and the package body from falling off in a layered manner, and the design of the second protrusion 51 can be aligned with the chip 20 quickly, prevent dislocation, and increase the operation feasibility.
The chip 20 of the embodiment includes a gate, a source, and a drain, that is, the gate, the S, and the D correspond to the G electrode, the G electrode is an electrode that covers a layer of metal on an insulating layer of the chip 20 and is led out, the G electrode is a ground terminal, the D electrode is an internal MOS drain, the S electrode is an internal MOS source, in the circuit, the G electrode is grounded, the D electrode is connected to the power source anode, and the S electrode is connected to the power source cathode. The drain electrode is located at the upper end of the chip 20, the source electrode and the grid electrode are located at the lower end of the chip 20, the lower end of the first lead frame 30 is connected with the drain electrode through the first solder layer 21, the first protrusion 41 is connected with the source electrode through the second solder layer 22, and the second protrusion 51 is connected with the grid electrode through the third solder layer 23.
The first, second and third solder layers 21, 22 and 23 in this embodiment are all solder pastes, but not limited to solder pastes, and may be connected by solder pastes, such as tin-lead solder, silver solder, copper solder, etc., so that they are not easy to separate and fall off after solidification, and have good structural stability.
As shown in fig. 1 and 4, the front, rear, left and right sides of the first lead frame 30 are connected with the first connecting rib 31, the outer side of the first connecting rib 31 extends out of the outer side of the package body 10, and the first connecting rib 31 can serve as an auxiliary heat transfer component around the first lead frame 30, so that the heat dissipation efficiency of the first lead frame 30 can be increased.
As shown in fig. 1 and 4, the front, rear, left and right sides of the second lead frame 40 are connected with the second connecting ribs 43, the outer side surfaces of the second connecting ribs 43 extend out of the outer side surfaces of the package body 10, and the second connecting ribs 43 can serve as auxiliary heat transfer components around the second lead frame 40, so that the heat dissipation efficiency of the second lead frame 40 can be increased.
As shown in fig. 1 and 4, the front side and the left side of the third lead frame 50 are both connected with a third connecting rib 53, the outer side of the third connecting rib 53 extends out of the outer side of the package body 10, and the third connecting rib 53 can be used as an auxiliary heat transfer component around the third lead frame 50, so that the heat dissipation efficiency of the third lead frame 50 can be increased.
As shown in fig. 1, on the same plane, the first connecting rib 31 and the second connecting rib 43 are arranged in a staggered manner along the arrangement direction, the first connecting rib 31 and the third connecting rib 53 are arranged in a staggered manner along the arrangement direction, and the connecting ribs of the upper lead frame and the lower lead frame are designed in a staggered manner, so that electric leakage can be prevented when the upper lead frame and the lower lead frame are used as an application end under high voltage.
As shown in fig. 4, the upper end of the first lead frame 30 has a first heat dissipation portion 32 and a first hollow groove 33 surrounding the first heat dissipation portion 32, after the package body 10 is molded by plastic packaging, a portion of the package body 10 is filled in the first hollow groove 33, so that the engagement between the first lead frame 30 and the plastic packaging material is enhanced, the structural stability of the semiconductor package device is improved, the upper surface of the first heat dissipation portion 32 extends out of the upper surface of the package body 10, and the heat of the first lead frame 30 can be directly dissipated to the outside through the upper surface of the first heat dissipation portion 32, so that the heat dissipation efficiency is high.
As shown in fig. 6, the lower end of the second lead frame 40 has a second heat dissipation portion 44 and a second hollow groove 45 surrounding the second heat dissipation portion 44, after the package body 10 is molded by plastic packaging, a portion of the package body 10 is filled in the second hollow groove 45, so as to enhance the engagement between the second lead frame 40 and the plastic packaging material, improve the structural stability of the semiconductor package device, and the lower surface of the second heat dissipation portion 44 extends out of the lower surface of the package body 10, and the heat of the second lead frame 40 can be directly dissipated to the outside through the upper surface of the second heat dissipation portion 44, so that the heat dissipation efficiency is high.
As shown in fig. 6, the lower end of the third lead frame 50 has a third heat dissipation portion 54 and a third hollow groove 55 surrounding the third heat dissipation portion 54, after the package body 10 is molded by plastic packaging, a portion of the package body 10 is filled in the third hollow groove 55, so as to enhance the engagement between the third lead frame 50 and the plastic packaging material, improve the structural stability of the semiconductor package device, and the lower surface of the third heat dissipation portion 54 extends out of the lower surface of the package body 10, and the heat of the third lead frame 50 can be directly dissipated to the outside through the upper surface of the third heat dissipation portion 54, so that the heat dissipation efficiency is high.
As shown in fig. 4 to 6, the area ratio of the upper surface of the first heat dissipation portion 32 to the upper surface of the drain electrode is greater than 1:1, the area ratio of the lower surface of the second heat dissipation portion 44 to the lower surface of the source electrode is greater than 1:1, and the area ratio of the lower surface of the third heat dissipation portion 54 to the lower surface of the gate electrode is greater than 1:1.
A packaging method of a semiconductor package device, comprising the steps of:
s1 preparing a first frame 60 and a second frame 70 as shown in fig. 7 and 8, wherein the first frame 60 includes a first outer frame and a first lead frame 30 connected inside the first outer frame, and the second frame 70 includes a second outer frame and a second lead frame 40 and a third lead frame 50 connected inside the second outer frame;
s2, brushing solder paste on the second lead frame 40 and the third lead frame 50 respectively, aligning and fixing the chip 20, brushing solder paste on the chip 20, aligning and placing the first lead frame 30, and curing to obtain an intermediate core layer;
s3, coating the middle core layer by using plastic packaging materials, and curing to obtain a packaging body 10, wherein the upper surface of the first lead frame 30 extends out of the upper surface of the packaging body 10, the lower surface of the second lead frame 40 extends out of the lower surface of the packaging body 10, and the lower surface of the third lead frame 50 extends out of the lower surface of the packaging body 10;
s4, cutting and removing the first outer frame and the second outer frame to obtain the semiconductor packaging device.
According to the packaging method of the semiconductor packaging device disclosed by the embodiment, the chip 20 is fixed with the first lead frame 30, the second lead frame 40 and the third lead frame 50 in a solder coating manner, the use amount and the coating thickness of the solder are easy to control, local hollows are avoided, electric contact is directly realized after contact, a lead wire or a bridge type pin is not needed, the mounting difficulty is low, and the production efficiency is high.
While the preferred embodiment of the present invention has been described in detail, the invention is not limited to the embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the invention, and these equivalent modifications and substitutions are intended to be included in the scope of the invention as defined in the appended claims.
Claims (8)
1. A semiconductor package device comprising a package (10) and a chip (20) disposed within the package (10), the semiconductor package device further comprising:
a first lead frame (30), wherein the lower end of the first lead frame (30) is in electrical contact with the chip (20), and the upper surface of the first lead frame (30) extends out of the upper surface of the package body (10);
a second lead frame (40), wherein a first protrusion (41) and a first groove (42) surrounding the first protrusion (41) are arranged at the upper end of the second lead frame (40), the upper end of the first protrusion (41) is electrically contacted with the chip (20), and the lower surface of the second lead frame (40) extends out of the lower surface of the packaging body (10);
a third lead frame (50), wherein the upper end of the third lead frame (50) is provided with a second bulge (51) and a second groove (52) surrounding the second bulge (51), the upper end of the second bulge (51) is in electrical contact with the chip (20), and the lower surface of the third lead frame (50) extends out of the lower surface of the packaging body (10);
the front, back, left and right sides of the first lead frame (30) are connected with first connecting ribs (31), and the outer side surfaces of the first connecting ribs (31) extend out of the outer side surfaces of the package body (10);
the front, back, left and right sides of the second lead frame (40) are respectively connected with a second connecting rib (43), and the outer side surface of the second connecting rib (43) extends out of the outer side surface of the package body (10);
and the front side surface and the left side surface of the third lead frame (50) are connected with third connecting ribs (53), and the outer side surface of the third connecting ribs (53) extends out of the outer side surface of the package body (10).
2. A semiconductor package device according to claim 1, wherein the chip (20) comprises a gate, a source, and a drain, the drain being located at an upper end of the chip (20), the source and the gate being located at a lower end of the chip (20), the lower end of the first lead frame (30) being connected to the drain by a first solder layer (21), the first bump (41) being connected to the source by a second solder layer (22), and the second bump (51) being connected to the gate by a third solder layer (23).
3. A semiconductor package device according to claim 1, wherein the first connecting rib (31) and the second connecting rib (43) are arranged in a staggered manner along the arrangement direction, and the first connecting rib (31) and the third connecting rib (53) are arranged in a staggered manner along the arrangement direction on the same plane.
4. A semiconductor package device according to claim 2, wherein the upper end of the first lead frame (30) has a first heat sink (32) and a first hollowed-out groove (33) surrounding the first heat sink (32), a portion of the package body (10) is filled in the first hollowed-out groove (33), and an upper surface of the first heat sink (32) extends out of an upper surface of the package body (10);
the lower end of the second lead frame (40) is provided with a second heat dissipation part (44) and a second hollowed-out groove (45) surrounding the second heat dissipation part (44), a part of the packaging body (10) is filled in the second hollowed-out groove (45), and the lower surface of the second heat dissipation part (44) extends out of the lower surface of the packaging body (10);
the lower end of the third lead frame (50) is provided with a third heat dissipation part (54) and a third hollowed-out groove (55) surrounding the third heat dissipation part (54), a part of the packaging body (10) is filled in the third hollowed-out groove (55), and the lower surface of the third heat dissipation part (54) extends out of the lower surface of the packaging body (10).
5. The semiconductor package according to claim 4, wherein an area ratio of the upper surface of the first heat sink member (32) to the upper surface of the drain electrode is greater than 1:1.
6. The semiconductor package according to claim 4, wherein an area ratio of the lower surface of the second heat sink member (44) to the lower surface of the source is greater than 1:1.
7. The semiconductor package according to claim 4, wherein an area ratio of a lower surface of the third heat sink member (54) to a lower surface of the gate is greater than 1:1.
8. A packaging method of the semiconductor packaging device according to any one of claims 1 to 7, comprising the steps of:
s1, preparing a first frame (60) and a second frame (70), wherein the first frame (60) comprises a first outer frame and the first lead frame (30) connected to the inner side of the first outer frame, and the second frame (70) comprises a second outer frame and the second lead frame (40) and the third lead frame (50) connected to the inner side of the second outer frame;
s2, brushing solder on the second lead frame (40) and the third lead frame (50) respectively, aligning and fixing the chip (20), brushing solder on the chip (20), aligning and placing the first lead frame (30), and curing to obtain an intermediate core layer;
s3, coating the middle core layer through plastic packaging materials, and curing to obtain a packaging body (10), wherein the upper surface of the first lead frame (30) extends out of the upper surface of the packaging body (10), the lower surface of the second lead frame (40) extends out of the lower surface of the packaging body (10), and the lower surface of the third lead frame (50) extends out of the lower surface of the packaging body (10);
and S4, cutting and removing the first outer frame and the second outer frame to obtain the semiconductor packaging device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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