CN116996071A - SARADC sampling clock generation device and method - Google Patents
SARADC sampling clock generation device and method Download PDFInfo
- Publication number
- CN116996071A CN116996071A CN202311252962.1A CN202311252962A CN116996071A CN 116996071 A CN116996071 A CN 116996071A CN 202311252962 A CN202311252962 A CN 202311252962A CN 116996071 A CN116996071 A CN 116996071A
- Authority
- CN
- China
- Prior art keywords
- saradc
- sampling clock
- sampling
- clock
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 190
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 9
- 238000003708 edge detection Methods 0.000 claims description 6
- 230000001934 delay Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a SARADC sampling clock generating device and a SARADC sampling clock generating method, comprising the following steps: an enable signal generating circuit for converting an external sampling pulse of the SARADC into an enable logic level; the sampling clock generation circuit is electrically connected with the enabling signal generation circuit, and is used for generating an SARADC sampling clock with fixed delay with external sampling pulses, and the working state of the sampling clock generation circuit is controlled by enabling logic level; and the clock frequency divider is electrically connected with the output end of the sampling clock generation circuit and is used for generating a down-conversion SARADC sampling clock by setting the frequency division number. The SARADC sampling clock generating device provided by the invention utilizes the enabling logic level to control the sampling clock generating circuit to generate the SARADC sampling clock with fixed delay of external sampling pulse, and simultaneously utilizes the clock frequency divider to generate the down-conversion SARADC sampling clock with adjustable period.
Description
Technical Field
The invention relates to the technical field of SARADC sampling, in particular to a device and a method for generating an SARADC sampling clock.
Background
The SARADC starting mode is to externally trigger sampling and internally generate a series of sampling clocks; the external sampling clock is given by the host computer and has strict periodicity so as to realize uniform sampling; the digital module of the SARADC internally generates sampling pulses to trigger data conversion of the SARADC after receiving external sampling pulses, and simultaneously completes sampling.
In digital sampling, due to the possible metastable state of the sampling time, even if the input signal is a strictly periodic signal, the generated sampling clock may still have a deviation of one digital clock period. As shown in fig. 1, the external sampling clock period is T1, but since the digital clock is asynchronous with the external sampling clock, the sampling-generated sar adc sampling clock T3 is not equal to T4. The SNR of the device may be reduced due to non-uniformity of sampling.
The prior art SARADC samples typically produce a limited number of pulses and the pulse period produced depends on a delay unit, so the pulse period is difficult to achieve long. Meanwhile, the sampling circuit which depends on the delay unit has the problems of high cost, low efficiency, time consumption and the like. Therefore, a low-cost sar adc sampling clock generator with a fixed delay and an adjustable period is desired.
Based on the technical background, the invention researches an SARADC sampling clock generating device and an SARADC sampling clock generating method.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides an SARADC sampling clock generating device and method, wherein the device utilizes an enabling logic level to control a sampling clock generating circuit to generate an SARADC sampling clock with fixed delay of external sampling pulse, and simultaneously utilizes a clock frequency divider to generate a down-conversion SARADC sampling clock with adjustable period.
In order to achieve the above object, a first aspect of the present invention provides an sar adc sampling clock generating apparatus, comprising:
an enable signal generating circuit for converting an external sampling pulse of the SARADC into an enable logic level;
the sampling clock generation circuit is electrically connected with the enabling signal generation circuit and is used for generating an SARADC sampling clock with fixed delay with the external sampling pulse, and the working state of the sampling clock generation circuit is controlled by the enabling logic level;
and the clock frequency divider is electrically connected with the output end of the sampling clock generation circuit and is used for generating a down-conversion SARADC sampling clock by setting a frequency division number.
A second aspect of the present invention provides a method for generating a sar adc sampling clock in the above apparatus, comprising:
converting the external sampling pulse of the SARADC to an enable logic level;
controlling a sampling clock generation circuit through the enabling logic level to generate an SARADC sampling clock with fixed delay with the external sampling pulse;
and sending the SARADC sampling clock to a clock frequency divider, and setting the frequency division number to generate a down-conversion SARADC sampling clock.
The invention has the following effects:
(1) The SARADC sampling clock generating device provided by the invention utilizes the enabling logic level to control the sampling clock generating circuit to generate the SARADC sampling clock with fixed delay of external sampling pulse, and simultaneously utilizes the clock frequency divider to generate the down-conversion SARADC sampling clock with adjustable period.
(2) According to the SARADC sampling clock generation device, the first edge detector, the first D trigger and the inverter are matched to work, so that the detection of external sampling pulses is more accurate and controllable.
(3) According to the SARADC sampling clock generating device, the second edge detector, the second D trigger, the third edge detector and the third D trigger are matched to work, so that the fixed delay of an external sampling pulse and the SARADC sampling clock and the width of the high level and the low level of the SARADC sampling clock are accurately controlled.
(4) According to the SARADC sampling clock generation device, the number of the down-conversion SARADC sampling clocks is recorded by setting the counter, and after the number of the down-conversion SARADC sampling clocks meets the sampling requirement, a completion level signal is generated to reset and clear the second D trigger and the third D trigger, so that the power consumption of the device is saved.
(5) According to the SARADC sampling clock generating device, the frequency adjusting register is arranged, so that the period adjustment of the down-conversion SARADC sampling clock is more convenient and flexible.
(6) According to the SARADC sampling clock generating device, the delay parameters of the delay devices in the first edge detector, the second edge detector and the third edge detector are respectively set, so that the delay parameters of the enabling logic level and the period parameters of the SARADC sampling clock are more accurate and controllable.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 is a flow chart of a prior art SARADC sampling clock sampling method.
Fig. 2 is a schematic structural diagram of an SARADC sampling clock generating device according to the present invention.
Reference numerals illustrate:
a 1-enable signal generation circuit, a 2-sampling clock generation circuit, a 3-clock divider;
101-first edge detector, 102-first D flip-flop, 103-inverter, 104-second D flip-flop, 105-third D flip-flop, 106-second edge detector, 107-third edge detector, 108-three input AND gate, 109-clock delay;
1001-external sampling pulse, 1002-enable logic level, 1003-SARADC sampling clock, 1004-down-converted SARADC sampling clock, 1005-logic low level.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the preferred embodiments of the present invention are described below, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein.
In the present invention, unless otherwise indicated, terms of orientation such as "upper and lower" are used to refer generally to the upper and lower of the device in normal use, for example with reference to the orientation of the drawing of fig. 1, and "inner and outer" are used with respect to the outline of the device. Furthermore, the terms "first, second, third and the like" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first, second, third" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The invention provides an SARADC sampling clock generating device, as shown in figure 1, comprising:
an enable signal generating circuit 1 for converting an external sampling pulse 1001 of the sar adc into an enable logic level 1002;
a sampling clock generation circuit 2 electrically connected to the enable signal generation circuit 1, the sampling clock generation circuit 2 being configured to generate a sar adc sampling clock 1003 having a fixed delay with respect to the external sampling pulse 1001, and the operation state thereof being controlled by an enable logic level 1002;
the clock divider 3 is electrically connected to an output terminal of the sampling clock generation circuit 2, and is configured to generate a down-converted SARADC sampling clock 1004 by setting a division number.
In the present invention, the sampling clock generation circuit 2 is controlled by the enable logic level 1002, the SARADC sampling clock 1003 having a fixed delay is generated for the external sampling pulse 1001, and the down-conversion SARADC sampling clock 1004 having an adjustable period is generated by the clock divider 3.
According to the present invention, the enable signal generation circuit 1 includes a first edge detector 101, a first D flip-flop 102, and an inverter 103;
the input end of the first edge detector 101 is electrically connected with the external sampling pulse 1001, and the output end is electrically connected with the set end of the first D trigger 102;
the input terminal of the inverter 103 is electrically connected to the sar adc sampling clock 1003, and the output terminal is electrically connected to the clock input terminal of the first D flip-flop 102.
In the invention, the detection of the external sampling pulse 1001 is more accurate and controllable by the cooperation of the first edge detector 101, the first D flip-flop 102 and the inverter 103.
According to the present invention, the sampling clock generation circuit 2 includes a second edge detector 106, a second D flip-flop 104, a third edge detector 107, a third D flip-flop 105;
the inverting output terminal of the third D flip-flop 105 is electrically connected to the signal input terminal of the second D flip-flop 104;
the clock input ends of the second D trigger 104 and the third D trigger 105 are electrically connected with the SARADC sampling clock 1003, and the setting end is electrically connected with the in-phase output end of the first D trigger 102;
the non-inverting outputs of the second D flip-flop 104 and the third D flip-flop 105 are electrically connected to the inputs of the second edge detector 106 and the third edge detector 107, respectively.
According to the present invention, the sampling clock generation circuit 2 further includes a three-input and gate 108 and a clock delay 109;
the three input ends of the three-input AND gate 108 are respectively and electrically connected with the in-phase output end of the first D trigger 102, the second edge detector 106 and the output end of the third edge detector 107, and the output end is electrically connected with the input end of the clock delay 109;
the output of the clock delay 109 is used to output the sar adc sampling clock 1003.
Preferably, the signal input of the first D flip-flop 102 is electrically connected to a logic low 1005;
the non-inverting output of the second D flip-flop 104 is also electrically connected to the signal input of the third D flip-flop 105.
In the invention, the fixed delay of the external sampling pulse 1001 and the SARADC sampling clock 1003 and the width of the high level and the low level of the SARADC sampling clock 1003 are precisely controlled by the cooperation of the second edge detector 106, the second D trigger 104, the third edge detector 107 and the third D trigger 105.
Preferably, the first edge detector 101, the second edge detector 106 and the third edge detector 107 each comprise an edge delay and an exclusive or gate;
the input end of each edge detector is electrically connected with the input end of the edge delay and one input end of the exclusive-OR gate, the output end of the edge delay is electrically connected with the other input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is the output end of the edge detector.
In the invention, by respectively setting the delay parameters of the delays in the first edge detector 101, the second edge detector 106 and the third edge detector 107, the delay parameters of the enabled logic level 1002 and the period parameters of the SARADC sampling clock 1003 are more accurately controllable; the delay parameters of the delays in the first edge detector 101, the second edge detector 106, and the third edge detector 107 may be set to be the same or different according to the actual requirements of the cycle parameters of the sar adc sampling clock 1003.
Preferably, the clock divider 3 is electrically connected to an output terminal of the clock delay 109, and an output terminal thereof is used for outputting the down-converted SARADC sampling clock 1004;
the clock frequency divider 3 is provided with a frequency division number adjustment register for adjusting the period of the down-conversion SARADC sampling clock 1004;
the apparatus further includes a counter for recording the number of down-converted SARADC sampling clocks 1004, and generating a complete level signal feedback to reset the first D flip-flop 102, the second D flip-flop 104, and the third D flip-flop 105 to zero when the number of down-converted SARADC sampling clocks 1004 meets the sampling requirement.
In the invention, the number of the down-conversion SARADC sampling clocks 1004 is recorded by setting the counter, and when the number of the down-conversion SARADC sampling clocks 1004 meets the sampling requirement, a completion level signal is generated to reset and clear the second D trigger 104 and the third D trigger 105, so that the power consumption of the device is saved.
In the invention, the period adjustment of the down-conversion SARADC sampling clock 1004 is more convenient and flexible by setting the frequency adjustment register.
The invention also provides a SARADC sampling clock generation method performed in the device, which comprises the following steps:
converting the external sampling pulse 1001 of SARADC to an enable logic level 1002;
the sampling clock generation circuit 2 is controlled by the enable logic level 1002 to generate an sar adc sampling clock 1003 having a fixed delay from the external sampling pulse 1001;
the sar adc sampling clock 1003 is fed to the clock divider 3, and the frequency division number is set to generate a down-converted sar adc sampling clock 1004.
According to the present invention, the enable logic level 1002 is generated by feeding an external sampling pulse 1001 of the SARADC into the edge detector, and controlling the set terminal of the D flip-flop through the edge detector;
the set ends of the two D flip-flops connected in a loop are controlled by the enable logic level 1002, the in-phase output signals of the two D flip-flops are respectively subjected to edge detection, and the generated two edge detection signals and the enable logic level 1002 are subjected to logic and operation to obtain the SARADC sampling clock 1003.
Preferably, the input clock of the D flip-flop that generates the enable logic level 1002 is the inverted sar adc sampling clock 1003;
the input clocks of the two D flip-flops connected in a loop are the SARADC sampling clocks 1003.
The invention will be described in more detail by means of a specific example.
Example 1
As shown in fig. 1, the present embodiment provides an sar adc sampling clock generating apparatus, as shown in fig. 1, including:
an enable signal generating circuit 1 for converting an external sampling pulse 1001 of the sar adc into an enable logic level 1002;
a sampling clock generation circuit 2 electrically connected to the enable signal generation circuit 1, the sampling clock generation circuit 2 being configured to generate a sar adc sampling clock 1003 having a fixed delay with respect to the external sampling pulse 1001, and the operation state thereof being controlled by an enable logic level 1002;
a clock divider 3 electrically connected to an output terminal of the sampling clock generation circuit 2 and configured to generate a down-conversion SARADC sampling clock 1004 by setting a division number;
the enable signal generation circuit 1 includes a first edge detector 101, a first D flip-flop 102, and an inverter 103;
the input end of the first edge detector 101 is electrically connected with the external sampling pulse 1001, and the output end is electrically connected with the set end of the first D trigger 102;
the input end of the inverter 103 is electrically connected with the SARADC sampling clock 1003, and the output end is electrically connected with the clock input end of the first D trigger 102;
the sampling clock generation circuit 2 includes a second edge detector 106, a second D flip-flop 104, a third edge detector 107, and a third D flip-flop 105;
the inverting output terminal of the third D flip-flop 105 is electrically connected to the signal input terminal of the second D flip-flop 104;
the clock input ends of the second D trigger 104 and the third D trigger 105 are electrically connected with the SARADC sampling clock 1003, and the setting end is electrically connected with the in-phase output end of the first D trigger 102;
the non-inverting output ends of the second D trigger 104 and the third D trigger 105 are respectively and electrically connected with the input ends of the second edge detector 106 and the third edge detector 107;
the sampling clock generation circuit 2 further includes a three-input and gate 108 and a clock delay 109;
the three input ends of the three-input AND gate 108 are respectively and electrically connected with the in-phase output end of the first D trigger 102, the second edge detector 106 and the output end of the third edge detector 107, and the output end is electrically connected with the input end of the clock delay 109;
the output terminal of the clock delay 109 is used for outputting the SARADC sampling clock 1003;
the signal input of the first D flip-flop 102 is electrically connected to a logic low 1005;
the in-phase output of the second D flip-flop is also electrically connected to the signal input of the third D flip-flop 105;
the first edge detector 101, the second edge detector 106, and the third edge detector 107 each include an edge delay and an exclusive or gate;
the input end of each edge detector is electrically connected with the input end of the edge delay and one input end of the exclusive-OR gate, the output end of the edge delay is electrically connected with the other input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is the output end of the edge detector;
the delay parameters of the edge delays of the edge detectors in this embodiment are the same;
the clock divider 3 is electrically connected to the output terminal of the clock delay 109, and the output terminal thereof is used for outputting the down-converted SARADC sampling clock 1004;
the clock frequency divider 3 is provided with a frequency division number adjustment register for adjusting the period of the down-conversion SARADC sampling clock 1004;
the apparatus of (2) further comprises a counter for recording the number of down-converted SARADC sampling clocks 1004, and generating a complete level signal feedback to reset the first D flip-flop 102, the second D flip-flop 104 and the third D flip-flop 105 to zero when the number of down-converted SARADC sampling clocks 1004 meets the sampling requirement.
The embodiment provides a SARADC sampling clock generation method, which comprises the following steps:
converting the external sampling pulse 1001 of SARADC to an enable logic level 1002;
the sampling clock generation circuit 2 is controlled by the enable logic level 1002 to generate an sar adc sampling clock 1003 having a fixed delay from the external sampling pulse 1001;
the SARADC sampling clock 1003 is sent to the clock frequency divider 3, and a frequency division number is set to generate a down-conversion SARADC sampling clock 1004;
the enable logic level 1002 is generated by feeding an external sampling pulse 1001 of the sar adc into the edge detector, and controlling the set terminal of the D flip-flop by the edge detector;
the set ends of the two D flip-flops connected in a loop are controlled by the enable logic level 1002, the in-phase output signals of the two D flip-flops are respectively subjected to edge detection, and the generated two edge detection signals and the enable logic level 1002 are subjected to logic and operation to obtain the SARADC sampling clock 1003.
An SARADC sampling clock 1003 that generates an inverted input clock of the D flip-flop that enables the logic level 1002;
the input clocks of the two D flip-flops connected in a loop are the SARADC sampling clocks 1003. The SARADC sampling clock generating device provided in the present embodiment controls the sampling clock generating circuit 2 with the enable logic level 1002, generates the SARADC sampling clock 1003 with a fixed delay for the external sampling pulse 1001, and generates the period-adjustable down-conversion SARADC sampling clock 1004 with the clock divider 3.
The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.
Claims (10)
1. An sar adc sampling clock generating apparatus, comprising:
an enable signal generating circuit for converting an external sampling pulse of the SARADC into an enable logic level;
the sampling clock generation circuit is electrically connected with the enabling signal generation circuit and is used for generating an SARADC sampling clock with fixed delay with the external sampling pulse, and the working state of the sampling clock generation circuit is controlled by the enabling logic level;
and the clock frequency divider is electrically connected with the output end of the sampling clock generation circuit and is used for generating a down-conversion SARADC sampling clock by setting a frequency division number.
2. The apparatus of claim 1, wherein the enable signal generation circuit comprises a first edge detector, a first D flip-flop, and an inverter;
the input end of the first edge detector is electrically connected with the external sampling pulse, and the output end of the first edge detector is electrically connected with the setting end of the first D trigger;
the input end of the inverter is electrically connected with the SARADC sampling clock, and the output end of the inverter is electrically connected with the clock input end of the first D trigger.
3. The apparatus of claim 2, wherein the sampling clock generation circuit comprises a second edge detector, a second D flip-flop, a third edge detector, a third D flip-flop;
the inverting output end of the third D trigger is electrically connected with the signal input end of the second D trigger;
the clock input ends of the second D trigger and the third D trigger are electrically connected with the SARADC sampling clock, and the setting end is electrically connected with the in-phase output end of the first D trigger;
and the in-phase output ends of the second D trigger and the third D trigger are respectively and electrically connected with the input ends of the second edge detector and the third edge detector.
4. The apparatus of claim 3 wherein the sample clock generation circuit further comprises a three-input and gate and a clock delay;
the three input ends of the three-input AND gate are respectively and electrically connected with the in-phase output end of the first D trigger, the output ends of the second edge detector and the third edge detector, and the output ends are electrically connected with the input end of the clock delay device;
the output end of the clock delay device is used for outputting the SARADC sampling clock.
5. The apparatus of claim 4, wherein the signal input of the first D flip-flop is electrically connected to a logic low level;
and the in-phase output end of the second D trigger is also electrically connected with the signal input end of the third D trigger.
6. The apparatus of claim 5, wherein the first edge detector, the second edge detector, and the third edge detector each comprise an edge retarder and an exclusive-or gate;
the input end of each edge detector is electrically connected with the input end of the edge delay device and one input end of the exclusive-OR gate, the output end of the edge delay device is electrically connected with the other input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is the output end of the edge detector.
7. The apparatus of claim 6, wherein the clock divider is electrically connected to an output of the clock delay and an output thereof is configured to output a down-converted SARADC sampling clock;
the clock frequency divider is provided with a frequency division number adjusting register which is used for adjusting the period of the down-conversion SARADC sampling clock;
the device also comprises a counter, wherein the counter is used for recording the number of the down-conversion SARADC sampling clocks, and when the number of the down-conversion SARADC sampling clocks meets the sampling requirement, the device generates a complete level signal feedback to reset and clear the first D trigger, the second D trigger and the third D trigger.
8. A method of generating a sar adc sampling clock in an apparatus according to any one of claims 1 to 7, comprising the steps of:
converting the external sampling pulse of the SARADC to an enable logic level;
controlling a sampling clock generation circuit through the enabling logic level to generate an SARADC sampling clock with fixed delay with the external sampling pulse;
and sending the SARADC sampling clock to a clock frequency divider, and setting the frequency division number to generate a down-conversion SARADC sampling clock.
9. The method of claim 8, wherein the enabling logic level is generated by feeding an external sampling pulse of the sar adc into an edge detector, and controlling a set terminal of a D flip-flop by the edge detector;
and controlling the set ends of the two D flip-flops connected into a loop through the enabling logic level, respectively carrying out edge detection on in-phase output signals of the two D flip-flops, and carrying out logic AND operation on the generated two edge detection signals and the enabling logic level to obtain the SARADC sampling clock.
10. The method of claim 9, wherein the input clock of the D flip-flop that generates the enable logic level is the SARADC sampling clock that is inverted;
the input clocks of the two D flip-flops connected in a loop are the SARADC sampling clocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311252962.1A CN116996071B (en) | 2023-09-27 | 2023-09-27 | SARADC sampling clock generation device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311252962.1A CN116996071B (en) | 2023-09-27 | 2023-09-27 | SARADC sampling clock generation device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116996071A true CN116996071A (en) | 2023-11-03 |
| CN116996071B CN116996071B (en) | 2023-12-22 |
Family
ID=88532527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311252962.1A Active CN116996071B (en) | 2023-09-27 | 2023-09-27 | SARADC sampling clock generation device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116996071B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060181311A1 (en) * | 2005-01-20 | 2006-08-17 | Stmicroelectronics S.R.L. | Circuit for generating an internal enabling signal for an output buffer of a memory |
| US20090322385A1 (en) * | 2008-06-27 | 2009-12-31 | Anton Rozen | Device having clock generating capabilities and a method for generating a clock signal |
| CN201690355U (en) * | 2010-03-11 | 2010-12-29 | Bcd半导体制造有限公司 | External clock synchronous device of switching power supply |
| CN106342405B (en) * | 2010-09-14 | 2014-05-14 | 中国航空工业集团公司雷华电子技术研究所 | Digital radar frequency synthesizer controls pulse-generating circuit |
| CN105406868A (en) * | 2014-09-05 | 2016-03-16 | 德州仪器公司 | Adaptive Clocking For Analog-to-digital Conversion |
| CN109387776A (en) * | 2017-08-03 | 2019-02-26 | 三星电子株式会社 | Measure method, clock jitter measuring circuit and the semiconductor device of clock jitter |
| CN113497620A (en) * | 2020-04-06 | 2021-10-12 | 円星科技股份有限公司 | Clock data recovery circuit and multiplexer circuit |
| CN113608600A (en) * | 2020-05-04 | 2021-11-05 | 意法半导体国际有限公司 | Method and apparatus for data synchronization in a system having multiple clock domains and reset domains |
| CN114121132A (en) * | 2020-08-31 | 2022-03-01 | 长鑫存储技术(上海)有限公司 | Test circuit, test device and test method thereof |
| CN114301460A (en) * | 2021-12-31 | 2022-04-08 | 西安开阳微电子有限公司 | Clock generation circuit and clock calibration method |
| CN115240731A (en) * | 2022-08-01 | 2022-10-25 | 长鑫存储技术有限公司 | Control circuit of delay-locked loop circuit and memory |
| CN115347867A (en) * | 2021-05-13 | 2022-11-15 | 三星电子株式会社 | Clock generation circuit and wireless communication device including the same |
| CN116667843A (en) * | 2023-06-19 | 2023-08-29 | 河南矽思微电子有限公司 | Multi-phase serial data sampling clock signal generating circuit |
-
2023
- 2023-09-27 CN CN202311252962.1A patent/CN116996071B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060181311A1 (en) * | 2005-01-20 | 2006-08-17 | Stmicroelectronics S.R.L. | Circuit for generating an internal enabling signal for an output buffer of a memory |
| US20090322385A1 (en) * | 2008-06-27 | 2009-12-31 | Anton Rozen | Device having clock generating capabilities and a method for generating a clock signal |
| CN201690355U (en) * | 2010-03-11 | 2010-12-29 | Bcd半导体制造有限公司 | External clock synchronous device of switching power supply |
| CN106342405B (en) * | 2010-09-14 | 2014-05-14 | 中国航空工业集团公司雷华电子技术研究所 | Digital radar frequency synthesizer controls pulse-generating circuit |
| CN105406868A (en) * | 2014-09-05 | 2016-03-16 | 德州仪器公司 | Adaptive Clocking For Analog-to-digital Conversion |
| CN109387776A (en) * | 2017-08-03 | 2019-02-26 | 三星电子株式会社 | Measure method, clock jitter measuring circuit and the semiconductor device of clock jitter |
| CN113497620A (en) * | 2020-04-06 | 2021-10-12 | 円星科技股份有限公司 | Clock data recovery circuit and multiplexer circuit |
| CN113608600A (en) * | 2020-05-04 | 2021-11-05 | 意法半导体国际有限公司 | Method and apparatus for data synchronization in a system having multiple clock domains and reset domains |
| CN114121132A (en) * | 2020-08-31 | 2022-03-01 | 长鑫存储技术(上海)有限公司 | Test circuit, test device and test method thereof |
| CN115347867A (en) * | 2021-05-13 | 2022-11-15 | 三星电子株式会社 | Clock generation circuit and wireless communication device including the same |
| CN114301460A (en) * | 2021-12-31 | 2022-04-08 | 西安开阳微电子有限公司 | Clock generation circuit and clock calibration method |
| CN115240731A (en) * | 2022-08-01 | 2022-10-25 | 长鑫存储技术有限公司 | Control circuit of delay-locked loop circuit and memory |
| CN116667843A (en) * | 2023-06-19 | 2023-08-29 | 河南矽思微电子有限公司 | Multi-phase serial data sampling clock signal generating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116996071B (en) | 2023-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101019035B (en) | Precise time measurement apparatus and method | |
| US10234483B2 (en) | Sampling circuit, sampling method, sampling oscilloscope, and waveform display method | |
| JP2001289892A (en) | Method and device for measuring jitter | |
| JP4565992B2 (en) | DDS circuit with arbitrary frequency control clock | |
| CN111766771A (en) | Voltage-controlled crystal oscillator taming-based time interval measuring method and system | |
| CN220207786U (en) | Delay deviation measuring circuit | |
| JPH10232818A (en) | Memory controller | |
| CN116996071B (en) | SARADC sampling clock generation device and method | |
| CN112433469B (en) | 1PPS time synchronization system and method based on feedback mechanism | |
| CN115580275B (en) | High-precision pulse signal generating device, FPGA chip and signal processing equipment | |
| JP2000221248A (en) | Semiconductor testing device | |
| US7242341B2 (en) | Analog-to-digital converter and analog-to-digital conversion method | |
| CN109547024B (en) | Multi-signal detection method and detection control device | |
| CN109976134B (en) | High-stability time measurement circuit system and measurement method thereof | |
| US6944099B1 (en) | Precise time period measurement | |
| CN112286841B (en) | Data synchronization method and register | |
| EP1322969B1 (en) | Rf power measurement | |
| JP2007040742A (en) | Jitter measuring device | |
| JP2016095175A (en) | Test device of semiconductor integrated circuit, test system, and test method | |
| CN209805784U (en) | pulse power calibration device | |
| JPH05128061A (en) | Interface circuit | |
| JP2004279155A (en) | Jitter tester using sampling digitizer, method and semiconductor tester with sampling digitizer | |
| CN112858780A (en) | Method, device and system for measuring crystal oscillation frequency | |
| CN116915219A (en) | Self-test system for multichannel TDC | |
| JP4857575B2 (en) | Pulse radar equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |