CN116667843A - Multi-phase serial data sampling clock signal generating circuit - Google Patents
Multi-phase serial data sampling clock signal generating circuit Download PDFInfo
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- CN116667843A CN116667843A CN202310720226.8A CN202310720226A CN116667843A CN 116667843 A CN116667843 A CN 116667843A CN 202310720226 A CN202310720226 A CN 202310720226A CN 116667843 A CN116667843 A CN 116667843A
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- 238000001514 detection method Methods 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a generating circuit of a multiphase serial data sampling clock signal, which belongs to the technical field of frequency division circuits and comprises a four-phase clock signal generating circuit, a first-phase clock signal generating circuit, a second-phase clock signal generating circuit, a third-phase clock signal generating circuit and a fourth-phase clock signal generating circuit, wherein the four-phase clock signal generating circuit is used for generating a first-phase clock signal, a second-phase clock signal, a third-phase clock signal and a fourth-phase clock signal; a first four-phase selector, wherein the input end is respectively input with a first phase clock signal, a second phase clock signal, a third phase clock signal and a fourth phase clock signal, the control end is respectively input with a first bit control signal and a second bit control signal, and the output end is used for outputting the first clock signal; a second selector; a first sampling circuit; a second sampling circuit; a third sampling circuit; a fourth sampling circuit; a fifth sampling circuit; a sixth sampling circuit; a second fourth selector; a first divide by four circuit; and a second divide by four circuit. The invention has simple structure, fewer signals are used, the logic circuit is more convenient to realize, the power consumption is lower, the area required by the layout is smaller, and the cost can be reduced.
Description
Technical Field
The present invention relates to frequency dividing circuits, and more particularly to a circuit for generating a multi-phase serial data sampling clock signal.
Background
In a mobile industry processor interface (mipi-LVDS) of low voltage differential signals and a Camera/Display interface (LVDS Camera/Display) application of low voltage differential signals, it is required to output a clock with 16 selectable gears phase within 1 bit data period. For example, serial data rates up to 1Gbps, then a 1 ns/16=62.5 ps step adjustment is required.
Typically at a serial data rate of 1Gbps, the prior art generates a 4GHz 4-phase clock by a Phase Locked Loop (PLL), then generates a 4GHz multiphase clock by corresponding logic circuitry, samples the double data rate clock using the 4GHz multiphase clock, and gates the required phase clock. However, the circuit structure of the method in the prior art is complex, the power consumption is large, the area of the layout realization is large, and the cost is high.
Disclosure of Invention
The invention aims at: the generation circuit of the multiphase serial data sampling clock signal can output 16 sampling clocks with selectable gears, so that the function that 16 sampling clocks with selectable gears are phased in a 1-bit data period is realized.
The invention is realized by the following technical scheme:
a circuit for generating a multi-phase serial data sampling clock signal, comprising:
a four-phase clock signal generation circuit for generating a first phase clock signal, a second phase clock signal, a third phase clock signal, and a fourth phase clock signal; the first phase clock signal and the third phase clock signal are a pair of differential clock signals, and the second phase clock signal and the fourth phase clock signal are another pair of differential clock signals;
the first four-phase selector is characterized in that the input end of the first four-phase selector is respectively input with a first phase clock signal, a second phase clock signal, a third phase clock signal and a fourth phase clock signal, the control end of the first four-phase selector is respectively input with a first bit control signal and a second bit control signal, and the output end of the first four-phase selector is output with the first clock signal;
the input end of the two-phase selector is respectively input with a second phase clock signal and a fourth phase clock signal, the control end of the two-phase selector is input with a second bit control signal, and the output end of the two-phase selector outputs the second clock signal;
the first sampling circuit is used for sampling the third clock signal by the fourth phase clock signal to obtain a fourth clock signal;
the second sampling circuit is used for sampling the fourth clock signal by the second clock signal to obtain a fifth clock signal;
a third sampling circuit for sampling the fifth clock signal by the first clock signal to obtain a sixth clock signal;
a fourth sampling circuit for sampling the sixth clock signal by the first clock signal to obtain a seventh clock signal;
a fifth sampling circuit for sampling the seventh clock signal by the first clock signal to obtain an eighth clock signal;
a sixth sampling circuit for sampling the eighth clock signal by the first clock signal to obtain a ninth clock signal;
a second fourth selector, the input end of which is respectively input with a sixth clock signal, a seventh clock signal, an eighth clock signal and a ninth clock signal, the control end of which is respectively input with a third bit control signal and a fourth bit control signal, and the output end of which is output with a switch control signal;
the first four-frequency dividing circuit is used for carrying out four-frequency division on the first clock signal under the control of the switch control signal to obtain a first frequency dividing signal;
the second four-frequency dividing circuit is used for performing four-frequency division on the first frequency dividing signal under the control of the switch control signal to obtain a second frequency dividing signal;
the circuit control signals comprise four-bit control signals, wherein the four-bit control signals are the first-bit control signal, the second-bit control signal, the third-bit control signal and the fourth-bit control signal respectively.
The four-phase clock signal generating circuit is a voltage-controlled oscillator.
The first sampling circuit, the second sampling circuit, the third sampling circuit, the fourth sampling circuit, the fifth sampling circuit and the sixth sampling circuit are all D triggers.
The third clock signal is generated by a lock detection circuit.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention has simple structure, fewer signals are used, the logic circuit is more convenient to realize, the power consumption is lower, the area required by the layout is smaller, and the cost can be reduced.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
fig. 2 is a signal timing diagram of phase_sel < 3:0 > =0000.
Detailed Description
All the features disclosed in this specification, or the steps of all methods or processes disclosed, except for the mutually exclusive features and/or steps, may be combined in any combination, unless specifically stated otherwise, with other equivalents or alternatives having a similar purpose, i.e., each feature is one embodiment of a series of equivalents or similar features, unless specifically stated otherwise.
Referring to fig. 1, a generating circuit of a multiphase serial data sampling clock signal of the present invention includes a four-phase clock signal generating circuit, a first one-out-of-four selector mux1, a second one-out-of-four selector mux3, a first sampling circuit D1, a second sampling circuit D2, a third sampling circuit D3, a fourth sampling circuit D4, a fifth sampling circuit D5, a sixth sampling circuit D6, a second one-out-of-four selector mux2, a first divide-by-four circuit and a second divide-by-four circuit.
The four-phase clock signal generating circuit is used for generating a first-phase clock signal ck1, a second-phase clock signal ck2, a third-phase clock signal ck3 and a fourth-phase clock signal ck4. The first phase clock signal ck1 and the third phase clock signal ck3 are a pair of differential clock signals, and the second phase clock signal ck2 and the fourth phase clock signal ck4 are another pair of differential clock signals. In the embodiment shown in fig. 1, the four-phase clock signal generating circuit is a voltage-controlled oscillator. The frequencies of the first phase clock signal ck1, the second phase clock signal ck2, the third phase clock signal ck3 and the fourth phase clock signal ck4 are determined according to the serial data rate, and have specific multiple relations, for example, the frequencies of the first phase clock signal ck1, the second phase clock signal ck2, the third phase clock signal ck3 and the fourth phase clock signal ck4 can be four times the serial data rate, for example, the serial data rate is less than or equal to 1Gbps, and then the frequencies of the first phase clock signal ck1, the second phase clock signal ck2, the third phase clock signal ck3 and the fourth phase clock signal ck4 are determined by taking the highest serial data rate 1Gbps as a standard, namely, the frequencies of the first phase clock signal ck1, the second phase clock signal ck2, the third phase clock signal ck3 and the fourth phase clock signal ck4 are 4GHz.
The input terminal of the first four-way selector mux1 is respectively input with a first PHASE clock signal ck1, a second PHASE clock signal ck2, a third PHASE clock signal ck3 and a fourth PHASE clock signal ck4, the control terminal of the first four-way selector mux1 is respectively input with a first bit control signal phase_sel (0) and a second bit control signal phase_sel (1), and the output terminal of the first four-way selector mux1 outputs a first clock signal ckn. In FIG. 1, the PHASE_SEL < 1:0 > signals are the first bit control signal PHASE_SEL < 0 > and the second bit control signal PHASE_SEL < 1 >.
The input terminal of the alternative selector mux3 inputs the second PHASE clock signal ck2 and the fourth PHASE clock signal ck4, respectively, the control terminal of the alternative selector mux3 inputs the second bit control signal phase_sel (1), and the output terminal of the alternative selector mux3 outputs the second clock signal ckm.
The first sampling circuit D1 is configured to sample the third clock signal LCK by the fourth phase clock signal ck4 to obtain a fourth clock signal LOCK.
The second sampling circuit D2 is configured to sample the fourth clock signal LOCK by the second clock signal ckm to obtain a fifth clock signal rstn_pre.
The third sampling circuit D3 is configured to sample the fifth clock signal rstn_pre by using the first clock signal ckn to obtain a sixth clock signal q0.
The fourth sampling circuit D4 is configured to sample the sixth clock signal q0 by the first clock signal ckn to obtain a seventh clock signal q1.
The fifth sampling circuit D5 is configured to sample the seventh clock signal q1 by using the first clock signal ckn to obtain an eighth clock signal q2.
The sixth sampling circuit D6 is configured to sample the eighth clock signal q2 by the first clock signal ckn to obtain a ninth clock signal q3.
The input terminal of the second one-out-of-four selector mux2 is respectively input with a sixth clock signal q0, a seventh clock signal q1, an eighth clock signal q2 and a ninth clock signal q3, the control terminal of the second one-out-of-four selector mux2 is respectively input with a third bit control signal phase_sel (2) and a fourth bit control signal phase_sel (3), and the output terminal of the second one-out-of-four selector mux2 outputs a switch control signal rstn. In FIG. 1, the phase_SEL < 3:2 > signals are the third bit control signal phase_SEL < 2 > and the fourth bit control signal phase_SEL < 3 >.
The first divide-by-four circuit divides the first clock signal ckn by four under the control of the switch control signal rstn to obtain a first divided signal CKSEL.
The second divide-by-four circuit divides the first divided signal CKSEL by four under the control of the switch control signal rstn to obtain a second divided signal PCK.
In FIG. 1, the circuit control signals PHASE_SEL (3:0)) include four-bit control signals, which are respectively a first bit control signal PHASE_SEL (0)), a second bit control signal PHASE_SEL (1), a third bit control signal PHASE_SEL (2), and a fourth bit control signal PHASE_SEL (3). For example, when phase_sel < 0 > = 0, phase_sel < 1 > = 1, phase_sel < 2 > = 0, phase_sel < 3 > = 1, phase_sel < 3:0 > = 1010; when phase_sel < 0 > =1, phase_sel < 1 > =1, phase_sel < 2 > =0, phase_sel < 3 > =1, phase_sel < 3:0 > =1011; and others so on.
In the foregoing embodiment, the first sampling circuit D1, the second sampling circuit D2, the third sampling circuit D3, the fourth sampling circuit D4, the fifth sampling circuit D5, and the sixth sampling circuit D6 are all D flip-flops.
In the foregoing embodiment, the third clock signal LCK is generated by the lock detection circuit.
The working principle of the invention is as follows:
referring to fig. 1, four-phase clocks with a frequency of 4GHz are generated from a voltage-controlled oscillator, namely a first-phase clock signal ck1, a second-phase clock signal ck2, a third-phase clock signal ck3 and a fourth-phase clock signal ck4, wherein the first-phase clock signal ck1 and the third-phase clock signal ck3 are a pair of differential clock signals, and the second-phase clock signal ck2 and the second-phase clock signal ck4 are another pair of differential clock signals.
Referring to fig. 1 and 2, the first PHASE clock signal ck1, the second PHASE clock signal ck2, the third PHASE clock signal ck3 and the fourth PHASE clock signal ck4 are respectively input into the first fourth selector mux1, and the second PHASE control signal phase_sel < 1 >, the first PHASE control signal phase_sel < 0 >, i.e. phase_sel < 1:0 >, control the output of the first fourth selector mux1, and the output end of the first fourth selector mux1 outputs the first clock signal ckn. For example, when phase_sel < 1 > = 1, phase_sel < 0 > = 1, i.e. phase_sel < 1:0 > = 11, the first PHASE clock signal ck1 output from the output terminal of the first one-out-of-four selector mux1 is used as the first clock signal ckn; when phase_sel < 1:0 > =10, the second PHASE clock signal ck2 output from the output terminal of the first one-out-of-four selector mux1 is taken as the first clock signal ckn; when phase_sel < 1:0 > =01, the third PHASE clock signal ck3 output from the output terminal of the first one-out-of-four selector mux1 is taken as the first clock signal ckn; when phase_sel < 1:0 > =00, the fourth PHASE clock signal ck4 output from the output terminal of the first one-out-of-four selector mux1 is taken as the first clock signal ckn.
The second PHASE clock signal ck2 and the fourth PHASE clock signal ck4 are input into the alternative selector mux3, the alternative selector mux3 is controlled to output by the second bit control signal phase_sel (1), and the output end of the alternative selector mux3 outputs the second clock signal ckm. For example, when phase_sel < 1 > =1, the second PHASE clock signal ck2 output from the output terminal of the alternative selector mux3 is taken as the second clock signal ckm; when phase_sel < 1 > =0, the output terminal of the alternative selector mux3 outputs the fourth PHASE clock signal ck4 as the second clock signal ckm. The fourth phase clock signal ck4 is input to the first sampling circuit D1, and the third clock signal LCK is sampled to obtain a fourth clock signal LOCK. The second clock signal ckm is input to the second sampling circuit D2, and the fourth clock signal LOCK signal is sampled to obtain a fourth fifth clock signal rstn_pre. Thus, the second clock signal ckm and the fifth clock signal rstn_pre have a timing relationship.
Then, the first clock signal ckn is input to the third sampling circuit D3, and the fifth clock signal rstn_pre is sampled to obtain a sixth clock signal q0; the first clock signal ckn is input to the fourth sampling circuit D4, and the sixth clock signal q0 is sampled by the first clock signal ckn to obtain a seventh clock signal q1; the first clock signal ckn is input to the fifth sampling circuit D5, and the seventh clock signal q1 is sampled by the first clock signal ckn to obtain an eighth clock signal q2; the first clock signal ckn is input to the sixth sampling circuit D6, and the eighth clock signal q2 is sampled by the first clock signal ckn to obtain a ninth clock signal q3. The sixth clock signal q0, the seventh clock signal q1, the eighth clock signal q2, and the ninth clock signal q3 thus generated are each phase-shifted by one Tckn, where Tckn represents the period of the first clock signal ckn. The sixth clock signal q0, the seventh clock signal q1, the eighth clock signal q2 and the ninth clock signal q3 are input into the second one-out-of-four selector mux2, the second one-out-of-four selector mux2 is controlled to output by the fourth bit phase_sel (3) and the third bit control signal phase_sel (2), i.e. phase_sel (3: 2), and the output end of the second one-out-of-four selector mux2 outputs the switch control signal rstn. For example, when phase_sel < 3:2 > =11, the output terminal of the second one-out-of-four selector mux2 outputs the ninth clock signal q3; when phase_sel < 3:2 > = 10, the output terminal of the second one-out-of-four selector mux2 outputs the eighth clock signal q2; when phase_sel < 3:2 > =01, the output terminal of the second one-out-of-four selector mux2 outputs the seventh clock signal q1; when phase_sel < 3:2 > =00, the output terminal of the second one-out-of-four selector mux2 outputs the sixth clock signal q0.
The first clock signal ckn is input to a first divide-by-four circuit, which divides the first clock signal ckn by four under the control of the switch control signal rstn to obtain a first divided signal CKSEL; the first frequency division signal CKSEL is input to a second four frequency division circuit, which performs four frequency division on the first frequency division signal CKSEL under the control of the switch control signal rstn to obtain a second frequency division signal PCK. The second divided signal PCK is the clock signal finally output by the present invention. Thus, by selecting the circuit control signals PHASE_SEL < 3:0 >, the second divided signal PCK with 16 selectable shift PHASEs in 1 bit data period can be obtained, and the second divided signal PCK is the required double data rate Clock (DDR Clock). In fig. 2, data refers to serial data, and a portion indicated by a dotted arrow is a one-bit data period. The dashed arrow indicates 16 PHASEs of the second divided signal PCK by dashed lines, and the second divided signal PCK with different PHASEs is selected to be outputted by the circuit control signal PHASE_SEL (3:0).
Therefore, the invention only uses 6D flip-flops, 2 one-out-of-four selectors, 1 one-out-of-two selector and 2 four frequency dividing circuits, has simple and clear structure, does not relate to complex logic transformation, and has clear and understandable signal paths. The logic devices used are fewer, the clock frequency is not high, so that the generated power consumption is smaller, the occupied area of the layout corresponding to the whole invention is smaller, and the cost can be reduced.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.
Claims (4)
1. A circuit for generating a multi-phase serial data sampling clock signal, comprising:
a four-phase clock signal generation circuit for generating a first phase clock signal (ck 1), a second phase clock signal (ck 2), a third phase clock signal (ck 3), and a fourth phase clock signal (ck 4); wherein the first phase clock signal (ck 1) and the third phase clock signal (ck 3) are a pair of differential clock signals, and the second phase clock signal (ck 2) and the fourth phase clock signal (ck 4) are another pair of differential clock signals;
a first four-way selector (mux 1) having input terminals respectively for inputting a first PHASE clock signal (ck 1), a second PHASE clock signal (ck 2), a third PHASE clock signal (ck 3) and a fourth PHASE clock signal (ck 4), control terminals respectively for inputting a first bit control signal (phase_sel (0)) and a second bit control signal (phase_sel (1)) and output terminals for outputting a first clock signal (ckn);
a selector (mux 3) having an input terminal for inputting a second PHASE clock signal (ck 2) and a fourth PHASE clock signal (ck 4), a control terminal for inputting a second PHASE control signal (phase_sel (1)) and an output terminal for outputting a second clock signal (ckm);
a first sampling circuit (D1) for sampling the third clock signal (LCK) by a fourth phase clock signal (ck 4) to obtain a fourth clock signal (LOCK);
a second sampling circuit (D2) for sampling the fourth clock signal (LOCK) by the second clock signal (ckm) to obtain a fifth clock signal (rstn_pre);
a third sampling circuit (D3) for sampling the fifth clock signal (rstn_pre) by the first clock signal (ckn) to obtain a sixth clock signal (q 0);
a fourth sampling circuit (D4) for sampling the sixth clock signal (q 0) by the first clock signal (ckn) to obtain a seventh clock signal (q 1);
a fifth sampling circuit (D5) for sampling the seventh clock signal (q 1) by the first clock signal (ckn) to obtain an eighth clock signal (q 2);
a sixth sampling circuit (D6) for sampling the eighth clock signal (q 2) by the first clock signal (ckn) to obtain a ninth clock signal (q 3);
a second four-way selector (mux 2) having input terminals respectively inputting a sixth clock signal (q 0), a seventh clock signal (q 1), an eighth clock signal (q 2) and a ninth clock signal (q 3), having control terminals respectively inputting a third bit control signal (phase_sel (2)) and a fourth bit control signal (phase_sel (3)), and having output terminals outputting a switch control signal (rstn);
a first divide-by-four circuit that divides the first clock signal (ckn) by four under control of the switch control signal (rstn) to obtain a first divided signal (CKSEL);
a second divide-by-four circuit which divides the first divided signal (CKSEL) by four under the control of the switch control signal (rstn) to obtain a second divided signal (PCK);
the circuit control signals comprise four-bit control signals, wherein the four-bit control signals are the first bit control signal (PHASE_SEL < 0 >), the second bit control signal (PHASE_SEL < 1 >) and the third bit control signal (PHASE_SEL < 2 >) respectively.
2. The circuit for generating a multiphase serial data sampling clock signal according to claim 1, wherein the four-phase clock signal generating circuit is a voltage controlled oscillator.
3. The circuit for generating the multiphase serial data sampling clock signal according to claim 1, wherein the first sampling circuit (D1), the second sampling circuit (D2), the third sampling circuit (D3), the fourth sampling circuit (D4), the fifth sampling circuit (D5) and the sixth sampling circuit (D6) are D flip-flops.
4. A generation circuit of a multi-phase serial data sampling clock signal according to any of claims 1-3, characterized in that the third clock signal (LCK) is generated by a lock detection circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310720226.8A CN116667843A (en) | 2023-06-19 | 2023-06-19 | Multi-phase serial data sampling clock signal generating circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310720226.8A CN116667843A (en) | 2023-06-19 | 2023-06-19 | Multi-phase serial data sampling clock signal generating circuit |
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| CN116667843A true CN116667843A (en) | 2023-08-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116996071A (en) * | 2023-09-27 | 2023-11-03 | 苏州领慧立芯科技有限公司 | SARADC sampling clock generation device and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116996071A (en) * | 2023-09-27 | 2023-11-03 | 苏州领慧立芯科技有限公司 | SARADC sampling clock generation device and method |
| CN116996071B (en) * | 2023-09-27 | 2023-12-22 | 苏州领慧立芯科技有限公司 | SARADC sampling clock generation device and method |
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